mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

merge AVX and SSE .bochsrc options to single SIMD option which will configure SSE and AVX together

Browse Source
This commit is contained in:
Stanislav Shwartsman 2013-09-16 19:50:36 +00:00
parent 1cebe5f83d
commit b6c39a3176
9 changed files with 76 additions and 79 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
bochs/.bochsrc
View File

@ -198,10 +198,13 @@ cpu: cpuid_limit_winnt=0
# Select SYSENTER/SYSEXIT instruction set support.
# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# SSE:
# Select SSE instruction set support.
# Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 could be selected.
# SIMD:
# Select SIMD instructions support.
# Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2/AVX/AVX2/AVX512
# could be selected.
#
# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
# The AVX choises exists only if Bochs compiled with --enable-avx option.
#
# SSE4A:
# Select AMD SSE4A instructions support.
@ -235,10 +238,6 @@ cpu: cpuid_limit_winnt=0
# Select XSAVEOPT instruction support.
# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# AVX:
# Select AVX/AVX2 instruction set support.
# This option exists only if Bochs compiled with --enable-avx option.
#
# AVX_F16C:
# Select AVX float16 convert instructions support.
# This option exists only if Bochs compiled with --enable-avx option.
@ -323,7 +322,7 @@ cpu: cpuid_limit_winnt=0
# STEPPING:
# Set stepping information returned by CPUID. Default stepping value is 3.
#=======================================================================
#cpuid: x86_64=1, mmx=1, sep=1, sse=sse4_2, apic=xapic, aes=1, movbe=1, xsave=1
#cpuid: x86_64=1, mmx=1, sep=1, simd=sse4_2, apic=xapic, aes=1, movbe=1, xsave=1
#cpuid: family=6, model=0x1a, stepping=5
#=======================================================================

9
bochs/PARAM_TREE.txt
View File

@ -37,9 +37,11 @@ cpuid
brand_string
mmx
sep
sse
simd
sse4a
misaligned_sse
avx_f16c
avx_fma
aes
sha
movbe
@ -48,13 +50,10 @@ cpuid
xsaveopt
svm
vmx
avx
avx_f16c
avx_fma
bmi
xop
tbm
fma4
tbm
apic
x86_64
1g_pages

29
bochs/config.cc
View File

@ -515,11 +515,27 @@ void bx_init_options()
#if BX_CPU_LEVEL >= 6
// configure defaults to CPU_LEVEL = 6 with SSE2 enabled
static const char *sse_names[] = { "none", "sse", "sse2", "sse3", "ssse3", "sse4_1", "sse4_2", NULL };
static const char *simd_names[] = {
"none",
"sse",
"sse2",
"sse3",
"ssse3",
"sse4_1",
"sse4_2",
#if BX_SUPPORT_AVX
"avx",
"avx2",
#if BX_SUPPORT_EVEX
"avx512",
#endif
#endif
NULL };
new bx_param_enum_c(cpuid_param,
"sse", "Support for SSE instruction set",
"Support for SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 instruction set",
sse_names,
"simd", "Support for SIMD instruction set",
"Support for SIMD (SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2/AVX/AVX2/AVX512) instruction set",
simd_names,
BX_CPUID_SUPPORT_SSE2,
BX_CPUID_SUPPORT_NOSSE);
@ -561,11 +577,6 @@ void bx_init_options()
"Support for XSAVEOPT instruction",
0);
#if BX_SUPPORT_AVX
new bx_param_num_c(cpuid_param,
"avx", "Support for AVX instruction set",
"Support for AVX instruction set",
0, 2,
0);
new bx_param_bool_c(cpuid_param,
"avx_f16c", "Support for AVX F16 convert instructions",
"Support for AVX F16 convert instructions",

50
bochs/cpu/generic_cpuid.cc
View File

@ -706,9 +706,15 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
}
#endif
static unsigned sse_enabled = SIM->get_param_enum(BXPN_CPUID_SSE)->get();
static unsigned simd_enabled = SIM->get_param_enum(BXPN_CPUID_SIMD)->get();
// determine SSE in runtime
switch (sse_enabled) {
switch (simd_enabled) {
#if BX_SUPPORT_AVX
case BX_CPUID_SUPPORT_AVX2:
features_bitmask |= BX_ISA_AVX2;
case BX_CPUID_SUPPORT_AVX:
features_bitmask |= BX_ISA_AVX;
#endif
case BX_CPUID_SUPPORT_SSE4_2:
features_bitmask |= BX_ISA_SSE4_2;
case BX_CPUID_SUPPORT_SSE4_1:
@ -726,7 +732,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
break;
};
if (sse_enabled) {
if (simd_enabled) {
if (mmx_enabled == 0 || cpu_level < 6 || BX_CPU_LEVEL < 6) {
BX_PANIC(("PANIC: SSE support requires P6 emulation with MMX enabled !"));
return;
@ -734,18 +740,18 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
}
// enable CLFLUSH only when SSE2 or higher is enabled
if (sse_enabled >= BX_CPUID_SUPPORT_SSE2)
if (simd_enabled >= BX_CPUID_SUPPORT_SSE2)
features_bitmask |= BX_ISA_CLFLUSH;
// enable POPCNT if SSE4.2 is enabled
if (sse_enabled >= BX_CPUID_SUPPORT_SSE4_2)
if (simd_enabled >= BX_CPUID_SUPPORT_SSE4_2)
features_bitmask |= BX_ISA_POPCNT;
static bx_bool sse4a_enabled = SIM->get_param_bool(BXPN_CPUID_SSE4A)->get();
if (sse4a_enabled) {
features_bitmask |= BX_ISA_SSE4A;
if (! sse_enabled) {
if (! simd_enabled) {
BX_PANIC(("PANIC: SSE4A require SSE to be enabled !"));
return;
}
@ -762,7 +768,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
if (xsave_enabled) {
features_bitmask |= BX_ISA_XSAVE;
if (! sse_enabled) {
if (! simd_enabled) {
BX_PANIC(("PANIC: XSAVE emulation requires SSE support !"));
return;
}
@ -783,7 +789,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
features_bitmask |= BX_ISA_AES_PCLMULQDQ;
// AES required 3-byte opcode (SSS3E support or more)
if (sse_enabled < BX_CPUID_SUPPORT_SSSE3) {
if (simd_enabled < BX_CPUID_SUPPORT_SSSE3) {
BX_PANIC(("PANIC: AES support requires SSSE3 or higher !"));
return;
}
@ -794,7 +800,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
features_bitmask |= BX_ISA_SHA;
// SHA required 3-byte opcode (SSS3E support or more)
if (sse_enabled < BX_CPUID_SUPPORT_SSSE3) {
if (simd_enabled < BX_CPUID_SUPPORT_SSSE3) {
BX_PANIC(("PANIC: SHA support requires SSSE3 or higher !"));
return;
}
@ -805,7 +811,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
features_bitmask |= BX_ISA_MOVBE;
// MOVBE required 3-byte opcode (SSS3E support or more)
if (sse_enabled < BX_CPUID_SUPPORT_SSSE3) {
if (simd_enabled < BX_CPUID_SUPPORT_SSSE3) {
BX_PANIC(("PANIC: MOVBE support requires SSSE3 or higher !"));
return;
}
@ -816,7 +822,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
features_bitmask |= BX_ISA_ADX;
// ADX required 3-byte opcode (SSS3E support or more)
if (sse_enabled < BX_CPUID_SUPPORT_SSSE3) {
if (simd_enabled < BX_CPUID_SUPPORT_SSSE3) {
BX_PANIC(("PANIC: ADX support requires SSSE3 or higher !"));
return;
}
@ -830,7 +836,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
features_bitmask |= BX_ISA_CMPXCHG16B | BX_ISA_RDTSCP | BX_ISA_LM_LAHF_SAHF;
if (sse_enabled < BX_CPUID_SUPPORT_SSE2) {
if (simd_enabled < BX_CPUID_SUPPORT_SSE2) {
BX_PANIC(("PANIC: x86-64 emulation requires SSE2 support !"));
return;
}
@ -858,10 +864,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
}
#if BX_SUPPORT_AVX
static unsigned avx_enabled = SIM->get_param_num(BXPN_CPUID_AVX)->get();
if (avx_enabled) {
features_bitmask |= BX_ISA_AVX;
if (simd_enabled >= BX_CPUID_SUPPORT_AVX) {
if (! xsave_enabled) {
BX_PANIC(("PANIC: AVX emulation requires XSAVE support !"));
return;
@ -871,14 +874,11 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
BX_PANIC(("PANIC: AVX emulation requires x86-64 support !"));
return;
}
if (avx_enabled >= 2)
features_bitmask |= BX_ISA_AVX2;
}
static bx_bool avx_f16c_enabled = SIM->get_param_bool(BXPN_CPUID_AVX_F16CVT)->get();
if (avx_f16c_enabled) {
if (! avx_enabled) {
if (simd_enabled < BX_CPUID_SUPPORT_AVX) {
BX_PANIC(("PANIC: Float16 convert emulation requires AVX support !"));
return;
}
@ -888,7 +888,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
static bx_bool avx_fma_enabled = SIM->get_param_bool(BXPN_CPUID_AVX_FMA)->get();
if (avx_fma_enabled) {
if (avx_enabled < 2) {
if (simd_enabled < BX_CPUID_SUPPORT_AVX2) {
BX_PANIC(("PANIC: FMA emulation requires AVX2 support !"));
return;
}
@ -900,7 +900,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
if (bmi_enabled) {
features_bitmask |= BX_ISA_BMI1 | BX_ISA_LZCNT;
if (! avx_enabled) {
if (simd_enabled < BX_CPUID_SUPPORT_AVX) {
BX_PANIC(("PANIC: Bit Manipulation Instructions (BMI) emulation requires AVX support !"));
return;
}
@ -911,7 +911,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
static bx_bool fma4_enabled = SIM->get_param_bool(BXPN_CPUID_FMA4)->get();
if (fma4_enabled) {
if (! avx_enabled) {
if (simd_enabled < BX_CPUID_SUPPORT_AVX) {
BX_PANIC(("PANIC: FMA4 emulation requires AVX support !"));
return;
}
@ -921,7 +921,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
static bx_bool xop_enabled = SIM->get_param_bool(BXPN_CPUID_XOP)->get();
if (xop_enabled) {
if (! avx_enabled) {
if (simd_enabled < BX_CPUID_SUPPORT_AVX) {
BX_PANIC(("PANIC: XOP emulation requires AVX support !"));
return;
}
@ -931,7 +931,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
static bx_bool tbm_enabled = SIM->get_param_bool(BXPN_CPUID_TBM)->get();
if (tbm_enabled) {
if (! avx_enabled || ! xop_enabled) {
if (simd_enabled < BX_CPUID_SUPPORT_AVX || ! xop_enabled) {
BX_PANIC(("PANIC: TBM emulation requires AVX and XOP support !"));
return;
}

12
bochs/doc/docbook/user/user.dbk
View File

@ -3338,11 +3338,12 @@ This option exists only if Bochs compiled with BX_CPU_LEVEL >= 5.
Select SYSENTER/SYSEXIT instruction set support.
This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
</para>
<para><command>sse</command></para>
<para><command>simd</command></para>
<para>
Select SSE instruction set support.
Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 could be selected.
Select SIMD instructions support.
Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2/AVX/AVX2/AVX512 could be selected.
This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
The AVX choises exists only if Bochs compiled with --enable-avx option.
</para>
<para><command>sse4a</command></para>
<para>
@ -3384,11 +3385,6 @@ This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
Select XSAVEOPT instruction support.
This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
</para>
<para><command>avx</command></para>
<para>
Select AVX/AVX2 instruction set support.
This option exists only if Bochs compiled with <option>--enable-avx</option> option.
</para>
<para><command>avx_f16c</command></para>
<para>
Select AVX float16 convert instructions support.

14
bochs/doc/man/bochsrc.5
View File

@ -249,11 +249,14 @@ sep:
Select SYSENTER/SYSEXIT instruction set support.
This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
sse:
simd:
Select SIMD instructions support.
Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2/AVX/AVX2/AVX512
could be selected.
Select SSE instruction set support.
Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 could be selected.
This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
The AVX choises exists only if Bochs compiled with --enable-avx option.
sse4a:
@ -295,11 +298,6 @@ xsaveopt:
Select XSAVEOPT instruction support.
This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
avx:
Select AVX/AVX2 instruction set support.
This option exists only if Bochs compiled with --enable-avx option.
avx_f16c:
Select AVX float16 convert instructions support.

9
bochs/gui/siminterface.h
View File

@ -569,7 +569,14 @@ enum {
BX_CPUID_SUPPORT_SSE3,
BX_CPUID_SUPPORT_SSSE3,
BX_CPUID_SUPPORT_SSE4_1,
BX_CPUID_SUPPORT_SSE4_2
BX_CPUID_SUPPORT_SSE4_2,
#if BX_SUPPORT_AVX
BX_CPUID_SUPPORT_AVX,
BX_CPUID_SUPPORT_AVX2,
#if BX_SUPPORT_EVEX
BX_CPUID_SUPPORT_AVX512
#endif
#endif
};
enum {

14
bochs/main.cc
View File

@ -1175,9 +1175,7 @@ void bx_init_hardware()
#if BX_CPU_LEVEL >= 6
bx_bool sep_enabled = SIM->get_param_bool(BXPN_CPUID_SEP)->get();
BX_INFO((" SEP support: %s", sep_enabled?"yes":"no"));
bx_bool sse4a_enabled = SIM->get_param_bool(BXPN_CPUID_SSE4A)->get();
BX_INFO((" SSE support: %s%s", SIM->get_param_enum(BXPN_CPUID_SSE)->get_selected(),
sse4a_enabled ? "+sse4a" : ""));
BX_INFO((" SIMD support: %s", SIM->get_param_enum(BXPN_CPUID_SIMD)->get_selected()));
bx_bool xsave_enabled = SIM->get_param_bool(BXPN_CPUID_XSAVE)->get();
bx_bool xsaveopt_enabled = SIM->get_param_bool(BXPN_CPUID_XSAVEOPT)->get();
BX_INFO((" XSAVE support: %s %s",
@ -1202,16 +1200,6 @@ void bx_init_hardware()
bx_bool mwait_enabled = SIM->get_param_bool(BXPN_CPUID_MWAIT)->get();
BX_INFO((" MWAIT support: %s", mwait_enabled?"yes":"no"));
#endif
#if BX_SUPPORT_AVX
unsigned avx_enabled = SIM->get_param_num(BXPN_CPUID_AVX)->get();
bx_bool avx_fma_enabled = SIM->get_param_bool(BXPN_CPUID_AVX_FMA)->get();
if (avx_enabled) {
BX_INFO((" AVX support: %d%s", avx_enabled, avx_fma_enabled ? " (with FMA)" : ""));
}
else {
BX_INFO((" AVX support: no"));
}
#endif
#if BX_SUPPORT_VMX
unsigned vmx_enabled = SIM->get_param_num(BXPN_CPUID_VMX)->get();
if (vmx_enabled) {

3
bochs/param_names.h
View File

@ -51,7 +51,7 @@
#define BXPN_CPUID_MODEL "cpuid.model"
#define BXPN_CPUID_STEPPING "cpuid.stepping"
#define BXPN_CPUID_MMX "cpuid.mmx"
#define BXPN_CPUID_SSE "cpuid.sse"
#define BXPN_CPUID_SIMD "cpuid.simd"
#define BXPN_CPUID_SSE4A "cpuid.sse4a"
#define BXPN_CPUID_MISALIGNED_SSE "cpuid.misaligned_sse"
#define BXPN_CPUID_AES "cpuid.aes"
@ -63,7 +63,6 @@
#define BXPN_CPUID_XSAVEOPT "cpuid.xsaveopt"
#define BXPN_CPUID_SVM "cpuid.svm"
#define BXPN_CPUID_VMX "cpuid.vmx"
#define BXPN_CPUID_AVX "cpuid.avx"
#define BXPN_CPUID_AVX_F16CVT "cpuid.avx_f16c"
#define BXPN_CPUID_AVX_FMA "cpuid.avx_fma"
#define BXPN_CPUID_BMI "cpuid.bmi"