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Standartization of Bochs instruction handlers.

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Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.

Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code

Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)

Huge patch. Almost all source files wre modified.
This commit is contained in:
Stanislav Shwartsman 2012-08-05 13:52:40 +00:00
parent 0d7a18ed0d
commit cc694377b9
69 changed files with 4822 additions and 6131 deletions
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24
bochs/cpu/3dnow.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-2011 Stanislav Shwartsman
// Copyright (c) 2002-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -53,7 +53,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PI2FW_PqQq(bxInstruction_c *i)
/* op is a register or memory reference */
if (i->modC0()) {
op = BX_READ_MMX_REG(i->rm());
op = BX_READ_MMX_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -72,7 +72,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PI2FW_PqQq(bxInstruction_c *i)
int32_to_float32((Bit32s)(MMXSW2(op)), status_word);
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
BX_WRITE_MMX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
#endif
@ -88,7 +88,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PI2FD_PqQq(bxInstruction_c *i)
/* op is a register or memory reference */
if (i->modC0()) {
op = BX_READ_MMX_REG(i->rm());
op = BX_READ_MMX_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -107,7 +107,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PI2FD_PqQq(bxInstruction_c *i)
int32_to_float32(MMXSD1(op), status_word);
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
BX_WRITE_MMX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
#endif
@ -130,7 +130,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PF2ID_PqQq(bxInstruction_c *i)
/* op is a register or memory reference */
if (i->modC0()) {
op = BX_READ_MMX_REG(i->rm());
op = BX_READ_MMX_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -149,7 +149,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PF2ID_PqQq(bxInstruction_c *i)
float32_to_int32_round_to_zero(MMXUD1(op), status_word);
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
BX_WRITE_MMX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
#endif
@ -273,11 +273,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHRW_PqQq(bxInstruction_c *i)
#if BX_CPU_LEVEL >= 5
BX_CPU_THIS_PTR prepareMMX();
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->dst()), op2, result;
/* op2 is a register or memory reference */
if (i->modC0()) {
op2 = BX_READ_MMX_REG(i->rm());
op2 = BX_READ_MMX_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -298,7 +298,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHRW_PqQq(bxInstruction_c *i)
MMXUW3(result) = Bit16u(product4 >> 16);
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
BX_WRITE_MMX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
#endif
@ -314,7 +314,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PSWAPD_PqQq(bxInstruction_c *i)
/* op is a register or memory reference */
if (i->modC0()) {
op = BX_READ_MMX_REG(i->rm());
op = BX_READ_MMX_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -328,7 +328,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PSWAPD_PqQq(bxInstruction_c *i)
MMXUD1(result) = MMXUD0(op);
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
BX_WRITE_MMX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
#endif

40
bochs/cpu/aes.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2011 Stanislav Shwartsman
// Copyright (c) 2008-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -290,19 +290,19 @@ BX_CPP_INLINE Bit32u AES_RotWord(Bit32u x)
/* 66 0F 38 DB */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESIMC_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
AES_InverseMixColumns(op);
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op, i->getVL());
BX_NEXT_INSTR(i);
}
/* 66 0F 38 DC */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENC_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENC_VdqHdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
AES_ShiftRows(op1);
AES_SubstituteBytes(op1);
@ -311,15 +311,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENC_VdqWdqR(bxInstruction_c *i)
op1.xmm64u(0) ^= op2.xmm64u(0);
op1.xmm64u(1) ^= op2.xmm64u(1);
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op1, i->getVL());
BX_NEXT_INSTR(i);
}
/* 66 0F 38 DD */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENCLAST_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENCLAST_VdqHdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
AES_ShiftRows(op1);
AES_SubstituteBytes(op1);
@ -327,15 +327,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENCLAST_VdqWdqR(bxInstruction_c
op1.xmm64u(0) ^= op2.xmm64u(0);
op1.xmm64u(1) ^= op2.xmm64u(1);
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op1, i->getVL());
BX_NEXT_INSTR(i);
}
/* 66 0F 38 DE */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDEC_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDEC_VdqHdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
AES_InverseShiftRows(op1);
AES_InverseSubstituteBytes(op1);
@ -344,15 +344,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDEC_VdqWdqR(bxInstruction_c *i)
op1.xmm64u(0) ^= op2.xmm64u(0);
op1.xmm64u(1) ^= op2.xmm64u(1);
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op1, i->getVL());
BX_NEXT_INSTR(i);
}
/* 66 0F 38 DF */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDECLAST_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDECLAST_VdqHdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
AES_InverseShiftRows(op1);
AES_InverseSubstituteBytes(op1);
@ -360,7 +360,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDECLAST_VdqWdqR(bxInstruction_c
op1.xmm64u(0) ^= op2.xmm64u(0);
op1.xmm64u(1) ^= op2.xmm64u(1);
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op1, i->getVL());
BX_NEXT_INSTR(i);
}
@ -368,7 +368,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDECLAST_VdqWdqR(bxInstruction_c
/* 66 0F 3A DF */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src()), result;
Bit32u rcon32 = i->Ib();
@ -377,15 +377,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR(bxInstru
result.xmm32u(2) = AES_SubWord(op.xmm32u(3));
result.xmm32u(3) = AES_RotWord(result.xmm32u(2)) ^ rcon32;
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
/* 66 0F 3A 44 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PCLMULQDQ_VdqWdqIbR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PCLMULQDQ_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister r, a;
Bit8u imm8 = i->Ib();
@ -414,7 +414,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PCLMULQDQ_VdqWdqIbR(bxInstruction_
b >>= 1;
}
BX_WRITE_XMM_REGZ(i->nnn(), r, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), r, i->getVL());
BX_NEXT_INSTR(i);
}

163
bochs/cpu/arith16.cc
View File

@ -26,7 +26,7 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_RX(bxInstruction_c *i)
{
Bit32u rx = ++BX_READ_16BIT_REG(i->rm());
Bit32u rx = ++BX_READ_16BIT_REG(i->dst());
SET_FLAGS_OSZAP_ADD_16(rx - 1, 0, rx);
BX_NEXT_INSTR(i);
@ -34,7 +34,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_RX(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_RX(bxInstruction_c *i)
{
Bit32u rx = --BX_READ_16BIT_REG(i->rm());
Bit32u rx = --BX_READ_16BIT_REG(i->dst());
SET_FLAGS_OSZAP_SUB_16(rx + 1, 0, rx);
BX_NEXT_INSTR(i);
@ -45,7 +45,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
Bit32u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u sum_16 = op1_16 + op2_16;
write_RMW_virtual_word(sum_16);
@ -57,11 +57,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EwGwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GwEwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u sum_16 = op1_16 + op2_16;
BX_WRITE_16BIT_REG(i->nnn(), sum_16);
BX_WRITE_16BIT_REG(i->dst(), sum_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
@ -72,24 +72,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GwEwM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = read_virtual_word(i->seg(), eaddr);
Bit32u sum_16 = op1_16 + op2_16;
BX_WRITE_16BIT_REG(i->nnn(), sum_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_AXIw(bxInstruction_c *i)
{
Bit32u op1_16 = AX;
Bit32u op2_16 = i->Iw();
Bit32u sum_16 = op1_16 + op2_16;
AX = sum_16;
BX_WRITE_16BIT_REG(i->dst(), sum_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
@ -101,7 +88,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
Bit32u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u sum_16 = op1_16 + op2_16 + getB_CF();
write_RMW_virtual_word(sum_16);
@ -113,11 +100,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EwGwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GwEwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u sum_16 = op1_16 + op2_16 + getB_CF();
BX_WRITE_16BIT_REG(i->nnn(), sum_16);
BX_WRITE_16BIT_REG(i->dst(), sum_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
@ -128,24 +115,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GwEwM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = read_virtual_word(i->seg(), eaddr);
Bit32u sum_16 = op1_16 + op2_16 + getB_CF();
BX_WRITE_16BIT_REG(i->nnn(), sum_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_AXIw(bxInstruction_c *i)
{
Bit32u op1_16 = AX;
Bit32u op2_16 = i->Iw();
Bit32u sum_16 = op1_16 + op2_16 + getB_CF();
AX = sum_16;
BX_WRITE_16BIT_REG(i->dst(), sum_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
@ -157,7 +131,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
Bit32u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u diff_16 = op1_16 - (op2_16 + getB_CF());
write_RMW_virtual_word(diff_16);
@ -169,11 +143,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EwGwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GwEwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u diff_16 = op1_16 - (op2_16 + getB_CF());
BX_WRITE_16BIT_REG(i->nnn(), diff_16);
BX_WRITE_16BIT_REG(i->dst(), diff_16);
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
@ -184,24 +158,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GwEwM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = read_virtual_word(i->seg(), eaddr);
Bit32u diff_16 = op1_16 - (op2_16 + getB_CF());
BX_WRITE_16BIT_REG(i->nnn(), diff_16);
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_AXIw(bxInstruction_c *i)
{
Bit32u op1_16 = AX;
Bit32u op2_16 = i->Iw();
Bit32u diff_16 = op1_16 - (op2_16 + getB_CF());
AX = diff_16;
BX_WRITE_16BIT_REG(i->dst(), diff_16);
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
@ -225,11 +186,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EwIwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EwIwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = i->Iw();
Bit32u diff_16 = op1_16 - (op2_16 + getB_CF());
BX_WRITE_16BIT_REG(i->rm(), diff_16);
BX_WRITE_16BIT_REG(i->dst(), diff_16);
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
@ -241,7 +202,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
Bit32u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u diff_16 = op1_16 - op2_16;
write_RMW_virtual_word(diff_16);
@ -253,11 +214,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EwGwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GwEwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u diff_16 = op1_16 - op2_16;
BX_WRITE_16BIT_REG(i->nnn(), diff_16);
BX_WRITE_16BIT_REG(i->dst(), diff_16);
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
@ -268,24 +229,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GwEwM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = read_virtual_word(i->seg(), eaddr);
Bit32u diff_16 = op1_16 - op2_16;
BX_WRITE_16BIT_REG(i->nnn(), diff_16);
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_AXIw(bxInstruction_c *i)
{
Bit32u op1_16 = AX;
Bit32u op2_16 = i->Iw();
Bit32u diff_16 = op1_16 - op2_16;
AX = diff_16;
BX_WRITE_16BIT_REG(i->dst(), diff_16);
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
@ -297,7 +245,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = read_virtual_word(i->seg(), eaddr);
Bit32u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
@ -307,8 +255,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EwGwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GwEwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
@ -320,7 +268,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GwEwM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = read_virtual_word(i->seg(), eaddr);
Bit32u diff_16 = op1_16 - op2_16;
@ -329,17 +277,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GwEwM(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_AXIw(bxInstruction_c *i)
{
Bit32u op1_16 = AX;
Bit32u op2_16 = i->Iw();
Bit32u diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CBW(bxInstruction_c *i)
{
/* CBW: no flags are effected */
@ -372,13 +309,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
Bit32u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u sum_16 = op1_16 + op2_16;
write_RMW_virtual_word(sum_16);
/* and write destination into source */
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->src(), op1_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
@ -393,16 +330,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EwGwR(bxInstruction_c *i)
* dst <-- tmp | op1 = sum
*/
Bit32u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u sum_16 = op1_16 + op2_16;
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->rm(), sum_16);
BX_WRITE_16BIT_REG(i->src(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), sum_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
@ -426,10 +363,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EwIwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EwIwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = i->Iw();
Bit32u sum_16 = op1_16 + op2_16;
BX_WRITE_16BIT_REG(i->rm(), sum_16);
BX_WRITE_16BIT_REG(i->dst(), sum_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
@ -453,11 +390,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EwIwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EwIwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = i->Iw();
Bit32u sum_16 = op1_16 + op2_16 + getB_CF();
BX_WRITE_16BIT_REG(i->rm(), sum_16);
BX_WRITE_16BIT_REG(i->dst(), sum_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
@ -481,11 +418,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EwIwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EwIwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = i->Iw();
Bit32u diff_16 = op1_16 - op2_16;
BX_WRITE_16BIT_REG(i->rm(), diff_16);
BX_WRITE_16BIT_REG(i->dst(), diff_16);
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
@ -507,7 +444,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EwIwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EwIwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u op2_16 = i->Iw();
Bit32u diff_16 = op1_16 - op2_16;
@ -531,9 +468,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EwR(bxInstruction_c *i)
{
Bit32u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit32u op1_16 = BX_READ_16BIT_REG(i->dst());
op1_16 = 0 - (Bit32s)(Bit16s)(op1_16);
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
SET_FLAGS_OSZAPC_SUB_16(0, 0 - op1_16, op1_16);
@ -577,7 +514,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EwGwM(bxInstruction_c *i)
if (diff_16 == 0) { // if accumulator == dest
// dest <-- src
write_RMW_virtual_word(BX_READ_16BIT_REG(i->nnn()));
write_RMW_virtual_word(BX_READ_16BIT_REG(i->src()));
}
else {
// accumulator <-- dest
@ -589,14 +526,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EwGwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit16u diff_16 = AX - op1_16;
SET_FLAGS_OSZAPC_SUB_16(AX, op1_16, diff_16);
if (diff_16 == 0) { // if accumulator == dest
// dest <-- src
BX_WRITE_16BIT_REG(i->rm(), BX_READ_16BIT_REG(i->nnn()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
}
else {
// accumulator <-- dest

175
bochs/cpu/arith32.cc
View File

@ -26,18 +26,18 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_ERX(bxInstruction_c *i)
{
Bit32u erx = ++BX_READ_32BIT_REG(i->rm());
Bit32u erx = ++BX_READ_32BIT_REG(i->dst());
SET_FLAGS_OSZAP_ADD_32(erx - 1, 0, erx);
BX_CLEAR_64BIT_HIGH(i->rm());
BX_CLEAR_64BIT_HIGH(i->dst());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_ERX(bxInstruction_c *i)
{
Bit32u erx = --BX_READ_32BIT_REG(i->rm());
Bit32u erx = --BX_READ_32BIT_REG(i->dst());
SET_FLAGS_OSZAP_SUB_32(erx + 1, 0, erx);
BX_CLEAR_64BIT_HIGH(i->rm());
BX_CLEAR_64BIT_HIGH(i->dst());
BX_NEXT_INSTR(i);
}
@ -49,7 +49,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
sum_32 = op1_32 + op2_32;
write_RMW_virtual_dword(sum_32);
@ -62,11 +62,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, sum_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
sum_32 = op1_32 + op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
@ -79,24 +79,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GdEdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = read_virtual_dword(i->seg(), eaddr);
sum_32 = op1_32 + op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EAXId(bxInstruction_c *i)
{
Bit32u op1_32, op2_32 = i->Id(), sum_32;
op1_32 = EAX;
sum_32 = op1_32 + op2_32;
RAX = sum_32;
BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
@ -112,7 +99,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
sum_32 = op1_32 + op2_32 + temp_CF;
write_RMW_virtual_dword(sum_32);
@ -127,10 +114,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GdEdR(bxInstruction_c *i)
Bit32u op1_32, op2_32, sum_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
sum_32 = op1_32 + op2_32 + temp_CF;
BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
@ -145,25 +132,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GdEdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = read_virtual_dword(i->seg(), eaddr);
sum_32 = op1_32 + op2_32 + temp_CF;
BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EAXId(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
Bit32u op1_32, op2_32 = i->Id(), sum_32;
op1_32 = EAX;
sum_32 = op1_32 + op2_32 + temp_CF;
RAX = sum_32;
BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
@ -179,7 +151,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
diff_32 = op1_32 - (op2_32 + temp_CF);
write_RMW_virtual_dword(diff_32);
@ -194,10 +166,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GdEdR(bxInstruction_c *i)
Bit32u op1_32, op2_32, diff_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
diff_32 = op1_32 - (op2_32 + temp_CF);
BX_WRITE_32BIT_REGZ(i->nnn(), diff_32);
BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
@ -212,26 +184,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GdEdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = read_virtual_dword(i->seg(), eaddr);
diff_32 = op1_32 - (op2_32 + temp_CF);
BX_WRITE_32BIT_REGZ(i->nnn(), diff_32);
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EAXId(bxInstruction_c *i)
{
bx_bool temp_CF = getB_CF();
Bit32u op1_32, op2_32, diff_32;
op1_32 = EAX;
op2_32 = i->Id();
diff_32 = op1_32 - (op2_32 + temp_CF);
RAX = diff_32;
BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
@ -261,9 +217,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EdIdR(bxInstruction_c *i)
Bit32u op1_32, op2_32 = i->Id(), diff_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
diff_32 = op1_32 - (op2_32 + temp_CF);
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
@ -277,7 +233,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
diff_32 = op1_32 - op2_32;
write_RMW_virtual_dword(diff_32);
@ -290,10 +246,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
diff_32 = op1_32 - op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), diff_32);
BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
@ -306,24 +262,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GdEdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = read_virtual_dword(i->seg(), eaddr);
diff_32 = op1_32 - op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), diff_32);
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EAXId(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
op1_32 = EAX;
op2_32 = i->Id();
diff_32 = op1_32 - op2_32;
RAX = diff_32;
BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
@ -337,7 +279,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
@ -349,8 +291,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
@ -364,7 +306,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GdEdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = read_virtual_dword(i->seg(), eaddr);
diff_32 = op1_32 - op2_32;
@ -373,19 +315,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GdEdM(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EAXId(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
op1_32 = EAX;
op2_32 = i->Id();
diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CWDE(bxInstruction_c *i)
{
/* CWDE: no flags are effected */
@ -421,12 +350,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
sum_32 = op1_32 + op2_32;
write_RMW_virtual_dword(sum_32);
/* and write destination into source */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->src(), op1_32);
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
@ -443,16 +372,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdR(bxInstruction_c *i)
* dst <-- tmp | op1 = sum
*/
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
sum_32 = op1_32 + op2_32;
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
BX_WRITE_32BIT_REGZ(i->src(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
@ -479,11 +408,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EdIdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, sum_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = i->Id();
sum_32 = op1_32 + op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
@ -513,9 +442,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EdIdR(bxInstruction_c *i)
Bit32u op1_32, op2_32 = i->Id(), sum_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
sum_32 = op1_32 + op2_32 + temp_CF;
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
@ -541,9 +470,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EdIdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32 = i->Id(), diff_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
diff_32 = op1_32 - op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
BX_WRITE_32BIT_REGZ(i->dst(), diff_32);
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
@ -569,7 +498,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EdIdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, diff_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = i->Id();
diff_32 = op1_32 - op2_32;
@ -593,9 +522,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EdM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
op1_32 = - (Bit32s)(op1_32);
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
SET_FLAGS_OSZAPC_SUB_32(0, 0 - op1_32, op1_32);
@ -638,7 +567,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdM(bxInstruction_c *i)
if (diff_32 == 0) { // if accumulator == dest
// dest <-- src
write_RMW_virtual_dword(BX_READ_32BIT_REG(i->nnn()));
write_RMW_virtual_dword(BX_READ_32BIT_REG(i->src()));
}
else {
// accumulator <-- dest
@ -650,13 +579,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
Bit32u diff_32 = EAX - op1_32;
SET_FLAGS_OSZAPC_SUB_32(EAX, op1_32, diff_32);
if (diff_32 == 0) { // if accumulator == dest
// dest <-- src
BX_WRITE_32BIT_REGZ(i->rm(), BX_READ_32BIT_REG(i->nnn()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
}
else {
// accumulator <-- dest

183
bochs/cpu/arith64.cc
View File

@ -34,7 +34,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EqGqM(bxInstruction_c *i)
/* pointer, segment address pair */
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
sum_64 = op1_64 + op2_64;
write_RMW_virtual_qword(sum_64);
@ -47,10 +47,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, sum_64;
op1_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
sum_64 = op1_64 + op2_64;
BX_WRITE_64BIT_REG(i->nnn(), sum_64);
BX_WRITE_64BIT_REG(i->dst(), sum_64);
SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
@ -63,26 +63,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GqEqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
sum_64 = op1_64 + op2_64;
BX_WRITE_64BIT_REG(i->nnn(), sum_64);
SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_RAXId(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, sum_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
sum_64 = op1_64 + op2_64;
/* now write sum back to destination */
RAX = sum_64;
BX_WRITE_64BIT_REG(i->dst(), sum_64);
SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
@ -97,7 +81,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EqGqM(bxInstruction_c *i)
/* pointer, segment address pair */
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
sum_64 = op1_64 + op2_64 + getB_CF();
write_RMW_virtual_qword(sum_64);
@ -110,11 +94,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, sum_64;
op1_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
sum_64 = op1_64 + op2_64 + getB_CF();
BX_WRITE_64BIT_REG(i->nnn(), sum_64);
BX_WRITE_64BIT_REG(i->dst(), sum_64);
SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
@ -127,27 +111,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GqEqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
sum_64 = op1_64 + op2_64 + getB_CF();
BX_WRITE_64BIT_REG(i->nnn(), sum_64);
SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_RAXId(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, sum_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
sum_64 = op1_64 + op2_64 + getB_CF();
/* now write sum back to destination */
RAX = sum_64;
BX_WRITE_64BIT_REG(i->dst(), sum_64);
SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
@ -162,7 +130,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EqGqM(bxInstruction_c *i)
/* pointer, segment address pair */
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
diff_64 = op1_64 - (op2_64 + getB_CF());
write_RMW_virtual_qword(diff_64);
@ -175,11 +143,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
diff_64 = op1_64 - (op2_64 + getB_CF());
BX_WRITE_64BIT_REG(i->nnn(), diff_64);
BX_WRITE_64BIT_REG(i->dst(), diff_64);
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
@ -192,26 +160,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GqEqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
diff_64 = op1_64 - (op2_64 + getB_CF());
BX_WRITE_64BIT_REG(i->nnn(), diff_64);
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_RAXId(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
diff_64 = op1_64 - (op2_64 + getB_CF());
RAX = diff_64;
BX_WRITE_64BIT_REG(i->dst(), diff_64);
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
@ -239,10 +192,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = (Bit32s) i->Id();
diff_64 = op1_64 - (op2_64 + getB_CF());
BX_WRITE_64BIT_REG(i->rm(), diff_64);
BX_WRITE_64BIT_REG(i->dst(), diff_64);
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
@ -257,7 +210,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EqGqM(bxInstruction_c *i)
/* pointer, segment address pair */
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
diff_64 = op1_64 - op2_64;
write_RMW_virtual_qword(diff_64);
@ -270,11 +223,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
diff_64 = op1_64 - op2_64;
BX_WRITE_64BIT_REG(i->nnn(), diff_64);
BX_WRITE_64BIT_REG(i->dst(), diff_64);
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
@ -287,26 +240,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GqEqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
diff_64 = op1_64 - op2_64;
BX_WRITE_64BIT_REG(i->nnn(), diff_64);
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_RAXId(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
diff_64 = op1_64 - op2_64;
RAX = diff_64;
BX_WRITE_64BIT_REG(i->dst(), diff_64);
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
@ -320,7 +258,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EqGqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
@ -332,8 +270,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
@ -347,7 +285,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GqEqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
diff_64 = op1_64 - op2_64;
@ -356,19 +294,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GqEqM(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_RAXId(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CDQE(bxInstruction_c *i)
{
/* CWDE: no flags are affected */
@ -403,12 +328,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EqGqM(bxInstruction_c *i)
/* pointer, segment address pair */
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
sum_64 = op1_64 + op2_64;
write_RMW_virtual_qword(sum_64);
/* and write destination into source */
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->src(), op1_64);
SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
@ -425,16 +350,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EqGqR(bxInstruction_c *i)
* dst <-- tmp | op1 = sum
*/
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
sum_64 = op1_64 + op2_64;
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->rm(), sum_64);
BX_WRITE_64BIT_REG(i->src(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), sum_64);
SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
@ -462,10 +387,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, sum_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = (Bit32s) i->Id();
sum_64 = op1_64 + op2_64;
BX_WRITE_64BIT_REG(i->rm(), sum_64);
BX_WRITE_64BIT_REG(i->dst(), sum_64);
SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
@ -493,10 +418,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, sum_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = (Bit32s) i->Id();
sum_64 = op1_64 + op2_64 + getB_CF();
BX_WRITE_64BIT_REG(i->rm(), sum_64);
BX_WRITE_64BIT_REG(i->dst(), sum_64);
SET_FLAGS_OSZAPC_ADD_64(op1_64, op2_64, sum_64);
@ -524,10 +449,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = (Bit32s) i->Id();
diff_64 = op1_64 - op2_64;
BX_WRITE_64BIT_REG(i->rm(), diff_64);
BX_WRITE_64BIT_REG(i->dst(), diff_64);
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
@ -553,7 +478,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64, diff_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = (Bit32s) i->Id();
diff_64 = op1_64 - op2_64;
@ -577,9 +502,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EqM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
op1_64 = - (Bit64s)(op1_64);
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_SUB_64(0, -op1_64, op1_64);
@ -601,7 +526,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_EqM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_EqR(bxInstruction_c *i)
{
Bit64u rrx = ++BX_READ_64BIT_REG(i->rm());
Bit64u rrx = ++BX_READ_64BIT_REG(i->dst());
SET_FLAGS_OSZAP_ADD_64(rrx - 1, 0, rrx);
BX_NEXT_INSTR(i);
@ -622,7 +547,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_EqM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_EqR(bxInstruction_c *i)
{
Bit64u rrx = --BX_READ_64BIT_REG(i->rm());
Bit64u rrx = --BX_READ_64BIT_REG(i->dst());
SET_FLAGS_OSZAP_SUB_64(rrx + 1, 0, rrx);
BX_NEXT_INSTR(i);
@ -638,7 +563,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EqGqM(bxInstruction_c *i)
if (diff_64 == 0) { // if accumulator == dest
// dest <-- src
write_RMW_virtual_qword(BX_READ_64BIT_REG(i->nnn()));
write_RMW_virtual_qword(BX_READ_64BIT_REG(i->src()));
}
else {
// accumulator <-- dest
@ -650,13 +575,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EqGqM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
Bit64u diff_64 = RAX - op1_64;
SET_FLAGS_OSZAPC_SUB_64(RAX, op1_64, diff_64);
if (diff_64 == 0) { // if accumulator == dest
// dest <-- src
BX_WRITE_64BIT_REG(i->rm(), BX_READ_64BIT_REG(i->nnn()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
}
else {
// accumulator <-- dest
@ -668,20 +593,18 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EqGqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG16B(bxInstruction_c *i)
{
Bit64u op1_64_lo, op1_64_hi, diff;
Bit64u diff;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
bx_address laddr = get_laddr64(i->seg(), eaddr);
if (laddr & 0xf) {
BX_ERROR(("CMPXCHG16B: not aligned memory location (#GP)"));
exception(BX_GP_EXCEPTION, 0);
}
// check write permission for following write
op1_64_lo = read_RMW_virtual_qword_64(i->seg(), eaddr);
op1_64_hi = read_RMW_virtual_qword_64(i->seg(), (eaddr + 8) & i->asize_mask());
Bit64u op1_64_lo = read_RMW_virtual_qword_64(i->seg(), eaddr);
Bit64u op1_64_hi = read_RMW_virtual_qword_64(i->seg(), (eaddr + 8) & i->asize_mask());
diff = RAX - op1_64_lo;
diff |= RDX - op1_64_hi;

167
bochs/cpu/arith8.cc
View File

@ -29,7 +29,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1 = read_RMW_virtual_byte(i->seg(), eaddr);
Bit32u op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u sum = op1 + op2;
write_RMW_virtual_byte(sum);
@ -41,11 +41,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EbGbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GbEbR(bxInstruction_c *i)
{
Bit32u op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u sum = op1 + op2;
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), sum);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), sum);
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
@ -56,23 +56,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GbEbM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2 = read_virtual_byte(i->seg(), eaddr);
Bit32u sum = op1 + op2;
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), sum);
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_ALIb(bxInstruction_c *i)
{
Bit32u op1 = AL;
Bit32u op2 = i->Ib();
Bit32u sum = op1 + op2;
AL = sum;
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), sum);
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
@ -84,7 +72,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1 = read_RMW_virtual_byte(i->seg(), eaddr);
Bit32u op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u sum = op1 + op2 + getB_CF();
write_RMW_virtual_byte(sum);
@ -96,11 +84,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EbGbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GbEbR(bxInstruction_c *i)
{
Bit32u op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u sum = op1 + op2 + getB_CF();
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), sum);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), sum);
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
@ -111,23 +99,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GbEbM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2 = read_virtual_byte(i->seg(), eaddr);
Bit32u sum = op1 + op2 + getB_CF();
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), sum);
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_ALIb(bxInstruction_c *i)
{
Bit32u op1 = AL;
Bit32u op2 = i->Ib();
Bit32u sum = op1 + op2 + getB_CF();
AL = sum;
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), sum);
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
@ -139,7 +115,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_8 = read_RMW_virtual_byte(i->seg(), eaddr);
Bit32u op2_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u diff_8 = op1_8 - (op2_8 + getB_CF());
write_RMW_virtual_byte(diff_8);
@ -151,11 +127,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EbGbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GbEbR(bxInstruction_c *i)
{
Bit32u op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u diff_8 = op1_8 - (op2_8 + getB_CF());
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), diff_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), diff_8);
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
@ -166,24 +142,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GbEbM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2_8 = read_virtual_byte(i->seg(), eaddr);
Bit32u diff_8 = op1_8 - (op2_8 + getB_CF());
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), diff_8);
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_ALIb(bxInstruction_c *i)
{
Bit32u op1_8 = AL;
Bit32u op2_8 = i->Ib();
Bit32u diff_8 = op1_8 - (op2_8 + getB_CF());
AL = diff_8;
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), diff_8);
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
@ -206,10 +169,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EbIbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EbIbR(bxInstruction_c *i)
{
Bit32u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2_8 = i->Ib();
Bit32u diff_8 = op1_8 - (op2_8 + getB_CF());
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), diff_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), diff_8);
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
@ -221,7 +184,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_8 = read_RMW_virtual_byte(i->seg(), eaddr);
Bit32u op2_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u diff_8 = op1_8 - op2_8;
write_RMW_virtual_byte(diff_8);
@ -233,11 +196,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EbGbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GbEbR(bxInstruction_c *i)
{
Bit32u op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u diff_8 = op1_8 - op2_8;
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), diff_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), diff_8);
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
@ -248,24 +211,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GbEbM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2_8 = read_virtual_byte(i->seg(), eaddr);
Bit32u diff_8 = op1_8 - op2_8;
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), diff_8);
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_ALIb(bxInstruction_c *i)
{
Bit32u op1_8 = AL;
Bit32u op2_8 = i->Ib();
Bit32u diff_8 = op1_8 - op2_8;
AL = diff_8;
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), diff_8);
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
@ -277,7 +227,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_8 = read_virtual_byte(i->seg(), eaddr);
Bit32u op2_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
@ -287,8 +237,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EbGbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GbEbR(bxInstruction_c *i)
{
Bit32u op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
@ -300,7 +250,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GbEbM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2_8 = read_virtual_byte(i->seg(), eaddr);
Bit32u diff_8 = op1_8 - op2_8;
@ -309,17 +259,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GbEbM(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_ALIb(bxInstruction_c *i)
{
Bit32u op1_8 = AL;
Bit32u op2_8 = i->Ib();
Bit32u diff_8 = op1_8 - op2_8;
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EbGbM(bxInstruction_c *i)
{
/* XADD dst(r/m8), src(r8)
@ -331,13 +270,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1 = read_RMW_virtual_byte(i->seg(), eaddr);
Bit32u op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u sum = op1 + op2;
write_RMW_virtual_byte(sum);
/* and write destination into source */
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->src(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
@ -352,16 +291,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EbGbR(bxInstruction_c *i)
* dst <-- tmp | op1 = sum
*/
Bit32u op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u sum = op1 + op2;
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), sum);
BX_WRITE_8BIT_REGx(i->src(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), sum);
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
@ -385,11 +324,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EbIbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EbIbR(bxInstruction_c *i)
{
Bit32u op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2 = i->Ib();
Bit32u sum = op1 + op2;
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), sum);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), sum);
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
@ -413,11 +352,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EbIbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EbIbR(bxInstruction_c *i)
{
Bit32u op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2 = i->Ib();
Bit32u sum = op1 + op2 + getB_CF();
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), sum);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), sum);
SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
@ -441,11 +380,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EbIbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EbIbR(bxInstruction_c *i)
{
Bit32u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2_8 = i->Ib();
Bit32u diff_8 = op1_8 - op2_8;
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), diff_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), diff_8);
SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8);
@ -467,7 +406,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EbIbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EbIbR(bxInstruction_c *i)
{
Bit32u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u op2_8 = i->Ib();
Bit32u diff_8 = op1_8 - op2_8;
@ -491,9 +430,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EbR(bxInstruction_c *i)
{
Bit32u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op1_8 = - (Bit8s)(op1_8);
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op1_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1_8);
SET_FLAGS_OSZAPC_SUB_8(0, 0 - op1_8, op1_8);
@ -515,9 +454,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_EbR(bxInstruction_c *i)
{
Bit32u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op1_8++;
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op1_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1_8);
SET_FLAGS_OSZAP_ADD_8(op1_8 - 1, 0, op1_8);
@ -539,9 +478,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_EbR(bxInstruction_c *i)
{
Bit32u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op1_8--;
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op1_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1_8);
SET_FLAGS_OSZAP_SUB_8(op1_8 + 1, 0, op1_8);
@ -559,7 +498,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EbGbM(bxInstruction_c *i)
if (diff_8 == 0) { // if accumulator == dest
// dest <-- src
Bit32u op2_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit32u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
write_RMW_virtual_byte(op2_8);
}
else {
@ -572,15 +511,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EbGbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EbGbR(bxInstruction_c *i)
{
Bit32u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit32u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit32u diff_8 = AL - op1_8;
SET_FLAGS_OSZAPC_SUB_8(AL, op1_8, diff_8);
if (diff_8 == 0) { // if accumulator == dest
// dest <-- src
Bit32u op2_8 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2_8);
Bit32u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op2_8);
}
else {
// accumulator <-- dest

162
bochs/cpu/avx.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011 Stanislav Shwartsman
// Copyright (c) 2011-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -60,11 +60,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VZEROALL(bxInstruction_c *i)
/* VMOVSS: VEX.F3.0F 10 (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSS_VssHpsWssR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src2());
op.xmm32u(0) = BX_READ_XMM_REG_LO_DWORD(i->rm());
op.xmm32u(0) = BX_READ_XMM_REG_LO_DWORD(i->src1());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
@ -74,10 +74,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSD_VsdHpdWsdR(bxInstruction_c
{
BxPackedXmmRegister op;
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->rm());
op.xmm64u(1) = BX_READ_XMM_REG_HI_QWORD(i->vvv());
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->src1());
op.xmm64u(1) = BX_READ_XMM_REG_HI_QWORD(i->src2());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
@ -87,7 +87,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSD_VsdHpdWsdR(bxInstruction_c
/* VMOVDQA: VEX.66.0F 6F (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_VpsWpsR(bxInstruction_c *i)
{
BX_WRITE_AVX_REGZ(i->nnn(), BX_READ_AVX_REG(i->rm()), i->getVL());
BX_WRITE_AVX_REGZ(i->dst(), BX_READ_AVX_REG(i->src()), i->getVL());
BX_NEXT_INSTR(i);
}
@ -100,7 +100,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_VpsWpsM(bxInstruction_c *i
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
read_virtual_dword_vector_aligned(i->seg(), eaddr, len << 2, &op);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
@ -116,7 +116,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPS_VpsWpsM(bxInstruction_c *i
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
read_virtual_dword_vector(i->seg(), eaddr, len << 2, &op);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
@ -126,7 +126,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPS_VpsWpsM(bxInstruction_c *i
/* VMOVUQA: VEX.66.0F 7F (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPS_WpsVpsM(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->nnn());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dword_vector(i->seg(), eaddr, i->getVL() << 2, &op);
@ -139,7 +139,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPS_WpsVpsM(bxInstruction_c *i
/* VMOVDQA: VEX.66.0F 7F (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_WpsVpsM(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->nnn());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dword_vector_aligned(i->seg(), eaddr, i->getVL() << 2, &op);
@ -150,14 +150,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_WpsVpsM(bxInstruction_c *i
/* VEX.F2.0F 12 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVDDUP_VpdWpdR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n+=2) {
op.avx64u(n+1) = op.avx64u(n);
}
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
@ -165,14 +165,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVDDUP_VpdWpdR(bxInstruction_c *
/* VEX.F3.0F 12 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSLDUP_VpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
for (unsigned n=0; n < (4*len); n+=2) {
op.avx32u(n+1) = op.avx32u(n);
}
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
@ -180,14 +180,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSLDUP_VpsWpsR(bxInstruction_c
/* VEX.F3.0F 12 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSHDUP_VpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
for (unsigned n=0; n < (4*len); n+=2) {
op.avx32u(n) = op.avx32u(n+1);
}
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
@ -197,10 +197,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHLPS_VpsHpsWps(bxInstruction_c
{
BxPackedXmmRegister op;
op.xmm64u(0) = BX_READ_XMM_REG_HI_QWORD(i->rm());
op.xmm64u(1) = BX_READ_XMM_REG_HI_QWORD(i->vvv());
op.xmm64u(0) = BX_READ_XMM_REG_HI_QWORD(i->src2());
op.xmm64u(1) = BX_READ_XMM_REG_HI_QWORD(i->src1());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
@ -213,9 +213,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLPD_VpdHpdMq(bxInstruction_c *
BxPackedXmmRegister op;
op.xmm64u(0) = read_virtual_qword(i->seg(), eaddr);
op.xmm64u(1) = BX_READ_XMM_REG_HI_QWORD(i->vvv());
op.xmm64u(1) = BX_READ_XMM_REG_HI_QWORD(i->src1());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
@ -225,10 +225,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLHPS_VpsHpsWps(bxInstruction_c
{
BxPackedXmmRegister op;
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->vvv());
op.xmm64u(1) = BX_READ_XMM_REG_LO_QWORD(i->rm());
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->src1());
op.xmm64u(1) = BX_READ_XMM_REG_LO_QWORD(i->src2());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
@ -240,10 +240,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHPD_VpdHpdMq(bxInstruction_c *
BxPackedXmmRegister op;
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->vvv());
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->src1());
op.xmm64u(1) = read_virtual_qword(i->seg(), eaddr);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
@ -251,14 +251,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHPD_VpdHpdMq(bxInstruction_c *
/* VEX.0F 50 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVMSKPS_GdVRps(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
Bit32u mask = 0;
for (unsigned n=0; n < len; n++)
mask |= sse_pmovmskd(&op.avx128(n)) << (4*n);
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
BX_WRITE_32BIT_REGZ(i->dst(), mask);
BX_NEXT_INSTR(i);
}
@ -266,14 +266,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVMSKPS_GdVRps(bxInstruction_c *
/* VEX.66.0F 50 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVMSKPD_GdVRpd(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
Bit32u mask = 0;
for (unsigned n=0; n < len; n++)
mask |= sse_pmovmskq(&op.avx128(n)) << (2*n);
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
BX_WRITE_32BIT_REGZ(i->dst(), mask);
BX_NEXT_INSTR(i);
}
@ -281,14 +281,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVMSKPD_GdVRpd(bxInstruction_c *
/* VEX.66.0F 50 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVMSKB_GdUdq(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
Bit32u mask = 0;
for (unsigned n=0; n < len; n++)
mask |= sse_pmovmskb(&op.avx128(n)) << (16*n);
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
BX_WRITE_32BIT_REGZ(i->dst(), mask);
BX_NEXT_INSTR(i);
}
@ -296,14 +296,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVMSKB_GdUdq(bxInstruction_c *i
/* Opcode: VEX.0F.C6 (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPS_VpsHpsWpsIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_shufps(&result.avx128(n), &op1.avx128(n), &op2.avx128(n), i->Ib());
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
@ -311,8 +311,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPS_VpsHpsWpsIbR(bxInstruction
/* Opcode: VEX.66.0F.C6 (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPD_VpdHpdWpdIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()), result;
unsigned len = i->getVL();
Bit8u order = i->Ib();
@ -322,7 +322,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPD_VpdHpdWpdIbR(bxInstruction
order >>= 2;
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
@ -330,7 +330,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPD_VpdHpdWpdIbR(bxInstruction
/* Opcode: VEX.66.0F.38.17 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPTEST_VdqWdqR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->nnn()), op2 = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->dst()), op2 = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
unsigned result = EFlagsZFMask | EFlagsCFMask;
@ -360,7 +360,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBROADCASTF128_VdqMdq(bxInstructio
op.avx64u(n*2+1) = src.xmm64u(1);
}
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
@ -368,7 +368,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBROADCASTF128_VdqMdq(bxInstructio
/* Opcode: VEX.66.0F.3A 0C (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPS_VpsHpsWpsIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2());
unsigned len = i->getVL();
Bit8u mask = i->Ib();
@ -377,7 +377,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPS_VpsHpsWpsIbR(bxInstructio
mask >>= 4;
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
BX_NEXT_INSTR(i);
}
@ -385,7 +385,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPS_VpsHpsWpsIbR(bxInstructio
/* Opcode: VEX.66.0F.3A 0D (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPD_VpdHpdWpdIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2());
unsigned len = i->getVL();
Bit8u mask = i->Ib();
@ -394,7 +394,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPD_VpdHpdWpdIbR(bxInstructio
mask >>= 2;
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
BX_NEXT_INSTR(i);
}
@ -402,15 +402,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPD_VpdHpdWpdIbR(bxInstructio
/* Opcode: VEX.66.0F.3A 4A (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPS_VpsHpsWpsIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()),
mask = BX_READ_AVX_REG(i->Ib());
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2()),
mask = BX_READ_AVX_REG(i->src3());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_blendvps(&op1.avx128(n), &op2.avx128(n), &mask.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
BX_NEXT_INSTR(i);
}
@ -418,15 +418,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPS_VpsHpsWpsIbR(bxInstructi
/* Opcode: VEX.66.0F.3A 4B (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPD_VpdHpdWpdIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()),
mask = BX_READ_AVX_REG(i->Ib());
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2()),
mask = BX_READ_AVX_REG(i->src3());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_blendvpd(&op1.avx128(n), &op2.avx128(n), &mask.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
BX_NEXT_INSTR(i);
}
@ -434,15 +434,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPD_VpdHpdWpdIbR(bxInstructi
/* Opcode: VEX.66.0F.3A 4C (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()),
mask = BX_READ_AVX_REG(i->Ib());
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2()),
mask = BX_READ_AVX_REG(i->src3());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_pblendvb(&op1.avx128(n), &op2.avx128(n), &mask.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
BX_NEXT_INSTR(i);
}
@ -450,11 +450,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR(bxInstructi
/* Opcode: VEX.66.0F.3A 18 (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF128_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
op1.avx128(i->Ib() & 1) = BX_READ_XMM_REG(i->rm());
op1.avx128(i->Ib() & 1) = BX_READ_XMM_REG(i->src2());
BX_WRITE_AVX_REG(i->nnn(), op1);
BX_WRITE_AVX_REG(i->dst(), op1);
BX_NEXT_INSTR(i);
}
@ -462,7 +462,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF128_VdqHdqWdqIbR(bxInstruc
/* Opcode: VEX.66.0F.3A 19 (VEX.W=0, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF128_WdqVdqIbM(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->nnn());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dqword(i->seg(), eaddr, &(op.avx128(i->Ib() & 1)));
@ -472,9 +472,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF128_WdqVdqIbM(bxInstructi
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF128_WdqVdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->nnn());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->rm(), op.avx128(i->Ib() & 1));
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op.avx128(i->Ib() & 1));
BX_NEXT_INSTR(i);
}
@ -482,14 +482,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF128_WdqVdqIbR(bxInstructi
/* Opcode: VEX.66.0F.38 0C (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsHpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_permilps(&result.avx128(n), &op1.avx128(n), &op2.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
@ -497,14 +497,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsHpsWpsR(bxInstruction
/* Opcode: VEX.66.0F.3A 05 (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdHpdWpdR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_permilpd(&result.avx128(n), &op1.avx128(n), &op2.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
@ -512,13 +512,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdHpdWpdR(bxInstruction
/* Opcode: VEX.66.0F.3A 04 (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsWpsIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_shufps(&result.avx128(n), &op1.avx128(n), &op1.avx128(n), i->Ib());
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
@ -526,7 +526,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsWpsIbR(bxInstruction_
/* Opcode: VEX.66.0F.3A 05 (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdWpdIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src()), result;
unsigned len = i->getVL();
Bit8u order = i->Ib();
@ -536,7 +536,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdWpdIbR(bxInstruction_
order >>= 2;
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
@ -544,8 +544,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdWpdIbR(bxInstruction_
/* Opcode: VEX.66.0F.3A 06 (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERM2F128_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()), result;
Bit8u order = i->Ib();
for (unsigned n=0;n<2;n++) {
@ -563,7 +563,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERM2F128_VdqHdqWdqIbR(bxInstruct
order >>= 4;
}
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
@ -571,7 +571,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERM2F128_VdqHdqWdqIbR(bxInstruct
/* Opcode: VEX.66.0F.38 2C (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsHpsMps(bxInstruction_c *i)
{
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), result;
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->src1()), result;
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -594,7 +594,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsHpsMps(bxInstruction
result.avx32u(n) = 0;
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
@ -602,7 +602,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsHpsMps(bxInstruction
/* Opcode: VEX.66.0F.38 2D (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdHpdMpd(bxInstruction_c *i)
{
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), result;
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->src1()), result;
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -625,7 +625,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdHpdMpd(bxInstruction
result.avx64u(n) = 0;
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
@ -633,7 +633,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdHpdMpd(bxInstruction
/* Opcode: VEX.66.0F.38 2C (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsHpsVps(bxInstruction_c *i)
{
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), op = BX_READ_AVX_REG(i->nnn());
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->src1()), op = BX_READ_AVX_REG(i->src2());
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -666,7 +666,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsHpsVps(bxInstruction
/* Opcode: VEX.66.0F.38 2D (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_MpdHpdVpd(bxInstruction_c *i)
{
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), op = BX_READ_AVX_REG(i->nnn());
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->src1()), op = BX_READ_AVX_REG(i->src2());
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));

144
bochs/cpu/avx2.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011 Stanislav Shwartsman
// Copyright (c) 2011-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -31,19 +31,19 @@
#include "simd_int.h"
#include "simd_compare.h"
#define AVX_2OP(HANDLER, func) \
/* AVX instruction with two src operands */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C :: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()); \
unsigned len = i->getVL(); \
\
for (unsigned n=0; n < len; n++) \
(func)(&op1.avx128(n), &op2.avx128(n)); \
\
BX_WRITE_AVX_REGZ(i->nnn(), op1, len); \
\
BX_NEXT_INSTR(i); \
#define AVX_2OP(HANDLER, func) \
/* AVX instruction with two src operands */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C :: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2()); \
unsigned len = i->getVL(); \
\
for (unsigned n=0; n < len; n++) \
(func)(&op1.avx128(n), &op2.avx128(n)); \
\
BX_WRITE_AVX_REGZ(i->dst(), op1, len); \
\
BX_NEXT_INSTR(i); \
}
AVX_2OP(VANDPS_VpsHpsWpsR, sse_andps)
@ -143,13 +143,13 @@ AVX_2OP(VPSRLVQ_VdqHdqWdqR, sse_psrlvq)
/* AVX instruction with single src operand */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C :: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm()); \
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src()); \
unsigned len = i->getVL(); \
\
for (unsigned n=0; n < len; n++) \
(func)(&op.avx128(n)); \
\
BX_WRITE_AVX_REGZ(i->nnn(), op, len); \
BX_WRITE_AVX_REGZ(i->dst(), op, len); \
\
BX_NEXT_INSTR(i); \
}
@ -162,13 +162,13 @@ AVX_1OP(VPABSD_VdqWdqR, sse_pabsd)
/* AVX packed shift instruction */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op = BX_READ_AVX_REG(i->vvv()); \
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src1()); \
unsigned len = i->getVL(); \
\
for (unsigned n=0; n < len; n++) \
(func)(&op.avx128(n), BX_READ_XMM_REG_LO_QWORD(i->rm())); \
(func)(&op.avx128(n), BX_READ_XMM_REG_LO_QWORD(i->src2())); \
\
BX_WRITE_AVX_REGZ(i->nnn(), op, len); \
BX_WRITE_AVX_REGZ(i->dst(), op, len); \
\
BX_NEXT_INSTR(i); \
}
@ -186,13 +186,13 @@ AVX_PSHIFT(VPSLLQ_VdqHdqWdqR, sse_psllq);
/* AVX packed shift with imm8 instruction */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm()); \
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src()); \
unsigned len = i->getVL(); \
\
for (unsigned n=0; n < len; n++) \
(func)(&op.avx128(n), i->Ib()); \
\
BX_WRITE_AVX_REGZ(i->vvv(), op, len); \
BX_WRITE_AVX_REGZ(i->dst(), op, len); \
\
BX_NEXT_INSTR(i); \
}
@ -211,50 +211,50 @@ AVX_PSHIFT_IMM(VPSLLDQ_UdqIb, sse_pslldq);
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPSHUFHW_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src()), result;
Bit8u order = i->Ib();
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_pshufhw(&result.avx128(n), &op.avx128(n), order);
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPSHUFLW_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src()), result;
Bit8u order = i->Ib();
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_pshuflw(&result.avx128(n), &op.avx128(n), order);
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPSHUFB_VdqHdqWdqR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_pshufb(&result.avx128(n), &op1.avx128(n), &op2.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMPSADBW_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()), result;
Bit8u control = i->Ib();
unsigned len = i->getVL();
@ -264,14 +264,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMPSADBW_VdqHdqWdqIbR(bxInstructio
control >>= 3;
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDW_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2());
unsigned len = i->getVL();
Bit8u mask = i->Ib();
@ -279,7 +279,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDW_VdqHdqWdqIbR(bxInstructio
for (unsigned n=0; n < len; n++)
sse_pblendw(&op1.avx128(n), &op2.avx128(n), mask);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
BX_NEXT_INSTR(i);
}
@ -289,12 +289,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTB_VdqWb(bxInstruction_c
unsigned len = i->getVL();
BxPackedAvxRegister op;
Bit8u val_8 = BX_READ_XMM_REG_LO_BYTE(i->rm());
Bit8u val_8 = BX_READ_XMM_REG_LO_BYTE(i->src());
for (unsigned n=0; n < len; n++)
sse_pbroadcastb(&op.avx128(n), val_8);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
@ -304,12 +304,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTW_VdqWw(bxInstruction_c
unsigned len = i->getVL();
BxPackedAvxRegister op;
Bit16u val_16 = BX_READ_XMM_REG_LO_WORD(i->rm());
Bit16u val_16 = BX_READ_XMM_REG_LO_WORD(i->src());
for (unsigned n=0; n < len; n++)
sse_pbroadcastw(&op.avx128(n), val_16);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
@ -319,12 +319,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTD_VdqWd(bxInstruction_c
unsigned len = i->getVL();
BxPackedAvxRegister op;
Bit32u val_32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
Bit32u val_32 = BX_READ_XMM_REG_LO_DWORD(i->src());
for (unsigned n=0; n < len; n++)
sse_pbroadcastd(&op.avx128(n), val_32);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
@ -334,25 +334,25 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTQ_VdqWq(bxInstruction_c
unsigned len = i->getVL();
BxPackedAvxRegister op;
Bit64u val_64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
Bit64u val_64 = BX_READ_XMM_REG_LO_QWORD(i->src());
for (unsigned n=0; n < len; n++)
sse_pbroadcastq(&op.avx128(n), val_64);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBW256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedAvxRegister result;
for (int n=0; n<16; n++)
result.avx16u(n) = (Bit8s) op.xmmsbyte(n);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
@ -363,7 +363,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBD256_VdqWqR(bxInstruction_
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.avx32u(0) = (Bit8s) MMXSB0(op);
result.avx32u(1) = (Bit8s) MMXSB1(op);
@ -374,7 +374,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBD256_VdqWqR(bxInstruction_
result.avx32u(6) = (Bit8s) MMXSB6(op);
result.avx32u(7) = (Bit8s) MMXSB7(op);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
@ -382,21 +382,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBD256_VdqWqR(bxInstruction_
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBQ256_VdqWdR(bxInstruction_c *i)
{
BxPackedAvxRegister result;
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->src());
result.avx64u(0) = (Bit8s) (val32 & 0xFF);
result.avx64u(1) = (Bit8s) ((val32 >> 8) & 0xFF);
result.avx64u(2) = (Bit8s) ((val32 >> 16) & 0xFF);
result.avx64u(3) = (Bit8s) (val32 >> 24);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXWD256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedAvxRegister result;
result.avx32u(0) = op.xmm16s(0);
@ -408,7 +408,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXWD256_VdqWdqR(bxInstruction
result.avx32u(6) = op.xmm16s(6);
result.avx32u(7) = op.xmm16s(7);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
@ -419,21 +419,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXWQ256_VdqWqR(bxInstruction_
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.avx64u(0) = MMXSW0(op);
result.avx64u(1) = MMXSW1(op);
result.avx64u(2) = MMXSW2(op);
result.avx64u(3) = MMXSW3(op);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXDQ256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedAvxRegister result;
result.avx64u(0) = op.xmm32s(0);
@ -441,20 +441,20 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXDQ256_VdqWdqR(bxInstruction
result.avx64u(2) = op.xmm32s(2);
result.avx64u(3) = op.xmm32s(3);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBW256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedAvxRegister result;
for (int n=0; n<16; n++)
result.avx16u(n) = op.xmmubyte(n);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
@ -465,7 +465,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBD256_VdqWqR(bxInstruction_
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.avx32u(0) = MMXUB0(op);
result.avx32u(1) = MMXUB1(op);
@ -476,7 +476,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBD256_VdqWqR(bxInstruction_
result.avx32u(6) = MMXUB6(op);
result.avx32u(7) = MMXUB7(op);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
@ -484,21 +484,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBD256_VdqWqR(bxInstruction_
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBQ256_VdqWdR(bxInstruction_c *i)
{
BxPackedAvxRegister result;
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->src());
result.avx64u(0) = (Bit8u) (val32 & 0xFF);
result.avx64u(1) = (Bit8u) ((val32 >> 8) & 0xFF);
result.avx64u(2) = (Bit8u) ((val32 >> 16) & 0xFF);
result.avx64u(3) = (Bit8u) (val32 >> 24);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXWD256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedAvxRegister result;
result.avx32u(0) = op.xmm16u(0);
@ -510,7 +510,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXWD256_VdqWdqR(bxInstruction
result.avx32u(6) = op.xmm16u(6);
result.avx32u(7) = op.xmm16u(7);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
@ -521,21 +521,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXWQ256_VdqWqR(bxInstruction_
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.avx64u(0) = MMXUW0(op);
result.avx64u(1) = MMXUW1(op);
result.avx64u(2) = MMXUW2(op);
result.avx64u(3) = MMXUW3(op);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXDQ256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedAvxRegister result;
result.avx64u(0) = op.xmm32u(0);
@ -543,28 +543,28 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXDQ256_VdqWdqR(bxInstruction
result.avx64u(2) = op.xmm32u(2);
result.avx64u(3) = op.xmm32u(3);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPALIGNR_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2());
unsigned len = i->getVL();
for (unsigned n=0; n<len; n++)
sse_palignr(&op2.avx128(n), &op1.avx128(n), i->Ib());
BX_WRITE_AVX_REGZ(i->nnn(), op2, i->getVL());
BX_WRITE_AVX_REGZ(i->dst(), op2, i->getVL());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMD_VdqHdqWdqR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()), result;
result.avx32u(0) = op2.avx32u(op1.avx32u(0) & 0x7);
result.avx32u(1) = op2.avx32u(op1.avx32u(1) & 0x7);
@ -575,14 +575,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMD_VdqHdqWdqR(bxInstruction_c
result.avx32u(6) = op2.avx32u(op1.avx32u(6) & 0x7);
result.avx32u(7) = op2.avx32u(op1.avx32u(7) & 0x7);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMQ_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src()), result;
Bit8u control = i->Ib();
result.avx64u(0) = op2.avx64u((control) & 0x3);
@ -590,7 +590,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMQ_VdqWdqIbR(bxInstruction_c *
result.avx64u(2) = op2.avx64u((control >> 4) & 0x3);
result.avx64u(3) = op2.avx64u((control >> 6) & 0x3);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_WRITE_AVX_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}

1090
bochs/cpu/avx_fma.cc
View File

File diff suppressed because it is too large Load Diff

310
bochs/cpu/avx_pfp.cc
View File

File diff suppressed because it is too large Load Diff

56
bochs/cpu/bit.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -38,7 +38,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETO_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETO_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), getB_OF());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), getB_OF());
BX_NEXT_INSTR(i);
}
@ -55,7 +55,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNO_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNO_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), !getB_OF());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), !getB_OF());
BX_NEXT_INSTR(i);
}
@ -72,7 +72,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETB_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETB_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), getB_CF());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), getB_CF());
BX_NEXT_INSTR(i);
}
@ -89,7 +89,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNB_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNB_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), !getB_CF());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), !getB_CF());
BX_NEXT_INSTR(i);
}
@ -106,7 +106,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETZ_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETZ_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), getB_ZF());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), getB_ZF());
BX_NEXT_INSTR(i);
}
@ -123,7 +123,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNZ_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNZ_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), !getB_ZF());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), !getB_ZF());
BX_NEXT_INSTR(i);
}
@ -140,7 +140,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETBE_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETBE_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), (getB_CF() | getB_ZF()));
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), (getB_CF() | getB_ZF()));
BX_NEXT_INSTR(i);
}
@ -157,7 +157,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNBE_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNBE_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), !(getB_CF() | getB_ZF()));
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), !(getB_CF() | getB_ZF()));
BX_NEXT_INSTR(i);
}
@ -174,7 +174,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETS_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETS_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), getB_SF());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), getB_SF());
BX_NEXT_INSTR(i);
}
@ -191,7 +191,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNS_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNS_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), !getB_SF());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), !getB_SF());
BX_NEXT_INSTR(i);
}
@ -208,7 +208,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETP_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETP_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), getB_PF());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), getB_PF());
BX_NEXT_INSTR(i);
}
@ -225,7 +225,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNP_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNP_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), !getB_PF());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), !getB_PF());
BX_NEXT_INSTR(i);
}
@ -242,7 +242,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETL_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETL_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), (getB_SF() ^ getB_OF()));
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), (getB_SF() ^ getB_OF()));
BX_NEXT_INSTR(i);
}
@ -259,7 +259,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNL_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNL_EbR(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), !(getB_SF() ^ getB_OF()));
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), !(getB_SF() ^ getB_OF()));
BX_NEXT_INSTR(i);
}
@ -277,7 +277,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETLE_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETLE_EbR(bxInstruction_c *i)
{
Bit8u result_8 = getB_ZF() | (getB_SF() ^ getB_OF());
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
BX_NEXT_INSTR(i);
}
@ -295,7 +295,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNLE_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNLE_EbR(bxInstruction_c *i)
{
Bit8u result_8 = !(getB_ZF() | (getB_SF() ^ getB_OF()));
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
BX_NEXT_INSTR(i);
}
@ -303,16 +303,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNLE_EbR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_RX(bxInstruction_c *i)
{
BX_ERROR(("BSWAP with 16-bit opsize: undefined behavior !"));
BX_WRITE_16BIT_REG(i->rm(), 0);
BX_WRITE_16BIT_REG(i->dst(), 0);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
{
Bit32u val32 = BX_READ_32BIT_REG(i->rm());
Bit32u val32 = BX_READ_32BIT_REG(i->dst());
BX_WRITE_32BIT_REGZ(i->rm(), bx_bswap32(val32));
BX_WRITE_32BIT_REGZ(i->dst(), bx_bswap32(val32));
BX_NEXT_INSTR(i);
}
@ -320,9 +320,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
#if BX_SUPPORT_X86_64
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_RRX(bxInstruction_c *i)
{
Bit64u val64 = BX_READ_64BIT_REG(i->rm());
Bit64u val64 = BX_READ_64BIT_REG(i->dst());
BX_WRITE_64BIT_REG(i->rm(), bx_bswap64(val64));
BX_WRITE_64BIT_REG(i->dst(), bx_bswap64(val64));
BX_NEXT_INSTR(i);
}
@ -335,14 +335,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_GwMw(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16u val16 = read_virtual_word(i->seg(), eaddr);
BX_WRITE_16BIT_REG(i->nnn(), bx_bswap16(val16));
BX_WRITE_16BIT_REG(i->dst(), bx_bswap16(val16));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_MwGw(bxInstruction_c *i)
{
Bit16u val16 = BX_READ_16BIT_REG(i->nnn());
Bit16u val16 = BX_READ_16BIT_REG(i->src());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_word(i->seg(), eaddr, bx_bswap16(val16));
@ -355,14 +355,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_GdMd(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u val32 = read_virtual_dword(i->seg(), eaddr);
BX_WRITE_32BIT_REGZ(i->nnn(), bx_bswap32(val32));
BX_WRITE_32BIT_REGZ(i->dst(), bx_bswap32(val32));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_MdGd(bxInstruction_c *i)
{
Bit32u val32 = BX_READ_32BIT_REG(i->nnn());
Bit32u val32 = BX_READ_32BIT_REG(i->src());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dword(i->seg(), eaddr, bx_bswap32(val32));
@ -377,14 +377,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_GqMq(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit64u val64 = read_virtual_qword(i->seg(), eaddr);
BX_WRITE_64BIT_REG(i->nnn(), bx_bswap64(val64));
BX_WRITE_64BIT_REG(i->dst(), bx_bswap64(val64));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_MqGq(bxInstruction_c *i)
{
Bit64u val64 = BX_READ_64BIT_REG(i->nnn());
Bit64u val64 = BX_READ_64BIT_REG(i->src());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_qword_64(i->seg(), eaddr, bx_bswap64(val64));

68
bochs/cpu/bit16.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -28,7 +28,7 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GwEwR(bxInstruction_c *i)
{
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
if (op2_16 == 0) {
assert_ZF(); /* op1_16 undefined */
@ -43,8 +43,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GwEwR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
clear_ZF();
/* now write result back to destination */
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
}
BX_NEXT_INSTR(i);
@ -52,7 +51,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GwEwR(bxInstruction_c *i)
{
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
if (op2_16 == 0) {
assert_ZF(); /* op1_16 undefined */
@ -67,8 +66,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GwEwR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
clear_ZF();
/* now write result back to destination */
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
}
BX_NEXT_INSTR(i);
@ -82,7 +80,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->src());
index = op2_16 & 0xf;
displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;
op1_addr = eaddr + 2 * displacement32;
@ -99,8 +97,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = BX_READ_16BIT_REG(i->src());
op2_16 &= 0xf;
set_CF((op1_16 >> op2_16) & 0x01);
@ -116,7 +114,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->src());
index = op2_16 & 0xf;
displacement32 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
op1_addr = eaddr + 2 * displacement32;
@ -136,14 +134,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = BX_READ_16BIT_REG(i->src());
op2_16 &= 0xf;
set_CF((op1_16 >> op2_16) & 0x01);
op1_16 |= (1 << op2_16);
/* now write result back to the destination */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
BX_NEXT_INSTR(i);
}
@ -156,7 +154,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->src());
index = op2_16 & 0xf;
displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;
op1_addr = eaddr + 2 * displacement32;
@ -178,14 +176,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = BX_READ_16BIT_REG(i->src());
op2_16 &= 0xf;
set_CF((op1_16 >> op2_16) & 0x01);
op1_16 &= ~(1 << op2_16);
/* now write result back to the destination */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
BX_NEXT_INSTR(i);
}
@ -198,7 +196,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->src());
index_16 = op2_16 & 0xf;
displacement16 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
op1_addr = eaddr + 2 * displacement16;
@ -217,13 +215,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = BX_READ_16BIT_REG(i->src());
op2_16 &= 0xf;
bx_bool temp_CF = (op1_16 >> op2_16) & 0x01;
op1_16 ^= (1 << op2_16); /* toggle bit */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
set_CF(temp_CF);
@ -244,7 +242,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwIbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwIbR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit8u op2_8 = i->Ib() & 0xf;
set_CF((op1_16 >> op2_8) & 0x01);
@ -272,10 +270,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwIbR(bxInstruction_c *i)
{
Bit8u op2_8 = i->Ib() & 0xf;
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
op1_16 |= (1 << op2_8);
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
set_CF(temp_CF);
@ -302,10 +300,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwIbR(bxInstruction_c *i)
{
Bit8u op2_8 = i->Ib() & 0xf;
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
op1_16 ^= (1 << op2_8); /* toggle bit */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
set_CF(temp_CF);
@ -332,10 +330,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwIbR(bxInstruction_c *i)
{
Bit8u op2_8 = i->Ib() & 0xf;
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
op1_16 &= ~(1 << op2_8);
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
set_CF(temp_CF);
@ -345,7 +343,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwIbR(bxInstruction_c *i)
/* F3 0F B8 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GwEwR(bxInstruction_c *i)
{
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
Bit16u op1_16 = 0;
while (op2_16 != 0) {
@ -356,7 +354,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GwEwR(bxInstruction_c *i)
Bit32u flags = op1_16 ? 0 : EFlagsZFMask;
setEFlagsOSZAPC(flags);
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
BX_NEXT_INSTR(i);
}
@ -364,7 +362,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GwEwR(bxInstruction_c *i)
/* F3 0F BC */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GwEwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->src());
Bit16u mask = 0x1, result_16 = 0;
while ((op1_16 & mask) == 0 && mask) {
@ -375,7 +373,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GwEwR(bxInstruction_c *i)
set_CF(! op1_16);
set_ZF(! result_16);
BX_WRITE_16BIT_REG(i->nnn(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
BX_NEXT_INSTR(i);
}
@ -383,7 +381,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GwEwR(bxInstruction_c *i)
/* F3 0F BD */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LZCNT_GwEwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->src());
Bit16u mask = 0x8000, result_16 = 0;
while ((op1_16 & mask) == 0 && mask) {
@ -394,7 +392,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LZCNT_GwEwR(bxInstruction_c *i)
set_CF(! op1_16);
set_ZF(! result_16);
BX_WRITE_16BIT_REG(i->nnn(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
BX_NEXT_INSTR(i);
}

68
bochs/cpu/bit32.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -28,7 +28,7 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GdEdR(bxInstruction_c *i)
{
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
if (op2_32 == 0) {
assert_ZF(); /* op1_32 undefined */
@ -43,8 +43,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GdEdR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
clear_ZF();
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
}
BX_NEXT_INSTR(i);
@ -52,7 +51,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GdEdR(bxInstruction_c *i)
{
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
if (op2_32 == 0) {
assert_ZF(); /* op1_32 undefined */
@ -67,8 +66,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GdEdR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
clear_ZF();
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
}
BX_NEXT_INSTR(i);
@ -82,7 +80,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
index = op2_32 & 0x1f;
displacement32 = ((Bit32s) (op2_32&0xffffffe0)) / 32;
op1_addr = eaddr + 4 * displacement32;
@ -99,8 +97,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
op2_32 &= 0x1f;
set_CF((op1_32 >> op2_32) & 0x01);
@ -117,7 +115,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
index = op2_32 & 0x1f;
displacement32 = ((Bit32s) (op2_32&0xffffffe0)) / 32;
op1_addr = eaddr + 4 * displacement32;
@ -139,14 +137,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
op2_32 &= 0x1f;
set_CF((op1_32 >> op2_32) & 0x01);
op1_32 |= (1 << op2_32);
/* now write result back to the destination */
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
@ -159,7 +157,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
index = op2_32 & 0x1f;
displacement32 = ((Bit32s) (op2_32&0xffffffe0)) / 32;
op1_addr = eaddr + 4 * displacement32;
@ -182,14 +180,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
op2_32 &= 0x1f;
set_CF((op1_32 >> op2_32) & 0x01);
op1_32 &= ~(1 << op2_32);
/* now write result back to the destination */
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
@ -202,7 +200,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
index_32 = op2_32 & 0x1f;
displacement32 = ((Bit32s) (op2_32 & 0xffffffe0)) / 32;
@ -222,15 +220,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
op2_32 &= 0x1f;
bx_bool temp_CF = (op1_32 >> op2_32) & 0x01;
op1_32 ^= (1 << op2_32); /* toggle bit */
set_CF(temp_CF);
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
@ -249,7 +247,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EdIbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EdIbR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
Bit8u op2_8 = i->Ib() & 0x1f;
set_CF((op1_32 >> op2_8) & 0x01);
@ -277,10 +275,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EdIbR(bxInstruction_c *i)
{
Bit8u op2_8 = i->Ib() & 0x1f;
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
op1_32 |= (1 << op2_8);
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
set_CF(temp_CF);
@ -307,10 +305,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EdIbR(bxInstruction_c *i)
{
Bit8u op2_8 = i->Ib() & 0x1f;
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
op1_32 ^= (1 << op2_8); /* toggle bit */
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
set_CF(temp_CF);
@ -337,10 +335,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EdIbR(bxInstruction_c *i)
{
Bit8u op2_8 = i->Ib() & 0x1f;
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
op1_32 &= ~(1 << op2_8);
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
set_CF(temp_CF);
@ -350,7 +348,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EdIbR(bxInstruction_c *i)
/* F3 0F B8 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GdEdR(bxInstruction_c *i)
{
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
Bit32u op1_32 = 0;
while (op2_32 != 0) {
@ -361,7 +359,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GdEdR(bxInstruction_c *i)
Bit32u flags = op1_32 ? 0 : EFlagsZFMask;
setEFlagsOSZAPC(flags);
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
@ -369,7 +367,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GdEdR(bxInstruction_c *i)
/* F3 0F BC */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src());
Bit32u mask = 0x1, result_32 = 0;
while ((op1_32 & mask) == 0 && mask) {
@ -380,7 +378,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GdEdR(bxInstruction_c *i)
set_CF(! op1_32);
set_ZF(! result_32);
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
@ -388,7 +386,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GdEdR(bxInstruction_c *i)
/* F3 0F BD */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LZCNT_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src());
Bit32u mask = 0x80000000, result_32 = 0;
while ((op1_32 & mask) == 0 && mask) {
@ -399,7 +397,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LZCNT_GdEdR(bxInstruction_c *i)
set_CF(! op1_32);
set_ZF(! result_32);
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}

68
bochs/cpu/bit64.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -28,7 +28,7 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GqEqR(bxInstruction_c *i)
{
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
if (op2_64 == 0) {
assert_ZF(); /* op1_64 undefined */
@ -43,8 +43,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GqEqR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
clear_ZF();
/* now write result back to destination */
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
}
BX_NEXT_INSTR(i);
@ -52,7 +51,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GqEqR(bxInstruction_c *i)
{
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
if (op2_64 == 0) {
assert_ZF(); /* op1_64 undefined */
@ -67,8 +66,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GqEqR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
clear_ZF();
/* now write result back to destination */
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
}
BX_NEXT_INSTR(i);
@ -83,7 +81,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EqGqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
index = op2_64 & 0x3f;
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
op1_addr = eaddr + 8 * displacement64;
@ -102,8 +100,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op2_64 &= 0x3f;
set_CF((op1_64 >> op2_64) & 0x01);
@ -119,7 +117,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EqGqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
index = op2_64 & 0x3f;
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
op1_addr = eaddr + 8 * displacement64;
@ -141,14 +139,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op2_64 &= 0x3f;
set_CF((op1_64 >> op2_64) & 0x01);
op1_64 |= (((Bit64u) 1) << op2_64);
/* now write result back to the destination */
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
@ -161,7 +159,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EqGqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
index = op2_64 & 0x3f;
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
op1_addr = eaddr + 8 * displacement64;
@ -184,14 +182,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op2_64 &= 0x3f;
set_CF((op1_64 >> op2_64) & 0x01);
op1_64 &= ~(((Bit64u) 1) << op2_64);
/* now write result back to the destination */
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
@ -205,7 +203,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EqGqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
index = op2_64 & 0x3f;
displacement64 = ((Bit64s) (op2_64 & BX_CONST64(0xffffffffffffffc0))) / 64;
op1_addr = eaddr + 8 * displacement64;
@ -226,15 +224,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op2_64 &= 0x3f;
bx_bool temp_CF = (op1_64 >> op2_64) & 0x01;
op1_64 ^= (((Bit64u) 1) << op2_64); /* toggle bit */
set_CF(temp_CF);
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
@ -253,7 +251,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EqIbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EqIbR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
Bit8u op2_8 = i->Ib() & 0x3f;
set_CF((op1_64 >> op2_8) & 0x01);
@ -281,10 +279,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EqIbR(bxInstruction_c *i)
{
Bit8u op2_8 = i->Ib() & 0x3f;
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
op1_64 |= (((Bit64u) 1) << op2_8);
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
set_CF(temp_CF);
@ -311,10 +309,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EqIbR(bxInstruction_c *i)
{
Bit8u op2_8 = i->Ib() & 0x3f;
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
op1_64 ^= (((Bit64u) 1) << op2_8); /* toggle bit */
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
set_CF(temp_CF);
@ -341,10 +339,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EqIbR(bxInstruction_c *i)
{
Bit8u op2_8 = i->Ib() & 0x3f;
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
bx_bool temp_CF = (op1_64 >> op2_8) & 0x01;
op1_64 &= ~(((Bit64u) 1) << op2_8);
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
set_CF(temp_CF);
@ -354,7 +352,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EqIbR(bxInstruction_c *i)
/* F3 0F B8 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GqEqR(bxInstruction_c *i)
{
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
Bit64u op1_64 = 0;
while (op2_64 != 0) {
@ -365,7 +363,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GqEqR(bxInstruction_c *i)
Bit32u flags = op1_64 ? 0 : EFlagsZFMask;
setEFlagsOSZAPC(flags);
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
@ -373,7 +371,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GqEqR(bxInstruction_c *i)
/* F3 0F BC */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->src());
Bit64u mask = 0x1, result_64 = 0;
while ((op1_64 & mask) == 0 && mask) {
@ -384,7 +382,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GqEqR(bxInstruction_c *i)
set_CF(! op1_64);
set_ZF(! result_64);
BX_WRITE_64BIT_REG(i->nnn(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
@ -392,7 +390,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GqEqR(bxInstruction_c *i)
/* F3 0F BD */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LZCNT_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm()), result_64 = 0;
Bit64u op1_64 = BX_READ_64BIT_REG(i->src()), result_64 = 0;
Bit64u mask = BX_CONST64(0x8000000000000000);
while ((op1_64 & mask) == 0 && mask) {
@ -403,7 +401,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LZCNT_GqEqR(bxInstruction_c *i)
set_CF(! op1_64);
set_ZF(! result_64);
BX_WRITE_64BIT_REG(i->nnn(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}

84
bochs/cpu/bmi32.cc
View File

@ -29,14 +29,14 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ANDN_GdBdEdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->vvv());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src2());
op1_32 = op1_32 & ~op2_32;
op1_32 = ~op1_32 & op2_32;
SET_FLAGS_OSZAxC_LOGIC_32(op1_32); // keep PF unchanged
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
@ -44,18 +44,18 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ANDN_GdBdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULX_GdBdEdR(bxInstruction_c *i)
{
Bit32u op1_32 = EDX;
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src2());
Bit64u product_64 = ((Bit64u) op1_32) * ((Bit64u) op2_32);
BX_WRITE_32BIT_REGZ(i->vvv(), GET32L(product_64));
BX_WRITE_32BIT_REGZ(i->nnn(), GET32H(product_64));
BX_WRITE_32BIT_REGZ(i->src1(), GET32L(product_64));
BX_WRITE_32BIT_REGZ(i->dst(), GET32H(product_64));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSI_BdEdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src());
bx_bool tmpCF = (op1_32 != 0);
op1_32 = (-op1_32) & op1_32;
@ -63,14 +63,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSI_BdEdR(bxInstruction_c *i)
SET_FLAGS_OSZAxC_LOGIC_32(op1_32); // keep PF unchanged
set_CF(tmpCF);
BX_WRITE_32BIT_REGZ(i->vvv(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSMSK_BdEdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src());
bx_bool tmpCF = (op1_32 == 0);
op1_32 = (op1_32-1) ^ op1_32;
@ -78,14 +78,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSMSK_BdEdR(bxInstruction_c *i)
SET_FLAGS_OSZAxC_LOGIC_32(op1_32); // keep PF unchanged
set_CF(tmpCF);
BX_WRITE_32BIT_REGZ(i->vvv(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSR_BdEdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src());
bx_bool tmpCF = (op1_32 == 0);
op1_32 = (op1_32-1) & op1_32;
@ -93,75 +93,75 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSR_BdEdR(bxInstruction_c *i)
SET_FLAGS_OSZAxC_LOGIC_32(op1_32); // keep PF unchanged
set_CF(tmpCF);
BX_WRITE_32BIT_REGZ(i->vvv(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RORX_GdEdIbR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src());
unsigned count = i->Ib() & 0x1f;
if (count) {
op1_32 = (op1_32 >> count) | (op1_32 << (32 - count));
}
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRX_GdEdBdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x1f;
unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x1f;
if (count)
op1_32 >>= count;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SARX_GdEdBdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x1f;
unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x1f;
if (count) {
/* count < 32, since only lower 5 bits used */
op1_32 = ((Bit32s) op1_32) >> count;
}
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLX_GdEdBdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x1f;
unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x1f;
if (count)
op1_32 <<= count;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GdEdBdR(bxInstruction_c *i)
{
Bit16u control = BX_READ_16BIT_REG(i->vvv());
Bit16u control = BX_READ_16BIT_REG(i->src2());
unsigned start = control & 0xff;
unsigned len = control >> 8;
Bit32u op1_32 = 0;
if (start < 32 && len > 0) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->src1());
op1_32 >>= start;
if (len < 32) {
@ -172,16 +172,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GdEdBdR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BZHI_GdEdBdR(bxInstruction_c *i)
{
unsigned control = BX_READ_16BIT_REG(i->vvv()) & 0xff;
unsigned control = BX_READ_16BIT_REG(i->src1()) & 0xff;
bx_bool tmpCF = 0;
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->src2());
if (control < 32) {
Bit32u mask = (1 << control) - 1;
@ -194,7 +194,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BZHI_GdEdBdR(bxInstruction_c *i)
SET_FLAGS_OSZAxC_LOGIC_32(op1_32); // keep PF unchanged
set_CF(tmpCF);
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
@ -202,8 +202,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BZHI_GdEdBdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXT_GdEdBdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->vvv());
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm()), result_32 = 0;
Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src2()), result_32 = 0;
Bit32u wr_mask = 0x1;
@ -216,15 +216,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXT_GdEdBdR(bxInstruction_c *i)
op1_32 >>= 1;
}
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PDEP_GdEdBdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->vvv());
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm()), result_32 = 0;
Bit32u op1_32 = BX_READ_32BIT_REG(i->src1());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src2()), result_32 = 0;
Bit32u wr_mask = 0x1;
@ -237,7 +237,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PDEP_GdEdBdR(bxInstruction_c *i)
wr_mask <<= 1;
}
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
@ -246,11 +246,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PDEP_GdEdBdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADCX_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->nnn());
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
Bit32u sum_32 = op1_32 + op2_32 + getB_CF();
BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
Bit32u carry_out = ADD_COUT_VEC(op1_32, op2_32, sum_32);
set_CF(carry_out >> 31);
@ -260,11 +260,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADCX_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADOX_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->nnn());
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
Bit32u sum_32 = op1_32 + op2_32 + getB_OF();
BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
BX_WRITE_32BIT_REGZ(i->dst(), sum_32);
Bit32u overflow = GET_ADD_OVERFLOW(op1_32, op2_32, sum_32, 0x80000000);
set_OF(!!overflow);

84
bochs/cpu/bmi64.cc
View File

@ -31,14 +31,14 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ANDN_GqBqEqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op2_64 = BX_READ_64BIT_REG(i->vvv());
Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src2());
op1_64 = op1_64 & ~op2_64;
op1_64 = ~op1_64 & op2_64;
SET_FLAGS_OSZAxC_LOGIC_64(op1_64); // keep PF unchanged
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
@ -48,7 +48,7 @@ extern void long_mul(Bit128u *product, Bit64u op1, Bit64u op2);
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULX_GqBqEqR(bxInstruction_c *i)
{
Bit64u op1_64 = RDX;
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src2());
Bit128u product_128;
@ -58,15 +58,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULX_GqBqEqR(bxInstruction_c *i)
long_mul(&product_128,op1_64,op2_64);
BX_WRITE_64BIT_REG(i->vvv(), product_128.lo);
BX_WRITE_64BIT_REG(i->nnn(), product_128.hi);
BX_WRITE_64BIT_REG(i->src1(), product_128.lo);
BX_WRITE_64BIT_REG(i->dst(), product_128.hi);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSI_BqEqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->src());
bx_bool tmpCF = (op1_64 != 0);
op1_64 = (-op1_64) & op1_64;
@ -74,14 +74,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSI_BqEqR(bxInstruction_c *i)
SET_FLAGS_OSZAxC_LOGIC_64(op1_64); // keep PF unchanged
set_CF(tmpCF);
BX_WRITE_64BIT_REG(i->vvv(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSMSK_BqEqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->src());
bx_bool tmpCF = (op1_64 == 0);
op1_64 = (op1_64-1) ^ op1_64;
@ -89,14 +89,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSMSK_BqEqR(bxInstruction_c *i)
SET_FLAGS_OSZAxC_LOGIC_64(op1_64); // keep PF unchanged
set_CF(tmpCF);
BX_WRITE_64BIT_REG(i->vvv(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSR_BqEqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->src());
bx_bool tmpCF = (op1_64 == 0);
op1_64 = (op1_64-1) & op1_64;
@ -104,75 +104,75 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSR_BqEqR(bxInstruction_c *i)
SET_FLAGS_OSZAxC_LOGIC_64(op1_64); // keep PF unchanged
set_CF(tmpCF);
BX_WRITE_64BIT_REG(i->vvv(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RORX_GqEqIbR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->src());
unsigned count = i->Ib() & 0x3f;
if (count) {
op1_64 = (op1_64 >> count) | (op1_64 << (64 - count));
}
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRX_GqEqBqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x3f;
unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x3f;
if (count)
op1_64 >>= count;
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SARX_GqEqBqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x3f;
unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x3f;
if (count) {
/* count < 64, since only lower 6 bits used */
op1_64 = ((Bit64s) op1_64) >> count;
}
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLX_GqEqBqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x3f;
unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x3f;
if (count)
op1_64 <<= count;
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GqEqBqR(bxInstruction_c *i)
{
Bit16u control = BX_READ_16BIT_REG(i->vvv());
Bit16u control = BX_READ_16BIT_REG(i->src2());
unsigned start = control & 0xff;
unsigned len = control >> 8;
Bit64u op1_64 = 0;
if (start < 64 && len > 0) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->src1());
op1_64 >>= start;
if (len < 64) {
@ -183,16 +183,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GqEqBqR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BZHI_GqEqBqR(bxInstruction_c *i)
{
unsigned control = BX_READ_16BIT_REG(i->vvv()) & 0xff;
unsigned control = BX_READ_16BIT_REG(i->src1()) & 0xff;
bx_bool tmpCF = 0;
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->src2());
if (control < 64) {
Bit64u mask = (BX_CONST64(1) << control) - 1;
@ -205,15 +205,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BZHI_GqEqBqR(bxInstruction_c *i)
SET_FLAGS_OSZAxC_LOGIC_64(op1_64); // keep PF unchanged
set_CF(tmpCF);
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXT_GqEqBqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->vvv());
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm()), result_64 = 0;
Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src2()), result_64 = 0;
Bit64u wr_mask = 0x1;
@ -226,15 +226,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXT_GqEqBqR(bxInstruction_c *i)
op1_64 >>= 1;
}
BX_WRITE_64BIT_REG(i->nnn(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PDEP_GqEqBqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->vvv());
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm()), result_64 = 0;
Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src2()), result_64 = 0;
Bit64u wr_mask = 0x1;
@ -247,7 +247,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PDEP_GqEqBqR(bxInstruction_c *i)
wr_mask <<= 1;
}
BX_WRITE_64BIT_REG(i->nnn(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
@ -256,11 +256,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PDEP_GqEqBqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADCX_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->nnn());
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
Bit64u sum_64 = op1_64 + op2_64 + getB_CF();
BX_WRITE_64BIT_REG(i->nnn(), sum_64);
BX_WRITE_64BIT_REG(i->dst(), sum_64);
Bit64u carry_out = ADD_COUT_VEC(op1_64, op2_64, sum_64);
set_CF(carry_out >> 63);
@ -270,11 +270,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADCX_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADOX_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->nnn());
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
Bit64u sum_64 = op1_64 + op2_64 + getB_OF();
BX_WRITE_64BIT_REG(i->nnn(), sum_64);
BX_WRITE_64BIT_REG(i->dst(), sum_64);
Bit64u overflow = GET_ADD_OVERFLOW(op1_64, op2_64, sum_64, BX_CONST64(0x8000000000000000));
set_OF(!!overflow);

179
bochs/cpu/cpu.h
View File

@ -1382,33 +1382,6 @@ public: // for now...
// <TAG-CLASS-CPU-START>
// prototypes for CPU instructions...
BX_SMF BX_INSF_TYPE ADD_ALIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE OR_ALIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE ADC_ALIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SBB_ALIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AND_ALIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SUB_ALIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE XOR_ALIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE CMP_ALIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE ADD_AXIw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE OR_AXIw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE ADC_AXIw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SBB_AXIw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AND_AXIw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SUB_AXIw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE XOR_AXIw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE CMP_AXIw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE ADD_EAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE OR_EAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE ADC_EAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SBB_EAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AND_EAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SUB_EAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE XOR_EAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE CMP_EAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PUSH16_Sw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE POP16_Sw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PUSH32_Sw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -1506,9 +1479,6 @@ public: // for now...
BX_SMF BX_INSF_TYPE MOV_OdAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOV_OdEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOV_OdAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE TEST_ALIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE TEST_EAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE TEST_AXIw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
// repeatable instructions
BX_SMF BX_INSF_TYPE REP_MOVSB_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2432,7 +2402,7 @@ public: // for now...
BX_SMF BX_INSF_TYPE MOVQ_VqWqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE CMPPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE CMPSD_VsdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRW_VdqEwIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRW_VdqHdqEwIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PEXTRW_GdUdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SHUFPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PSRLW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2587,12 +2557,12 @@ public: // for now...
BX_SMF BX_INSF_TYPE PEXTRD_EdVdqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE EXTRACTPS_EdVpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE EXTRACTPS_EdVpsIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRB_VdqEbIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE INSERTPS_VpsWssIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRD_VdqEdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRD_VdqEdIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRB_VdqHdqEbIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE INSERTPS_VpsHpsWssIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRD_VdqHdqEdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRD_VdqHdqEdIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE DPPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE DPPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE DPPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MPSADBW_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* SSE4.1 */
@ -2632,12 +2602,12 @@ public: // for now...
#if BX_CPU_LEVEL >= 6
/* AES instructions */
BX_SMF BX_INSF_TYPE AESIMC_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AESENC_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AESENCLAST_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AESDEC_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AESDECLAST_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AESENC_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AESENCLAST_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AESDEC_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AESDECLAST_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AESKEYGENASSIST_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PCLMULQDQ_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PCLMULQDQ_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* AES instructions */
#endif
@ -2649,8 +2619,8 @@ public: // for now...
BX_SMF BX_INSF_TYPE VMCLEAR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMPTRLD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMPTRST(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMREAD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMWRITE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMREAD_EdGd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMWRITE_GdEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMFUNC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* VMX instructions */
@ -2924,66 +2894,26 @@ public: // for now...
/* AVX2 */
/* AVX2 FMA */
BX_SMF BX_INSF_TYPE VFMADD132PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD213PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD231PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD132PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD213PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD231PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD132SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD213SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD231SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD132SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD213SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADD231SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSUB132PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSUB213PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSUB231PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSUB132PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSUB213PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSUB231PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBADD132PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBADD213PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBADD231PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBADD132PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBADD213PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBADD231PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB132PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB213PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB231PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB132PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB213PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB231PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB132SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB213SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB231SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB132SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB213SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUB231SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD132PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD213PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD231PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD132PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD213PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD231PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD132SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD213SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD231SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD132SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD213SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADD231SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB132PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB213PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB231PD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB132PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB213PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB231PS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB132SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB213SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB231SD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB132SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB213SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUB231SS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADDSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADDSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUBSD_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUBSS_VpsHssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* AVX2 FMA */
/* BMI */
@ -3016,28 +2946,16 @@ public: // for now...
BX_SMF BX_INSF_TYPE PDEP_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* BMI */
/* FMA4 (AMD) */
BX_SMF BX_INSF_TYPE VFMADDSUBPS_VpsHpsWpsVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSUBPD_VpdHpdWpdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBADDPS_VpsHpsWpsVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBADDPD_VpdHpdWpdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDPS_VpsHpsWpsVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDPD_VpdHpdWpdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* FMA4 specific handlers (AMD) */
BX_SMF BX_INSF_TYPE VFMADDSS_VssHssWssVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSD_VsdHsdWsdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBPS_VpsHpsWpsVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBPD_VpdHpdWpdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBSS_VssHssWssVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMSUBSD_VsdHsdWsdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADDPS_VpsHpsWpsVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADDPD_VpdHpdWpdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADDSS_VssHssWssVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMADDSD_VsdHsdWsdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUBPS_VpsHpsWpsVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUBPD_VpdHpdWpdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUBSS_VssHssWssVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFNMSUBSD_VsdHsdWsdVIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* FMA4 (AMD) */
/* FMA4 specific handlers (AMD) */
/* XOP (AMD) */
BX_SMF BX_INSF_TYPE VPCMOV_VdqHdqWdqVIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -3271,15 +3189,6 @@ public: // for now...
BX_SMF BX_INSF_TYPE XOR_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE CMP_GqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE ADD_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE OR_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE ADC_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SBB_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE AND_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SUB_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE XOR_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE CMP_RAXId(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE ADD_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE OR_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE ADC_EqGqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -4361,7 +4270,7 @@ public: // for now...
BX_SMF void VMX_Write_VTPR(Bit8u vtpr);
#endif
// vmexit reasons
BX_SMF void VMexit_Instruction(bxInstruction_c *i, Bit32u reason) BX_CPP_AttrRegparmN(2);
BX_SMF void VMexit_Instruction(bxInstruction_c *i, Bit32u reason, bx_bool rw = BX_READ) BX_CPP_AttrRegparmN(3);
BX_SMF void VMexit_Event(unsigned type, unsigned vector,
Bit16u errcode, bx_bool errcode_valid, Bit64u qualification = 0);
BX_SMF void VMexit_TripleFault(void);
@ -4381,7 +4290,7 @@ public: // for now...
BX_SMF bx_address VMexit_CR4_Write(bxInstruction_c *i, bx_address) BX_CPP_AttrRegparmN(2);
BX_SMF void VMexit_CR8_Read(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF void VMexit_CR8_Write(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF void VMexit_DR_Access(bxInstruction_c *i, unsigned read) BX_CPP_AttrRegparmN(2);
BX_SMF void VMexit_DR_Access(unsigned read, unsigned dr, unsigned reg);
#if BX_SUPPORT_VMX >= 2
BX_SMF void vmfunc_eptp_switching(void);
#endif
@ -4877,11 +4786,13 @@ enum {
#if BX_SUPPORT_X86_64
#define BxImmediate_Iq 0x0007 // 64 bit override
#endif
#define BxImmediate_Ib4 0x0008 // Register encoded in Ib[7:4]
#define BxImmediate_BrOff8 0x0009 // Relative branch offset byte
#define BxImmediate_BrOff8 0x0008 // Relative branch offset byte
#define BxImmediate_BrOff16 BxImmediate_Iw // Relative branch offset word, not encodable in 64-bit mode
#define BxImmediate_BrOff32 BxImmediate_Id // Relative branch offset dword
#define BxImmediate_Ib4 BxImmediate_Ib // Register encoded in Ib[7:4]
#define BxImmediate_Ib5 BxImmediate_Ib
#define BxImmediate_BrOff16 BxImmediate_Iw // Relative branch offset word, not encodable in 64-bit mode
#define BxImmediate_BrOff32 BxImmediate_Id // Relative branch offset dword
// Lookup for opcode and attributes in another opcode tables
// Totally 15 opcode groups supported
@ -4908,11 +4819,11 @@ enum {
#define BxImmediate_Id2 0x0300
#define BxLockable 0x0400 // bit 10
#define BxArithDstRM 0x0800 // bit 11
#define BxRepeatable 0x0800 // bit 11
#define BxVexW0 0x1000 // bit 12
#define BxVexW1 0x2000 // bit 13
#define BxTraceEnd 0x4000 // bit 14
#define BxTraceEnd 0x8000 // bit 15
#ifdef BX_TRACE_CACHE_NO_SPECULATIVE_TRACING

30
bochs/cpu/crc32.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2011 Stanislav Shwartsman
// Copyright (c) 2008-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -74,9 +74,9 @@ static Bit32u mod2_64bit(Bit64u divisor, Bit64u dividend)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEbR(bxInstruction_c *i)
{
Bit8u op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op1 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u op2 = BX_READ_32BIT_REG(i->nnn());
Bit32u op2 = BX_READ_32BIT_REG(i->dst());
op2 = BitReflect32(op2);
Bit64u tmp1 = ((Bit64u) BitReflect8 (op1)) << 32;
@ -84,42 +84,39 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEbR(bxInstruction_c *i)
Bit64u tmp3 = tmp1 ^ tmp2;
op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
BX_WRITE_32BIT_REGZ(i->dst(), BitReflect32(op2));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEwR(bxInstruction_c *i)
{
Bit32u op2 = BX_READ_32BIT_REG(i->nnn());
Bit32u op2 = BX_READ_32BIT_REG(i->dst());
op2 = BitReflect32(op2);
Bit16u op1 = BX_READ_16BIT_REG(i->rm());
Bit16u op1 = BX_READ_16BIT_REG(i->src());
Bit64u tmp1 = ((Bit64u) BitReflect16(op1)) << 32;
Bit64u tmp2 = ((Bit64u) op2) << 16;
Bit64u tmp3 = tmp1 ^ tmp2;
op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
BX_WRITE_32BIT_REGZ(i->dst(), BitReflect32(op2));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEdR(bxInstruction_c *i)
{
Bit32u op2 = BX_READ_32BIT_REG(i->nnn());
Bit32u op2 = BX_READ_32BIT_REG(i->dst());
op2 = BitReflect32(op2);
Bit32u op1 = BX_READ_32BIT_REG(i->rm());
Bit32u op1 = BX_READ_32BIT_REG(i->src());
Bit64u tmp1 = ((Bit64u) BitReflect32(op1)) << 32;
Bit64u tmp2 = ((Bit64u) op2) << 32;
Bit64u tmp3 = tmp1 ^ tmp2;
op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
BX_WRITE_32BIT_REGZ(i->dst(), BitReflect32(op2));
BX_NEXT_INSTR(i);
}
@ -128,9 +125,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEqR(bxInstruction_c *i)
{
Bit32u op2 = BX_READ_32BIT_REG(i->nnn());
Bit32u op2 = BX_READ_32BIT_REG(i->dst());
op2 = BitReflect32(op2);
Bit64u op1 = BX_READ_64BIT_REG(i->rm());
Bit64u op1 = BX_READ_64BIT_REG(i->src());
Bit64u tmp1 = ((Bit64u) BitReflect32(op1 & 0xffffffff)) << 32;
Bit64u tmp2 = ((Bit64u) op2) << 32;
@ -141,8 +138,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEqR(bxInstruction_c *i)
tmp3 = tmp1 ^ tmp2;
op2 = mod2_64bit(CRC32_POLYNOMIAL, tmp3);
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
BX_WRITE_32BIT_REGZ(i->dst(), BitReflect32(op2));
BX_NEXT_INSTR(i);
}

134
bochs/cpu/crregs.cc
View File

@ -30,12 +30,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
{
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest)
VMexit_DR_Access(i, 0 /* write */);
VMexit_DR_Access(0 /* write */, i->dst(), i->src());
#endif
#if BX_CPU_LEVEL >= 5
if (BX_CPU_THIS_PTR cr4.get_DE()) {
if ((i->nnn() & 0xE) == 4) {
if ((i->dst() & 0xE) == 4) {
BX_ERROR(("MOV_DdRd: access to DR4/DR5 causes #UD"));
exception(BX_UD_EXCEPTION, 0);
}
@ -58,26 +58,20 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
#if BX_SUPPORT_SVM
if (BX_CPU_THIS_PTR in_svm_guest) {
if (SVM_DR_WRITE_INTERCEPTED(i->nnn())) Svm_Vmexit(SVM_VMEXIT_DR0_WRITE + i->nnn());
if (SVM_DR_WRITE_INTERCEPTED(i->dst())) Svm_Vmexit(SVM_VMEXIT_DR0_WRITE + i->dst());
}
#endif
invalidate_prefetch_q();
/* This instruction is always treated as a register-to-register,
* regardless of the encoding of the MOD field in the MODRM byte.
*/
if (!i->modC0())
BX_PANIC(("MOV_DdRd(): rm field not a register!"));
Bit32u val_32 = BX_READ_32BIT_REG(i->src());
Bit32u val_32 = BX_READ_32BIT_REG(i->rm());
switch (i->nnn()) {
switch (i->dst()) {
case 0: // DR0
case 1: // DR1
case 2: // DR2
case 3: // DR3
BX_CPU_THIS_PTR dr[i->nnn()] = val_32;
BX_CPU_THIS_PTR dr[i->dst()] = val_32;
TLB_invlpg(val_32);
break;
@ -141,12 +135,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest)
VMexit_DR_Access(i, 1 /* read */);
VMexit_DR_Access(1 /* read */, i->src(), i->dst());
#endif
#if BX_CPU_LEVEL >= 5
if (BX_CPU_THIS_PTR cr4.get_DE()) {
if ((i->nnn() & 0xE) == 4) {
if ((i->src() & 0xE) == 4) {
BX_ERROR(("MOV_RdDd: access to DR4/DR5 causes #UD"));
exception(BX_UD_EXCEPTION, 0);
}
@ -169,22 +163,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
#if BX_SUPPORT_SVM
if (BX_CPU_THIS_PTR in_svm_guest) {
if (SVM_DR_READ_INTERCEPTED(i->nnn())) Svm_Vmexit(SVM_VMEXIT_DR0_READ + i->nnn());
if (SVM_DR_READ_INTERCEPTED(i->src())) Svm_Vmexit(SVM_VMEXIT_DR0_READ + i->src());
}
#endif
/* This instruction is always treated as a register-to-register,
* regardless of the encoding of the MOD field in the MODRM byte.
*/
if (!i->modC0())
BX_PANIC(("MOV_RdDd(): rm field not a register!"));
switch (i->nnn()) {
switch (i->src()) {
case 0: // DR0
case 1: // DR1
case 2: // DR2
case 3: // DR3
val_32 = (Bit32u) BX_CPU_THIS_PTR dr[i->nnn()];
val_32 = (Bit32u) BX_CPU_THIS_PTR dr[i->src()];
break;
case 4: // DR4
@ -206,7 +194,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
exception(BX_UD_EXCEPTION, 0);
}
BX_WRITE_32BIT_REGZ(i->rm(), val_32);
BX_WRITE_32BIT_REGZ(i->dst(), val_32);
BX_NEXT_INSTR(i);
}
@ -216,17 +204,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
{
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest)
VMexit_DR_Access(i, 0 /* write */);
VMexit_DR_Access(0 /* write */, i->dst(), i->src());
#endif
if (BX_CPU_THIS_PTR cr4.get_DE()) {
if ((i->nnn() & 0xE) == 4) {
if ((i->dst() & 0xE) == 4) {
BX_ERROR(("MOV_DqRq: access to DR4/DR5 causes #UD"));
exception(BX_UD_EXCEPTION, 0);
}
}
if (i->nnn() >= 8) {
if (i->dst() >= 8) {
BX_ERROR(("MOV_DqRq: #UD - register index out of range"));
exception(BX_UD_EXCEPTION, 0);
}
@ -247,26 +235,20 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
#if BX_SUPPORT_SVM
if (BX_CPU_THIS_PTR in_svm_guest) {
if (SVM_DR_WRITE_INTERCEPTED(i->nnn())) Svm_Vmexit(SVM_VMEXIT_DR0_WRITE + i->nnn());
if (SVM_DR_WRITE_INTERCEPTED(i->dst())) Svm_Vmexit(SVM_VMEXIT_DR0_WRITE + i->dst());
}
#endif
invalidate_prefetch_q();
/* This instruction is always treated as a register-to-register,
* regardless of the encoding of the MOD field in the MODRM byte.
*/
if (!i->modC0())
BX_PANIC(("MOV_DqRq(): rm field not a register!"));
Bit64u val_64 = BX_READ_64BIT_REG(i->src());
Bit64u val_64 = BX_READ_64BIT_REG(i->rm());
switch (i->nnn()) {
switch (i->dst()) {
case 0: // DR0
case 1: // DR1
case 2: // DR2
case 3: // DR3
BX_CPU_THIS_PTR dr[i->nnn()] = val_64;
BX_CPU_THIS_PTR dr[i->dst()] = val_64;
TLB_invlpg(val_64);
break;
@ -328,17 +310,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest)
VMexit_DR_Access(i, 1 /* read */);
VMexit_DR_Access(1 /* read */, i->src(), i->dst());
#endif
if (BX_CPU_THIS_PTR cr4.get_DE()) {
if ((i->nnn() & 0xE) == 4) {
if ((i->src() & 0xE) == 4) {
BX_ERROR(("MOV_RqDq: access to DR4/DR5 causes #UD"));
exception(BX_UD_EXCEPTION, 0);
}
}
if (i->nnn() >= 8) {
if (i->src() >= 8) {
BX_ERROR(("MOV_RqDq: #UD - register index out of range"));
exception(BX_UD_EXCEPTION, 0);
}
@ -359,22 +341,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
#if BX_SUPPORT_SVM
if (BX_CPU_THIS_PTR in_svm_guest) {
if (SVM_DR_READ_INTERCEPTED(i->nnn())) Svm_Vmexit(SVM_VMEXIT_DR0_READ + i->nnn());
if (SVM_DR_READ_INTERCEPTED(i->src())) Svm_Vmexit(SVM_VMEXIT_DR0_READ + i->src());
}
#endif
/* This instruction is always treated as a register-to-register,
* regardless of the encoding of the MOD field in the MODRM byte.
*/
if (!i->modC0())
BX_PANIC(("MOV_RqDq(): rm field not a register!"));
switch (i->nnn()) {
switch (i->src()) {
case 0: // DR0
case 1: // DR1
case 2: // DR2
case 3: // DR3
val_64 = BX_CPU_THIS_PTR dr[i->nnn()];
val_64 = BX_CPU_THIS_PTR dr[i->src()];
break;
case 4: // DR4
@ -396,7 +372,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
exception(BX_UD_EXCEPTION, 0);
}
BX_WRITE_64BIT_REG(i->rm(), val_64);
BX_WRITE_64BIT_REG(i->dst(), val_64);
BX_NEXT_INSTR(i);
}
@ -412,9 +388,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR0Rd(bxInstruction_c *i)
invalidate_prefetch_q();
Bit32u val_32 = BX_READ_32BIT_REG(i->rm());
Bit32u val_32 = BX_READ_32BIT_REG(i->src());
if (i->nnn() == 0) {
if (i->dst() == 0) {
// CR0
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest)
@ -449,7 +425,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR2Rd(bxInstruction_c *i)
}
#endif
BX_CPU_THIS_PTR cr2 = BX_READ_32BIT_REG(i->rm());
BX_CPU_THIS_PTR cr2 = BX_READ_32BIT_REG(i->src());
BX_NEXT_INSTR(i);
}
@ -464,7 +440,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR3Rd(bxInstruction_c *i)
invalidate_prefetch_q();
Bit32u val_32 = BX_READ_32BIT_REG(i->rm());
Bit32u val_32 = BX_READ_32BIT_REG(i->src());
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest)
@ -499,7 +475,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR4Rd(bxInstruction_c *i)
invalidate_prefetch_q();
Bit32u val_32 = BX_READ_32BIT_REG(i->rm());
Bit32u val_32 = BX_READ_32BIT_REG(i->src());
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest)
val_32 = (Bit32u) VMexit_CR4_Write(i, val_32);
@ -523,7 +499,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR0(bxInstruction_c *i)
Bit32u val_32 = 0;
if (i->nnn() == 0) {
if (i->src() == 0) {
// CR0
val_32 = (Bit32u) read_CR0(); /* correctly handle VMX */
}
@ -534,7 +510,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR0(bxInstruction_c *i)
}
#endif
BX_WRITE_32BIT_REGZ(i->rm(), val_32);
BX_WRITE_32BIT_REGZ(i->dst(), val_32);
BX_NEXT_INSTR(i);
}
@ -553,7 +529,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR2(bxInstruction_c *i)
}
#endif
BX_WRITE_32BIT_REGZ(i->rm(), (Bit32u) BX_CPU_THIS_PTR cr2);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) BX_CPU_THIS_PTR cr2);
BX_NEXT_INSTR(i);
}
@ -579,7 +555,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR3(bxInstruction_c *i)
Bit32u val_32 = (Bit32u) BX_CPU_THIS_PTR cr3;
BX_WRITE_32BIT_REGZ(i->rm(), val_32);
BX_WRITE_32BIT_REGZ(i->dst(), val_32);
BX_NEXT_INSTR(i);
}
@ -595,7 +571,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR4(bxInstruction_c *i)
Bit32u val_32 = (Bit32u) read_CR4(); /* correctly handle VMX */
BX_WRITE_32BIT_REGZ(i->rm(), val_32);
BX_WRITE_32BIT_REGZ(i->dst(), val_32);
#endif
BX_NEXT_INSTR(i);
@ -611,9 +587,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR0Rq(bxInstruction_c *i)
invalidate_prefetch_q();
Bit64u val_64 = BX_READ_64BIT_REG(i->rm());
Bit64u val_64 = BX_READ_64BIT_REG(i->src());
if (i->nnn() == 0) {
if (i->dst() == 0) {
// CR0
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest)
@ -633,7 +609,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR0Rq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR2Rq(bxInstruction_c *i)
{
if (i->nnn() != 2) {
if (i->dst() != 2) {
BX_ERROR(("MOV_CR2Rq: #UD - register index out of range"));
exception(BX_UD_EXCEPTION, 0);
}
@ -649,14 +625,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR2Rq(bxInstruction_c *i)
}
#endif
BX_CPU_THIS_PTR cr2 = BX_READ_64BIT_REG(i->rm());
BX_CPU_THIS_PTR cr2 = BX_READ_64BIT_REG(i->src());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR3Rq(bxInstruction_c *i)
{
if (i->nnn() != 3) {
if (i->dst() != 3) {
BX_ERROR(("MOV_CR3Rq: #UD - register index out of range"));
exception(BX_UD_EXCEPTION, 0);
}
@ -668,7 +644,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR3Rq(bxInstruction_c *i)
invalidate_prefetch_q();
Bit64u val_64 = BX_READ_64BIT_REG(i->rm());
Bit64u val_64 = BX_READ_64BIT_REG(i->src());
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest)
@ -686,7 +662,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR3Rq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR4Rq(bxInstruction_c *i)
{
if (i->nnn() != 4) {
if (i->dst() != 4) {
BX_ERROR(("MOV_CR4Rq: #UD - register index out of range"));
exception(BX_UD_EXCEPTION, 0);
}
@ -698,7 +674,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR4Rq(bxInstruction_c *i)
invalidate_prefetch_q();
Bit64u val_64 = BX_READ_64BIT_REG(i->rm());
Bit64u val_64 = BX_READ_64BIT_REG(i->src());
#if BX_SUPPORT_VMX
if (BX_CPU_THIS_PTR in_vmx_guest)
val_64 = VMexit_CR4_Write(i, val_64);
@ -720,7 +696,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR0(bxInstruction_c *i)
Bit64u val_64;
if (i->nnn() == 0) {
if (i->src() == 0) {
// CR0
val_64 = read_CR0(); /* correctly handle VMX */
}
@ -729,14 +705,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR0(bxInstruction_c *i)
val_64 = ReadCR8(i);
}
BX_WRITE_64BIT_REG(i->rm(), val_64);
BX_WRITE_64BIT_REG(i->dst(), val_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR2(bxInstruction_c *i)
{
if (i->nnn() != 2) {
if (i->src() != 2) {
BX_ERROR(("MOV_RqCR2: #UD - register index out of range"));
exception(BX_UD_EXCEPTION, 0);
}
@ -752,14 +728,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR2(bxInstruction_c *i)
}
#endif
BX_WRITE_64BIT_REG(i->rm(), BX_CPU_THIS_PTR cr2);
BX_WRITE_64BIT_REG(i->dst(), BX_CPU_THIS_PTR cr2);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR3(bxInstruction_c *i)
{
if (i->nnn() != 3) {
if (i->src() != 3) {
BX_ERROR(("MOV_RqCR3: #UD - register index out of range"));
exception(BX_UD_EXCEPTION, 0);
}
@ -780,14 +756,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR3(bxInstruction_c *i)
VMexit_CR3_Read(i);
#endif
BX_WRITE_64BIT_REG(i->rm(), BX_CPU_THIS_PTR cr3);
BX_WRITE_64BIT_REG(i->dst(), BX_CPU_THIS_PTR cr3);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR4(bxInstruction_c *i)
{
if (i->nnn() != 4) {
if (i->src() != 4) {
BX_ERROR(("MOV_RqCR4: #UD - register index out of range"));
exception(BX_UD_EXCEPTION, 0);
}
@ -799,7 +775,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR4(bxInstruction_c *i)
Bit64u val_64 = read_CR4(); /* correctly handle VMX */
BX_WRITE_64BIT_REG(i->rm(), val_64);
BX_WRITE_64BIT_REG(i->dst(), val_64);
BX_NEXT_INSTR(i);
}
@ -822,7 +798,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LMSW_Ew(bxInstruction_c *i)
#endif
if (i->modC0()) {
msw = BX_READ_16BIT_REG(i->rm());
msw = BX_READ_16BIT_REG(i->src());
}
else {
/* use RMAddr(i) to save address for VMexit */
@ -856,10 +832,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SMSW_EwR(bxInstruction_c *i)
Bit32u msw = (Bit32u) read_CR0(); // handle CR0 shadow in VMX
if (i->os32L()) {
BX_WRITE_32BIT_REGZ(i->rm(), msw);
BX_WRITE_32BIT_REGZ(i->dst(), msw);
}
else {
BX_WRITE_16BIT_REG(i->rm(), msw & 0xffff);
BX_WRITE_16BIT_REG(i->dst(), msw & 0xffff);
}
BX_NEXT_INSTR(i);

6
bochs/cpu/ctrl_xfer16.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -214,7 +214,7 @@ done:
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EwR(bxInstruction_c *i)
{
Bit16u new_IP = BX_READ_16BIT_REG(i->rm());
Bit16u new_IP = BX_READ_16BIT_REG(i->dst());
#if BX_DEBUGGER
BX_CPU_THIS_PTR show_flag |= Flag_call;
@ -497,7 +497,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JNLE_Jw(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EwR(bxInstruction_c *i)
{
Bit16u new_IP = BX_READ_16BIT_REG(i->rm());
Bit16u new_IP = BX_READ_16BIT_REG(i->dst());
branch_near16(new_IP);
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP_INDIRECT, PREV_RIP, new_IP);

6
bochs/cpu/ctrl_xfer32.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -219,7 +219,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EdR(bxInstruction_c *i)
BX_CPU_THIS_PTR show_flag |= Flag_call;
#endif
Bit32u new_EIP = BX_READ_32BIT_REG(i->rm());
Bit32u new_EIP = BX_READ_32BIT_REG(i->dst());
RSP_SPECULATIVE;
@ -538,7 +538,7 @@ done:
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EdR(bxInstruction_c *i)
{
Bit32u new_EIP = BX_READ_32BIT_REG(i->rm());
Bit32u new_EIP = BX_READ_32BIT_REG(i->dst());
branch_near32(new_EIP);
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP_INDIRECT, PREV_RIP, new_EIP);

4
bochs/cpu/ctrl_xfer64.cc
View File

@ -134,7 +134,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EqR(bxInstruction_c *i)
BX_CPU_THIS_PTR show_flag |= Flag_call;
#endif
Bit64u new_RIP = BX_READ_64BIT_REG(i->rm());
Bit64u new_RIP = BX_READ_64BIT_REG(i->dst());
/* push 64 bit EA of next instruction */
stack_write_qword(RSP-8, RIP);
@ -388,7 +388,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JNLE_Jq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
if (! IsCanonical(op1_64)) {
BX_ERROR(("JMP_Eq: canonical RIP violation"));

103
bochs/cpu/data_xfer16.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -26,7 +26,7 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RXIw(bxInstruction_c *i)
{
BX_WRITE_16BIT_REG(i->rm(), i->Iw());
BX_WRITE_16BIT_REG(i->dst(), i->Iw());
BX_NEXT_INSTR(i);
}
@ -34,8 +34,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RXIw(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_RXAX(bxInstruction_c *i)
{
Bit16u temp16 = AX;
AX = BX_READ_16BIT_REG(i->rm());
BX_WRITE_16BIT_REG(i->rm(), temp16);
AX = BX_READ_16BIT_REG(i->dst());
BX_WRITE_16BIT_REG(i->dst(), temp16);
BX_NEXT_INSTR(i);
}
@ -44,14 +44,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EwGwM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_word(i->seg(), eaddr, BX_READ_16BIT_REG(i->nnn()));
write_virtual_word(i->seg(), eaddr, BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GwEwR(bxInstruction_c *i)
{
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -59,9 +59,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GwEwM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16u val16 = read_virtual_word(i->seg(), eaddr);
BX_WRITE_16BIT_REG(i->nnn(), val16);
BX_WRITE_16BIT_REG(i->dst(), val16);
BX_NEXT_INSTR(i);
}
@ -69,18 +68,18 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GwEwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EwSwR(bxInstruction_c *i)
{
/* Illegal to use nonexisting segments */
if (i->nnn() >= 6) {
BX_INFO(("MOV_EwSw: using of nonexisting segment register %d", i->nnn()));
if (i->src() >= 6) {
BX_INFO(("MOV_EwSw: using of nonexisting segment register %d", i->src()));
exception(BX_UD_EXCEPTION, 0);
}
Bit16u seg_reg = BX_CPU_THIS_PTR sregs[i->nnn()].selector.value;
Bit16u seg_reg = BX_CPU_THIS_PTR sregs[i->src()].selector.value;
if (i->os32L()) {
BX_WRITE_32BIT_REGZ(i->rm(), seg_reg);
BX_WRITE_32BIT_REGZ(i->dst(), seg_reg);
}
else {
BX_WRITE_16BIT_REG(i->rm(), seg_reg);
BX_WRITE_16BIT_REG(i->dst(), seg_reg);
}
BX_NEXT_INSTR(i);
@ -89,14 +88,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EwSwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EwSwM(bxInstruction_c *i)
{
/* Illegal to use nonexisting segments */
if (i->nnn() >= 6) {
BX_INFO(("MOV_EwSw: using of nonexisting segment register %d", i->nnn()));
if (i->src() >= 6) {
BX_INFO(("MOV_EwSw: using of nonexisting segment register %d", i->src()));
exception(BX_UD_EXCEPTION, 0);
}
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16u seg_reg = BX_CPU_THIS_PTR sregs[i->nnn()].selector.value;
Bit16u seg_reg = BX_CPU_THIS_PTR sregs[i->src()].selector.value;
write_virtual_word(i->seg(), eaddr, seg_reg);
BX_NEXT_INSTR(i);
@ -107,13 +106,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_SwEw(bxInstruction_c *i)
Bit16u op2_16;
/* Attempt to load CS or nonexisting segment register */
if (i->nnn() >= 6 || i->nnn() == BX_SEG_REG_CS) {
BX_INFO(("MOV_EwSw: can't use this segment register %d", i->nnn()));
if (i->dst() >= 6 || i->dst() == BX_SEG_REG_CS) {
BX_INFO(("MOV_EwSw: can't use this segment register %d", i->dst()));
exception(BX_UD_EXCEPTION, 0);
}
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -121,9 +120,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_SwEw(bxInstruction_c *i)
op2_16 = read_virtual_word(i->seg(), eaddr);
}
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->nnn()], op2_16);
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->dst()], op2_16);
if (i->nnn() == BX_SEG_REG_SS) {
if (i->dst() == BX_SEG_REG_SS) {
// MOV SS inhibits interrupts, debug exceptions and single-step
// trap exceptions until the execution boundary following the
// next instruction is reached.
@ -138,7 +137,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LEA_GwM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) eaddr);
BX_WRITE_16BIT_REG(i->dst(), (Bit16u) eaddr);
BX_NEXT_INSTR(i);
}
@ -173,17 +172,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVZX_GwEbM(bxInstruction_c *i)
Bit8u op2_8 = read_virtual_byte(i->seg(), eaddr);
/* zero extend byte op2 into word op1 */
BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) op2_8);
BX_WRITE_16BIT_REG(i->dst(), (Bit16u) op2_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVZX_GwEbR(bxInstruction_c *i)
{
Bit8u op2_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
/* zero extend byte op2 into word op1 */
BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) op2_8);
BX_WRITE_16BIT_REG(i->dst(), (Bit16u) op2_8);
BX_NEXT_INSTR(i);
}
@ -195,17 +194,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GwEbM(bxInstruction_c *i)
Bit8u op2_8 = read_virtual_byte(i->seg(), eaddr);
/* sign extend byte op2 into word op1 */
BX_WRITE_16BIT_REG(i->nnn(), (Bit8s) op2_8);
BX_WRITE_16BIT_REG(i->dst(), (Bit8s) op2_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GwEbR(bxInstruction_c *i)
{
Bit8u op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
Bit8u op2_8 = BX_READ_8BIT_REGx(i->src(),i->extend8bitL());
/* sign extend byte op2 into word op1 */
BX_WRITE_16BIT_REG(i->nnn(), (Bit8s) op2_8);
BX_WRITE_16BIT_REG(i->dst(), (Bit8s) op2_8);
BX_NEXT_INSTR(i);
}
@ -217,10 +216,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->src());
write_RMW_virtual_word(op2_16);
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->src(), op1_16);
BX_NEXT_INSTR(i);
}
@ -231,18 +230,18 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EwGwR(bxInstruction_c *i)
#if BX_DEBUGGER
// Note for mortals: the instruction to trigger this is "xchgw %bx,%bx"
if (bx_dbg.magic_break_enabled && (i->nnn() == 3) && (i->rm() == 3))
if (bx_dbg.magic_break_enabled && (i->src() == 3) && (i->dst() == 3))
{
BX_CPU_THIS_PTR magic_break = 1;
BX_NEXT_INSTR(i);
}
#endif
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->rm(), op2_16);
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = BX_READ_16BIT_REG(i->src());
BX_WRITE_16BIT_REG(i->src(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op2_16);
BX_NEXT_INSTR(i);
}
@ -254,7 +253,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EwGwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GwEwR(bxInstruction_c *i)
{
if (get_OF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -262,7 +261,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GwEwR(bxInstruction_c *i)
{
if (!get_OF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -270,7 +269,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GwEwR(bxInstruction_c *i)
{
if (get_CF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -278,7 +277,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GwEwR(bxInstruction_c *i)
{
if (!get_CF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -286,7 +285,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GwEwR(bxInstruction_c *i)
{
if (get_ZF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -294,7 +293,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GwEwR(bxInstruction_c *i)
{
if (!get_ZF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -302,7 +301,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GwEwR(bxInstruction_c *i)
{
if (get_CF() || get_ZF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -310,7 +309,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GwEwR(bxInstruction_c *i)
{
if (! (get_CF() || get_ZF()))
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -318,7 +317,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GwEwR(bxInstruction_c *i)
{
if (get_SF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -326,7 +325,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GwEwR(bxInstruction_c *i)
{
if (!get_SF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -334,7 +333,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GwEwR(bxInstruction_c *i)
{
if (get_PF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -342,7 +341,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GwEwR(bxInstruction_c *i)
{
if (!get_PF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -350,7 +349,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GwEwR(bxInstruction_c *i)
{
if (getB_SF() != getB_OF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -358,7 +357,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GwEwR(bxInstruction_c *i)
{
if (getB_SF() == getB_OF())
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -366,7 +365,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GwEwR(bxInstruction_c *i)
{
if (get_ZF() || (getB_SF() != getB_OF()))
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -374,7 +373,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GwEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNLE_GwEwR(bxInstruction_c *i)
{
if (! get_ZF() && (getB_SF() == getB_OF()))
BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
BX_WRITE_16BIT_REG(i->dst(), BX_READ_16BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}

121
bochs/cpu/data_xfer32.cc
View File

@ -27,21 +27,21 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_ERXEAX(bxInstruction_c *i)
{
#if BX_SUPPORT_X86_64
if (i->rm() == 0) { // 'xchg eax, eax' is NOP even in 64-bit mode
if (i->dst() == 0) { // 'xchg eax, eax' is NOP even in 64-bit mode
BX_NEXT_INSTR(i);
}
#endif
Bit32u temp32 = EAX;
RAX = BX_READ_32BIT_REG(i->rm());
BX_WRITE_32BIT_REGZ(i->rm(), temp32);
RAX = BX_READ_32BIT_REG(i->dst());
BX_WRITE_32BIT_REGZ(i->dst(), temp32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_ERXId(bxInstruction_c *i)
{
BX_WRITE_32BIT_REGZ(i->rm(), i->Id());
BX_WRITE_32BIT_REGZ(i->dst(), i->Id());
BX_NEXT_INSTR(i);
}
@ -50,7 +50,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV32_EdGdM(bxInstruction_c *i)
{
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dword_32(i->seg(), eaddr, BX_READ_32BIT_REG(i->nnn()));
write_virtual_dword_32(i->seg(), eaddr, BX_READ_32BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -59,14 +59,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV32S_EdGdM(bxInstruction_c *i)
{
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
stack_write_dword(eaddr, BX_READ_32BIT_REG(i->nnn()));
stack_write_dword(eaddr, BX_READ_32BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GdEdR(bxInstruction_c *i)
{
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -76,7 +76,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV32_GdEdM(bxInstruction_c *i)
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u val32 = read_virtual_dword_32(i->seg(), eaddr);
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
BX_WRITE_32BIT_REGZ(i->dst(), val32);
BX_NEXT_INSTR(i);
}
@ -86,7 +86,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV32S_GdEdM(bxInstruction_c *i)
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u val32 = stack_read_dword(eaddr);
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
BX_WRITE_32BIT_REGZ(i->dst(), val32);
BX_NEXT_INSTR(i);
}
@ -95,7 +95,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LEA_GdM(bxInstruction_c *i)
{
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
BX_WRITE_32BIT_REGZ(i->nnn(), eaddr);
BX_WRITE_32BIT_REGZ(i->dst(), eaddr);
BX_NEXT_INSTR(i);
}
@ -130,17 +130,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVZX_GdEbM(bxInstruction_c *i)
Bit8u op2_8 = read_virtual_byte(i->seg(), eaddr);
/* zero extend byte op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit32u) op2_8);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) op2_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVZX_GdEbR(bxInstruction_c *i)
{
Bit8u op2_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
/* zero extend byte op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit32u) op2_8);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) op2_8);
BX_NEXT_INSTR(i);
}
@ -152,17 +152,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVZX_GdEwM(bxInstruction_c *i)
Bit16u op2_16 = read_virtual_word(i->seg(), eaddr);
/* zero extend word op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit32u) op2_16);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) op2_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVZX_GdEwR(bxInstruction_c *i)
{
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
/* zero extend word op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit32u) op2_16);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) op2_16);
BX_NEXT_INSTR(i);
}
@ -174,17 +174,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GdEbM(bxInstruction_c *i)
Bit8u op2_8 = read_virtual_byte(i->seg(), eaddr);
/* sign extend byte op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit8s) op2_8);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit8s) op2_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GdEbR(bxInstruction_c *i)
{
Bit8u op2_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
/* sign extend byte op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit8s) op2_8);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit8s) op2_8);
BX_NEXT_INSTR(i);
}
@ -196,17 +196,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GdEwM(bxInstruction_c *i)
Bit16u op2_16 = read_virtual_word(i->seg(), eaddr);
/* sign extend word op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit16s) op2_16);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit16s) op2_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GdEwR(bxInstruction_c *i)
{
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
/* sign extend word op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit16s) op2_16);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit16s) op2_16);
BX_NEXT_INSTR(i);
}
@ -216,21 +216,20 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
Bit32u op2_32 = BX_READ_32BIT_REG(i->nnn());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
write_RMW_virtual_dword(op2_32);
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->src(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->nnn());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
BX_WRITE_32BIT_REGZ(i->src(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op2_32);
BX_NEXT_INSTR(i);
}
@ -242,9 +241,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EdGdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GdEdR(bxInstruction_c *i)
{
if (get_OF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -252,9 +251,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GdEdR(bxInstruction_c *i)
{
if (!get_OF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -262,9 +261,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GdEdR(bxInstruction_c *i)
{
if (get_CF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -272,9 +271,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GdEdR(bxInstruction_c *i)
{
if (!get_CF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -282,9 +281,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GdEdR(bxInstruction_c *i)
{
if (get_ZF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -292,9 +291,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GdEdR(bxInstruction_c *i)
{
if (!get_ZF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -302,9 +301,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GdEdR(bxInstruction_c *i)
{
if (get_CF() || get_ZF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -312,9 +311,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GdEdR(bxInstruction_c *i)
{
if (! (get_CF() || get_ZF()))
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -322,9 +321,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GdEdR(bxInstruction_c *i)
{
if (get_SF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -332,9 +331,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GdEdR(bxInstruction_c *i)
{
if (!get_SF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -342,9 +341,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GdEdR(bxInstruction_c *i)
{
if (get_PF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -352,9 +351,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GdEdR(bxInstruction_c *i)
{
if (!get_PF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -362,9 +361,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GdEdR(bxInstruction_c *i)
{
if (getB_SF() != getB_OF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -372,9 +371,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GdEdR(bxInstruction_c *i)
{
if (getB_SF() == getB_OF())
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -382,9 +381,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GdEdR(bxInstruction_c *i)
{
if (get_ZF() || (getB_SF() != getB_OF()))
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
@ -392,9 +391,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GdEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNLE_GdEdR(bxInstruction_c *i)
{
if (! get_ZF() && (getB_SF() == getB_OF()))
BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_32BIT_REG(i->src()));
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}

98
bochs/cpu/data_xfer64.cc
View File

@ -29,15 +29,15 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_RRXRAX(bxInstruction_c *i)
{
Bit64u temp64 = RAX;
RAX = BX_READ_64BIT_REG(i->rm());
BX_WRITE_64BIT_REG(i->rm(), temp64);
RAX = BX_READ_64BIT_REG(i->dst());
BX_WRITE_64BIT_REG(i->dst(), temp64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RRXIq(bxInstruction_c *i)
{
BX_WRITE_64BIT_REG(i->rm(), i->Iq());
BX_WRITE_64BIT_REG(i->dst(), i->Iq());
BX_NEXT_INSTR(i);
}
@ -47,7 +47,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV64_GdEdM(bxInstruction_c *i)
Bit64u eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u val32 = read_virtual_dword_64(i->seg(), eaddr);
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
BX_WRITE_32BIT_REGZ(i->dst(), val32);
BX_NEXT_INSTR(i);
}
@ -56,7 +56,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV64_EdGdM(bxInstruction_c *i)
{
Bit64u eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dword_64(i->seg(), eaddr, BX_READ_32BIT_REG(i->nnn()));
write_virtual_dword_64(i->seg(), eaddr, BX_READ_32BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -65,7 +65,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EqGqM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_qword_64(i->seg(), eaddr, BX_READ_64BIT_REG(i->nnn()));
write_virtual_qword_64(i->seg(), eaddr, BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -74,7 +74,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV64S_EqGqM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
stack_write_qword(eaddr, BX_READ_64BIT_REG(i->nnn()));
stack_write_qword(eaddr, BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -84,7 +84,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GqEqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit64u val64 = read_virtual_qword_64(i->seg(), eaddr);
BX_WRITE_64BIT_REG(i->nnn(), val64);
BX_WRITE_64BIT_REG(i->dst(), val64);
BX_NEXT_INSTR(i);
}
@ -93,14 +93,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV64S_GqEqM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
BX_WRITE_64BIT_REG(i->nnn(), stack_read_qword(eaddr));
BX_WRITE_64BIT_REG(i->dst(), stack_read_qword(eaddr));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GqEqR(bxInstruction_c *i)
{
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -109,7 +109,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LEA_GqM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
BX_WRITE_64BIT_REG(i->nnn(), eaddr);
BX_WRITE_64BIT_REG(i->dst(), eaddr);
BX_NEXT_INSTR(i);
}
@ -184,7 +184,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EqIdM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EqIdR(bxInstruction_c *i)
{
Bit64u op_64 = (Bit32s) i->Id();
BX_WRITE_64BIT_REG(i->rm(), op_64);
BX_WRITE_64BIT_REG(i->dst(), op_64);
BX_NEXT_INSTR(i);
}
@ -196,17 +196,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVZX_GqEbM(bxInstruction_c *i)
Bit8u op2_8 = read_virtual_byte_64(i->seg(), eaddr);
/* zero extend byte op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_8);
BX_WRITE_64BIT_REG(i->dst(), (Bit64u) op2_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVZX_GqEbR(bxInstruction_c *i)
{
Bit8u op2_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
/* zero extend byte op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_8);
BX_WRITE_64BIT_REG(i->dst(), (Bit64u) op2_8);
BX_NEXT_INSTR(i);
}
@ -218,17 +218,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVZX_GqEwM(bxInstruction_c *i)
Bit16u op2_16 = read_virtual_word_64(i->seg(), eaddr);
/* zero extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_16);
BX_WRITE_64BIT_REG(i->dst(), (Bit64u) op2_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVZX_GqEwR(bxInstruction_c *i)
{
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
/* zero extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_16);
BX_WRITE_64BIT_REG(i->dst(), (Bit64u) op2_16);
BX_NEXT_INSTR(i);
}
@ -240,17 +240,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GqEbM(bxInstruction_c *i)
Bit8u op2_8 = read_virtual_byte_64(i->seg(), eaddr);
/* sign extend byte op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit8s) op2_8);
BX_WRITE_64BIT_REG(i->dst(), (Bit8s) op2_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GqEbR(bxInstruction_c *i)
{
Bit8u op2_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op2_8 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
/* sign extend byte op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit8s) op2_8);
BX_WRITE_64BIT_REG(i->dst(), (Bit8s) op2_8);
BX_NEXT_INSTR(i);
}
@ -262,17 +262,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GqEwM(bxInstruction_c *i)
Bit16u op2_16 = read_virtual_word_64(i->seg(), eaddr);
/* sign extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit16s) op2_16);
BX_WRITE_64BIT_REG(i->dst(), (Bit16s) op2_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GqEwR(bxInstruction_c *i)
{
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
/* sign extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit16s) op2_16);
BX_WRITE_64BIT_REG(i->dst(), (Bit16s) op2_16);
BX_NEXT_INSTR(i);
}
@ -284,17 +284,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GqEdM(bxInstruction_c *i)
Bit32u op2_32 = read_virtual_dword_64(i->seg(), eaddr);
/* sign extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit32s) op2_32);
BX_WRITE_64BIT_REG(i->dst(), (Bit32s) op2_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GqEdR(bxInstruction_c *i)
{
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
/* sign extend word op2 into qword op1 */
BX_WRITE_64BIT_REG(i->nnn(), (Bit32s) op2_32);
BX_WRITE_64BIT_REG(i->dst(), (Bit32s) op2_32);
BX_NEXT_INSTR(i);
}
@ -304,21 +304,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EqGqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit64u op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
Bit64u op2_64 = BX_READ_64BIT_REG(i->nnn());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
write_RMW_virtual_qword(op2_64);
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->src(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op2_64 = BX_READ_64BIT_REG(i->nnn());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->rm(), op2_64);
BX_WRITE_64BIT_REG(i->src(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op2_64);
BX_NEXT_INSTR(i);
}
@ -330,7 +330,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EqGqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GqEqR(bxInstruction_c *i)
{
if (get_OF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -338,7 +338,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GqEqR(bxInstruction_c *i)
{
if (!get_OF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -346,7 +346,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GqEqR(bxInstruction_c *i)
{
if (get_CF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -354,7 +354,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GqEqR(bxInstruction_c *i)
{
if (!get_CF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -362,7 +362,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GqEqR(bxInstruction_c *i)
{
if (get_ZF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -370,7 +370,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GqEqR(bxInstruction_c *i)
{
if (!get_ZF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -378,7 +378,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GqEqR(bxInstruction_c *i)
{
if (get_CF() || get_ZF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -386,7 +386,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GqEqR(bxInstruction_c *i)
{
if (! (get_CF() || get_ZF()))
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -394,7 +394,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GqEqR(bxInstruction_c *i)
{
if (get_SF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -402,7 +402,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GqEqR(bxInstruction_c *i)
{
if (!get_SF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -410,7 +410,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GqEqR(bxInstruction_c *i)
{
if (get_PF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -418,7 +418,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GqEqR(bxInstruction_c *i)
{
if (!get_PF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -426,7 +426,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GqEqR(bxInstruction_c *i)
{
if (getB_SF() != getB_OF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -434,7 +434,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GqEqR(bxInstruction_c *i)
{
if (getB_SF() == getB_OF())
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -442,7 +442,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GqEqR(bxInstruction_c *i)
{
if (get_ZF() || (getB_SF() != getB_OF()))
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}
@ -450,7 +450,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNLE_GqEqR(bxInstruction_c *i)
{
if (! get_ZF() && (getB_SF() == getB_OF()))
BX_WRITE_64BIT_REG(i->nnn(), BX_READ_64BIT_REG(i->rm()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_64BIT_REG(i->src()));
BX_NEXT_INSTR(i);
}

26
bochs/cpu/data_xfer8.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -26,14 +26,14 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RLIb(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), i->Ib());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), i->Ib());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RHIb(bxInstruction_c *i)
{
BX_WRITE_8BIT_REGH(i->rm() & 0x03, i->Ib());
BX_WRITE_8BIT_REGH(i->dst() & 0x3, i->Ib());
BX_NEXT_INSTR(i);
}
@ -42,7 +42,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EbGbM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_byte(i->seg(), eaddr, BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL()));
write_virtual_byte(i->seg(), eaddr, BX_READ_8BIT_REGx(i->src(), i->extend8bitL()));
BX_NEXT_INSTR(i);
}
@ -52,15 +52,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GbEbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit8u val8 = read_virtual_byte(i->seg(), eaddr);
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), val8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), val8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GbEbR(bxInstruction_c *i)
{
Bit8u op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op2);
Bit8u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op2);
BX_NEXT_INSTR(i);
}
@ -111,21 +111,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit8u op1 = read_RMW_virtual_byte(i->seg(), eaddr);
Bit8u op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit8u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
write_RMW_virtual_byte(op2);
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->src(), i->extend8bitL(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EbGbR(bxInstruction_c *i)
{
Bit8u op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
Bit8u op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit8u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2);
BX_WRITE_8BIT_REGx(i->src(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op2);
BX_NEXT_INSTR(i);
}

272
bochs/cpu/fetchdecode.cc
View File

@ -165,7 +165,7 @@ static unsigned sreg_mod1or2_base32[8] = {
// table of all Bochs opcodes
bxIAOpcodeTable BxOpcodesTable[] = {
#define bx_define_opcode(a, b, c, d, e) { b, c, e },
#define bx_define_opcode(a, b, c, d, s1, s2, s3, s4, e) { b, c, { s1, s2, s3, (s4) | (e) } },
#include "ia_opcodes.h"
};
#undef bx_define_opcode
@ -177,64 +177,64 @@ bxIAOpcodeTable BxOpcodesTable[] = {
static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
// 512 entries for 16bit mode
/* 00 /w */ { BxLockable | BxArithDstRM, BX_IA_ADD_EbGb },
/* 01 /w */ { BxLockable | BxArithDstRM, BX_IA_ADD_EwGw },
/* 00 /w */ { BxLockable, BX_IA_ADD_EbGb },
/* 01 /w */ { BxLockable, BX_IA_ADD_EwGw },
/* 02 /w */ { 0, BX_IA_ADD_GbEb },
/* 03 /w */ { 0, BX_IA_ADD_GwEw },
/* 04 /w */ { BxImmediate_Ib, BX_IA_ADD_ALIb },
/* 05 /w */ { BxImmediate_Iw, BX_IA_ADD_AXIw },
/* 06 /w */ { 0, BX_IA_PUSH16_ES },
/* 07 /w */ { 0, BX_IA_POP16_ES },
/* 08 /w */ { BxLockable | BxArithDstRM, BX_IA_OR_EbGb },
/* 09 /w */ { BxLockable | BxArithDstRM, BX_IA_OR_EwGw },
/* 08 /w */ { BxLockable, BX_IA_OR_EbGb },
/* 09 /w */ { BxLockable, BX_IA_OR_EwGw },
/* 0A /w */ { 0, BX_IA_OR_GbEb },
/* 0B /w */ { 0, BX_IA_OR_GwEw },
/* 0C /w */ { BxImmediate_Ib, BX_IA_OR_ALIb },
/* 0D /w */ { BxImmediate_Iw, BX_IA_OR_AXIw },
/* 0E /w */ { 0, BX_IA_PUSH16_CS },
/* 0F /w */ { 0, BX_IA_ERROR }, // 2-byte escape
/* 10 /w */ { BxLockable | BxArithDstRM, BX_IA_ADC_EbGb },
/* 11 /w */ { BxLockable | BxArithDstRM, BX_IA_ADC_EwGw },
/* 10 /w */ { BxLockable, BX_IA_ADC_EbGb },
/* 11 /w */ { BxLockable, BX_IA_ADC_EwGw },
/* 12 /w */ { 0, BX_IA_ADC_GbEb },
/* 13 /w */ { 0, BX_IA_ADC_GwEw },
/* 14 /w */ { BxImmediate_Ib, BX_IA_ADC_ALIb },
/* 15 /w */ { BxImmediate_Iw, BX_IA_ADC_AXIw },
/* 16 /w */ { 0, BX_IA_PUSH16_SS },
/* 17 /w */ { 0, BX_IA_POP16_SS },
/* 18 /w */ { BxLockable | BxArithDstRM, BX_IA_SBB_EbGb },
/* 19 /w */ { BxLockable | BxArithDstRM, BX_IA_SBB_EwGw },
/* 18 /w */ { BxLockable, BX_IA_SBB_EbGb },
/* 19 /w */ { BxLockable, BX_IA_SBB_EwGw },
/* 1A /w */ { 0, BX_IA_SBB_GbEb },
/* 1B /w */ { 0, BX_IA_SBB_GwEw },
/* 1C /w */ { BxImmediate_Ib, BX_IA_SBB_ALIb },
/* 1D /w */ { BxImmediate_Iw, BX_IA_SBB_AXIw },
/* 1E /w */ { 0, BX_IA_PUSH16_DS },
/* 1F /w */ { 0, BX_IA_POP16_DS },
/* 20 /w */ { BxLockable | BxArithDstRM, BX_IA_AND_EbGb },
/* 21 /w */ { BxLockable | BxArithDstRM, BX_IA_AND_EwGw },
/* 20 /w */ { BxLockable, BX_IA_AND_EbGb },
/* 21 /w */ { BxLockable, BX_IA_AND_EwGw },
/* 22 /w */ { 0, BX_IA_AND_GbEb },
/* 23 /w */ { 0, BX_IA_AND_GwEw },
/* 24 /w */ { BxImmediate_Ib, BX_IA_AND_ALIb },
/* 25 /w */ { BxImmediate_Iw, BX_IA_AND_AXIw },
/* 26 /w */ { 0, BX_IA_ERROR }, // ES:
/* 27 /w */ { 0, BX_IA_DAA },
/* 28 /w */ { BxLockable | BxArithDstRM, BX_IA_SUB_EbGb },
/* 29 /w */ { BxLockable | BxArithDstRM, BX_IA_SUB_EwGw },
/* 28 /w */ { BxLockable, BX_IA_SUB_EbGb },
/* 29 /w */ { BxLockable, BX_IA_SUB_EwGw },
/* 2A /w */ { 0, BX_IA_SUB_GbEb },
/* 2B /w */ { 0, BX_IA_SUB_GwEw },
/* 2C /w */ { BxImmediate_Ib, BX_IA_SUB_ALIb },
/* 2D /w */ { BxImmediate_Iw, BX_IA_SUB_AXIw },
/* 2E /w */ { 0, BX_IA_ERROR }, // CS:
/* 2F /w */ { 0, BX_IA_DAS },
/* 30 /w */ { BxLockable | BxArithDstRM, BX_IA_XOR_EbGb },
/* 31 /w */ { BxLockable | BxArithDstRM, BX_IA_XOR_EwGw },
/* 30 /w */ { BxLockable, BX_IA_XOR_EbGb },
/* 31 /w */ { BxLockable, BX_IA_XOR_EwGw },
/* 32 /w */ { 0, BX_IA_XOR_GbEb },
/* 33 /w */ { 0, BX_IA_XOR_GwEw },
/* 34 /w */ { BxImmediate_Ib, BX_IA_XOR_ALIb },
/* 35 /w */ { BxImmediate_Iw, BX_IA_XOR_AXIw },
/* 36 /w */ { 0, BX_IA_ERROR }, // SS:
/* 37 /w */ { 0, BX_IA_AAA },
/* 38 /w */ { BxArithDstRM, BX_IA_CMP_EbGb },
/* 39 /w */ { BxArithDstRM, BX_IA_CMP_EwGw },
/* 38 /w */ { 0, BX_IA_CMP_EbGb },
/* 39 /w */ { 0, BX_IA_CMP_EwGw },
/* 3A /w */ { 0, BX_IA_CMP_GbEb },
/* 3B /w */ { 0, BX_IA_CMP_GwEw },
/* 3C /w */ { BxImmediate_Ib, BX_IA_CMP_ALIb },
@ -285,10 +285,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 69 /w */ { BxImmediate_Iw, BX_IA_IMUL_GwEwIw },
/* 6A /w */ { BxImmediate_Ib_SE, BX_IA_PUSH_Iw },
/* 6B /w */ { BxImmediate_Ib_SE, BX_IA_IMUL_GwEwIw },
/* 6C /w */ { 0, BX_IA_REP_INSB_YbDX },
/* 6D /w */ { 0, BX_IA_REP_INSW_YwDX },
/* 6E /w */ { 0, BX_IA_REP_OUTSB_DXXb },
/* 6F /w */ { 0, BX_IA_REP_OUTSW_DXXw },
/* 6C /w */ { BxRepeatable, BX_IA_REP_INSB_YbDX },
/* 6D /w */ { BxRepeatable, BX_IA_REP_INSW_YwDX },
/* 6E /w */ { BxRepeatable, BX_IA_REP_OUTSB_DXXb },
/* 6F /w */ { BxRepeatable, BX_IA_REP_OUTSW_DXXw },
/* 70 /w */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JO_Jw },
/* 71 /w */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JNO_Jw },
/* 72 /w */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JB_Jw },
@ -313,8 +313,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 85 /w */ { 0, BX_IA_TEST_EwGw },
/* 86 /w */ { BxLockable, BX_IA_XCHG_EbGb },
/* 87 /w */ { BxLockable, BX_IA_XCHG_EwGw },
/* 88 /w */ { BxArithDstRM, BX_IA_MOV_EbGb },
/* 89 /w */ { BxArithDstRM, BX_IA_MOV_EwGw },
/* 88 /w */ { 0, BX_IA_MOV_EbGb },
/* 89 /w */ { 0, BX_IA_MOV_EwGw },
/* 8A /w */ { 0, BX_IA_MOV_GbEb },
/* 8B /w */ { 0, BX_IA_MOV_GwEw },
/* 8C /w */ { 0, BX_IA_MOV_EwSw },
@ -341,18 +341,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* A1 /w */ { BxImmediate_O, BX_IA_MOV_AXOd },
/* A2 /w */ { BxImmediate_O, BX_IA_MOV_OdAL },
/* A3 /w */ { BxImmediate_O, BX_IA_MOV_OdAX },
/* A4 /w */ { 0, BX_IA_REP_MOVSB_XbYb },
/* A5 /w */ { 0, BX_IA_REP_MOVSW_XwYw },
/* A6 /w */ { 0, BX_IA_REP_CMPSB_XbYb },
/* A7 /w */ { 0, BX_IA_REP_CMPSW_XwYw },
/* A4 /w */ { BxRepeatable, BX_IA_REP_MOVSB_XbYb },
/* A5 /w */ { BxRepeatable, BX_IA_REP_MOVSW_XwYw },
/* A6 /w */ { BxRepeatable, BX_IA_REP_CMPSB_XbYb },
/* A7 /w */ { BxRepeatable, BX_IA_REP_CMPSW_XwYw },
/* A8 /w */ { BxImmediate_Ib, BX_IA_TEST_ALIb },
/* A9 /w */ { BxImmediate_Iw, BX_IA_TEST_AXIw },
/* AA /w */ { 0, BX_IA_REP_STOSB_YbAL },
/* AB /w */ { 0, BX_IA_REP_STOSW_YwAX },
/* AC /w */ { 0, BX_IA_REP_LODSB_ALXb },
/* AD /w */ { 0, BX_IA_REP_LODSW_AXXw },
/* AE /w */ { 0, BX_IA_REP_SCASB_ALXb },
/* AF /w */ { 0, BX_IA_REP_SCASW_AXXw },
/* AA /w */ { BxRepeatable, BX_IA_REP_STOSB_YbAL },
/* AB /w */ { BxRepeatable, BX_IA_REP_STOSW_YwAX },
/* AC /w */ { BxRepeatable, BX_IA_REP_LODSB_ALXb },
/* AD /w */ { BxRepeatable, BX_IA_REP_LODSW_AXXw },
/* AE /w */ { BxRepeatable, BX_IA_REP_SCASB_ALXb },
/* AF /w */ { BxRepeatable, BX_IA_REP_SCASW_AXXw },
/* B0 /w */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
/* B1 /w */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
/* B2 /w */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
@ -461,8 +461,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 0D /w */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCHW on AMD, NOP on Intel
/* 0F 0E /w */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
/* 0F 0F /w */ { BxImmediate_Ib, BX_IA_ERROR }, // 3DNow! Opcode Table
/* 0F 10 /w */ { BxPrefixSSE, BX_IA_MOVUPS_VpsWps, BxOpcodeGroupSSE_0f10 },
/* 0F 11 /w */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVUPS_WpsVps, BxOpcodeGroupSSE_0f11 },
/* 0F 10 /w */ { BxPrefixSSE, BX_IA_MOVUPS_VpsWps, BxOpcodeGroupSSE_0f10 },
/* 0F 11 /w */ { BxPrefixSSE, BX_IA_MOVUPS_WpsVps, BxOpcodeGroupSSE_0f11 },
/* 0F 12 /w */ { BxPrefixSSE, BX_IA_MOVLPS_VpsMq, BxOpcodeGroupSSE_0f12 },
/* 0F 13 /w */ { BxPrefixSSE, BX_IA_MOVLPS_MqVps, BxOpcodeGroupSSE_0f13M },
/* 0F 14 /w */ { BxPrefixSSE, BX_IA_UNPCKLPS_VpsWdq, BxOpcodeGroupSSE_0f14 },
@ -496,8 +496,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 25 /w */ { 0, BX_IA_ERROR },
/* 0F 26 /w */ { 0, BX_IA_ERROR }, // BX_IA_MOV_TdRd not implemented
/* 0F 27 /w */ { 0, BX_IA_ERROR },
/* 0F 28 /w */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /w */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
/* 0F 28 /w */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /w */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
/* 0F 2A /w */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
/* 0F 2B /w */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
/* 0F 2C /w */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
@ -591,7 +591,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 7C /w */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
/* 0F 7D /w */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
/* 0F 7E /w */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
/* 0F 7F /w */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
/* 0F 7F /w */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
/* 0F 80 /w */ { BxImmediate_BrOff16 | BxTraceJCC, BX_IA_JO_Jw },
/* 0F 81 /w */ { BxImmediate_BrOff16 | BxTraceJCC, BX_IA_JNO_Jw },
/* 0F 82 /w */ { BxImmediate_BrOff16 | BxTraceJCC, BX_IA_JB_Jw },
@ -722,64 +722,64 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F FF /w */ { 0, BX_IA_ERROR },
// 512 entries for 32bit mode
/* 00 /d */ { BxLockable | BxArithDstRM, BX_IA_ADD_EbGb },
/* 01 /d */ { BxLockable | BxArithDstRM, BX_IA_ADD_EdGd },
/* 00 /d */ { BxLockable, BX_IA_ADD_EbGb },
/* 01 /d */ { BxLockable, BX_IA_ADD_EdGd },
/* 02 /d */ { 0, BX_IA_ADD_GbEb },
/* 03 /d */ { 0, BX_IA_ADD_GdEd },
/* 04 /d */ { BxImmediate_Ib, BX_IA_ADD_ALIb },
/* 05 /d */ { BxImmediate_Id, BX_IA_ADD_EAXId },
/* 06 /d */ { 0, BX_IA_PUSH32_ES },
/* 07 /d */ { 0, BX_IA_POP32_ES },
/* 08 /d */ { BxLockable | BxArithDstRM, BX_IA_OR_EbGb },
/* 09 /d */ { BxLockable | BxArithDstRM, BX_IA_OR_EdGd },
/* 08 /d */ { BxLockable, BX_IA_OR_EbGb },
/* 09 /d */ { BxLockable, BX_IA_OR_EdGd },
/* 0A /d */ { 0, BX_IA_OR_GbEb },
/* 0B /d */ { 0, BX_IA_OR_GdEd },
/* 0C /d */ { BxImmediate_Ib, BX_IA_OR_ALIb },
/* 0D /d */ { BxImmediate_Id, BX_IA_OR_EAXId },
/* 0E /d */ { 0, BX_IA_PUSH32_CS },
/* 0F /d */ { 0, BX_IA_ERROR }, // 2-byte escape
/* 10 /d */ { BxLockable | BxArithDstRM, BX_IA_ADC_EbGb },
/* 11 /d */ { BxLockable | BxArithDstRM, BX_IA_ADC_EdGd },
/* 10 /d */ { BxLockable, BX_IA_ADC_EbGb },
/* 11 /d */ { BxLockable, BX_IA_ADC_EdGd },
/* 12 /d */ { 0, BX_IA_ADC_GbEb },
/* 13 /d */ { 0, BX_IA_ADC_GdEd },
/* 14 /d */ { BxImmediate_Ib, BX_IA_ADC_ALIb },
/* 15 /d */ { BxImmediate_Id, BX_IA_ADC_EAXId },
/* 16 /d */ { 0, BX_IA_PUSH32_SS },
/* 17 /d */ { 0, BX_IA_POP32_SS },
/* 18 /d */ { BxLockable | BxArithDstRM, BX_IA_SBB_EbGb },
/* 19 /d */ { BxLockable | BxArithDstRM, BX_IA_SBB_EdGd },
/* 18 /d */ { BxLockable, BX_IA_SBB_EbGb },
/* 19 /d */ { BxLockable, BX_IA_SBB_EdGd },
/* 1A /d */ { 0, BX_IA_SBB_GbEb },
/* 1B /d */ { 0, BX_IA_SBB_GdEd },
/* 1C /d */ { BxImmediate_Ib, BX_IA_SBB_ALIb },
/* 1D /d */ { BxImmediate_Id, BX_IA_SBB_EAXId },
/* 1E /d */ { 0, BX_IA_PUSH32_DS },
/* 1F /d */ { 0, BX_IA_POP32_DS },
/* 20 /d */ { BxLockable | BxArithDstRM, BX_IA_AND_EbGb },
/* 21 /d */ { BxLockable | BxArithDstRM, BX_IA_AND_EdGd },
/* 20 /d */ { BxLockable, BX_IA_AND_EbGb },
/* 21 /d */ { BxLockable, BX_IA_AND_EdGd },
/* 22 /d */ { 0, BX_IA_AND_GbEb },
/* 23 /d */ { 0, BX_IA_AND_GdEd },
/* 24 /d */ { BxImmediate_Ib, BX_IA_AND_ALIb },
/* 25 /d */ { BxImmediate_Id, BX_IA_AND_EAXId },
/* 26 /d */ { 0, BX_IA_ERROR }, // ES:
/* 27 /d */ { 0, BX_IA_DAA },
/* 28 /d */ { BxLockable | BxArithDstRM, BX_IA_SUB_EbGb },
/* 29 /d */ { BxLockable | BxArithDstRM, BX_IA_SUB_EdGd },
/* 28 /d */ { BxLockable, BX_IA_SUB_EbGb },
/* 29 /d */ { BxLockable, BX_IA_SUB_EdGd },
/* 2A /d */ { 0, BX_IA_SUB_GbEb },
/* 2B /d */ { 0, BX_IA_SUB_GdEd },
/* 2C /d */ { BxImmediate_Ib, BX_IA_SUB_ALIb },
/* 2D /d */ { BxImmediate_Id, BX_IA_SUB_EAXId },
/* 2E /d */ { 0, BX_IA_ERROR }, // CS:
/* 2F /d */ { 0, BX_IA_DAS },
/* 30 /d */ { BxLockable | BxArithDstRM, BX_IA_XOR_EbGb },
/* 31 /d */ { BxLockable | BxArithDstRM, BX_IA_XOR_EdGd },
/* 30 /d */ { BxLockable, BX_IA_XOR_EbGb },
/* 31 /d */ { BxLockable, BX_IA_XOR_EdGd },
/* 32 /d */ { 0, BX_IA_XOR_GbEb },
/* 33 /d */ { 0, BX_IA_XOR_GdEd },
/* 34 /d */ { BxImmediate_Ib, BX_IA_XOR_ALIb },
/* 35 /d */ { BxImmediate_Id, BX_IA_XOR_EAXId },
/* 36 /d */ { 0, BX_IA_ERROR }, // SS:
/* 37 /d */ { 0, BX_IA_AAA },
/* 38 /d */ { BxArithDstRM, BX_IA_CMP_EbGb },
/* 39 /d */ { BxArithDstRM, BX_IA_CMP_EdGd },
/* 38 /d */ { 0, BX_IA_CMP_EbGb },
/* 39 /d */ { 0, BX_IA_CMP_EdGd },
/* 3A /d */ { 0, BX_IA_CMP_GbEb },
/* 3B /d */ { 0, BX_IA_CMP_GdEd },
/* 3C /d */ { BxImmediate_Ib, BX_IA_CMP_ALIb },
@ -830,10 +830,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 69 /d */ { BxImmediate_Id, BX_IA_IMUL_GdEdId },
/* 6A /d */ { BxImmediate_Ib_SE, BX_IA_PUSH_Id },
/* 6B /d */ { BxImmediate_Ib_SE, BX_IA_IMUL_GdEdId },
/* 6C /d */ { 0, BX_IA_REP_INSB_YbDX },
/* 6D /d */ { 0, BX_IA_REP_INSD_YdDX },
/* 6E /d */ { 0, BX_IA_REP_OUTSB_DXXb },
/* 6F /d */ { 0, BX_IA_REP_OUTSD_DXXd },
/* 6C /d */ { BxRepeatable, BX_IA_REP_INSB_YbDX },
/* 6D /d */ { BxRepeatable, BX_IA_REP_INSD_YdDX },
/* 6E /d */ { BxRepeatable, BX_IA_REP_OUTSB_DXXb },
/* 6F /d */ { BxRepeatable, BX_IA_REP_OUTSD_DXXd },
/* 70 /d */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JO_Jd },
/* 71 /d */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JNO_Jd },
/* 72 /d */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JB_Jd },
@ -858,8 +858,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 85 /d */ { 0, BX_IA_TEST_EdGd },
/* 86 /d */ { BxLockable, BX_IA_XCHG_EbGb },
/* 87 /d */ { BxLockable, BX_IA_XCHG_EdGd },
/* 88 /d */ { BxArithDstRM, BX_IA_MOV_EbGb },
/* 89 /d */ { BxArithDstRM, BX_IA_MOV32_EdGd },
/* 88 /d */ { 0, BX_IA_MOV_EbGb },
/* 89 /d */ { 0, BX_IA_MOV32_EdGd },
/* 8A /d */ { 0, BX_IA_MOV_GbEb },
/* 8B /d */ { 0, BX_IA_MOV32_GdEd },
/* 8C /d */ { 0, BX_IA_MOV_EwSw },
@ -886,18 +886,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* A1 /d */ { BxImmediate_O, BX_IA_MOV_EAXOd },
/* A2 /d */ { BxImmediate_O, BX_IA_MOV_OdAL },
/* A3 /d */ { BxImmediate_O, BX_IA_MOV_OdEAX },
/* A4 /d */ { 0, BX_IA_REP_MOVSB_XbYb },
/* A5 /d */ { 0, BX_IA_REP_MOVSD_XdYd },
/* A6 /d */ { 0, BX_IA_REP_CMPSB_XbYb },
/* A7 /d */ { 0, BX_IA_REP_CMPSD_XdYd },
/* A4 /d */ { BxRepeatable, BX_IA_REP_MOVSB_XbYb },
/* A5 /d */ { BxRepeatable, BX_IA_REP_MOVSD_XdYd },
/* A6 /d */ { BxRepeatable, BX_IA_REP_CMPSB_XbYb },
/* A7 /d */ { BxRepeatable, BX_IA_REP_CMPSD_XdYd },
/* A8 /d */ { BxImmediate_Ib, BX_IA_TEST_ALIb },
/* A9 /d */ { BxImmediate_Id, BX_IA_TEST_EAXId },
/* AA /d */ { 0, BX_IA_REP_STOSB_YbAL },
/* AB /d */ { 0, BX_IA_REP_STOSD_YdEAX },
/* AC /d */ { 0, BX_IA_REP_LODSB_ALXb },
/* AD /d */ { 0, BX_IA_REP_LODSD_EAXXd },
/* AE /d */ { 0, BX_IA_REP_SCASB_ALXb },
/* AF /d */ { 0, BX_IA_REP_SCASD_EAXXd },
/* AA /d */ { BxRepeatable, BX_IA_REP_STOSB_YbAL },
/* AB /d */ { BxRepeatable, BX_IA_REP_STOSD_YdEAX },
/* AC /d */ { BxRepeatable, BX_IA_REP_LODSB_ALXb },
/* AD /d */ { BxRepeatable, BX_IA_REP_LODSD_EAXXd },
/* AE /d */ { BxRepeatable, BX_IA_REP_SCASB_ALXb },
/* AF /d */ { BxRepeatable, BX_IA_REP_SCASD_EAXXd },
/* B0 /d */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
/* B1 /d */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
/* B2 /d */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
@ -1006,8 +1006,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 0D /d */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCHW on AMD, NOP on Intel
/* 0F 0E /d */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
/* 0F 0F /d */ { BxImmediate_Ib, BX_IA_ERROR }, // 3DNow! Opcode Table
/* 0F 10 /d */ { BxPrefixSSE, BX_IA_MOVUPS_VpsWps, BxOpcodeGroupSSE_0f10 },
/* 0F 11 /d */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVUPS_WpsVps, BxOpcodeGroupSSE_0f11 },
/* 0F 10 /d */ { BxPrefixSSE, BX_IA_MOVUPS_VpsWps, BxOpcodeGroupSSE_0f10 },
/* 0F 11 /d */ { BxPrefixSSE, BX_IA_MOVUPS_WpsVps, BxOpcodeGroupSSE_0f11 },
/* 0F 12 /d */ { BxPrefixSSE, BX_IA_MOVLPS_VpsMq, BxOpcodeGroupSSE_0f12 },
/* 0F 13 /d */ { BxPrefixSSE, BX_IA_MOVLPS_MqVps, BxOpcodeGroupSSE_0f13M },
/* 0F 14 /d */ { BxPrefixSSE, BX_IA_UNPCKLPS_VpsWdq, BxOpcodeGroupSSE_0f14 },
@ -1041,8 +1041,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 25 /d */ { 0, BX_IA_ERROR },
/* 0F 26 /d */ { 0, BX_IA_ERROR }, // BX_IA_MOV_TdRd not implemented
/* 0F 27 /d */ { 0, BX_IA_ERROR },
/* 0F 28 /d */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /d */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
/* 0F 28 /d */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /d */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
/* 0F 2A /d */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
/* 0F 2B /d */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
/* 0F 2C /d */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
@ -1136,7 +1136,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 7C /d */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
/* 0F 7D /d */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
/* 0F 7E /d */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
/* 0F 7F /d */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
/* 0F 7F /d */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
/* 0F 80 /d */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jd },
/* 0F 81 /d */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jd },
/* 0F 82 /d */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JB_Jd },
@ -1275,7 +1275,7 @@ BX_CPU_C::fetchDecode32(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
unsigned remain = remainingInPage; // remain must be at least 1
bx_bool is_32, lock=0;
unsigned b1, b2 = 0, os_32, ia_opcode = 0;
unsigned rm = 0, mod=0, nnn=0, mod_mem = 0;
unsigned rm = 0, mod=0, nnn=0, mod_mem = 0, rep = 0;
unsigned seg = BX_SEG_REG_DS, seg_override = BX_SEG_REG_NULL;
#define SSE_PREFIX_NONE 0
@ -1286,7 +1286,7 @@ BX_CPU_C::fetchDecode32(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
int vvv = -1;
#if BX_SUPPORT_AVX
int had_vex = 0, had_xop = 0;
int had_vex = 0, had_xop = 0, use_vvv = 0;
bx_bool vex_w = 0, vex_l = 0;
#endif
@ -1326,7 +1326,7 @@ fetch_b1:
case 0xf2: // REPNE/REPNZ
case 0xf3: // REP/REPE/REPZ
sse_prefix = (b1 & 3) ^ 1;
i->setRepUsed(b1 & 3);
rep = b1 & 3;
if (remain != 0) {
goto fetch_b1;
}
@ -1349,7 +1349,6 @@ fetch_b1:
return(-1);
case 0xf0: // LOCK:
lock = 1;
i->assertLock();
if (remain != 0) {
goto fetch_b1;
}
@ -1392,7 +1391,6 @@ fetch_b1:
return(-1);
vex_w = (vex >> 7) & 0x1;
i->setVexW(vex_w);
}
vvv = 15 - ((vex >> 3) & 0xf);
@ -1441,7 +1439,6 @@ fetch_b1:
return(-1);
vex_w = (vex >> 7) & 0x1;
i->setVexW(vex_w);
vvv = 15 - ((vex >> 3) & 0xf);
vex_l = (vex >> 2) & 0x1;
i->setVL(BX_VL128 + vex_l);
@ -1492,13 +1489,6 @@ fetch_b1:
nnn = (b2 >> 3) & 0x7;
rm = b2 & 0x7;
i->setNnn(nnn);
#if BX_SUPPORT_AVX
if (had_vex == 0)
#endif
vvv = nnn;
i->setVvv(vvv);
i->setFoo((b2 | (b1 << 8)) & 0x7ff); /* for x87 */
// MOVs with CRx and DRx always use register ops and ignore the mod field.
@ -1507,13 +1497,10 @@ fetch_b1:
if (mod == 0xc0) { // mod == 11b
i->assertModC0();
i->setRm(rm);
goto modrm_done;
}
mod_mem = 1;
i->setRm(BX_TMP_REGISTER);
i->setSibBase(rm); // initialize with rm to use BxResolve32Base
i->setSibIndex(BX_NIL_REGISTER);
// initialize displ32 with zero to include cases with no diplacement
@ -1681,10 +1668,6 @@ modrm_done:
switch(group) {
case BxGroupN:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn]);
#if BX_SUPPORT_AVX
if (had_vex == 0)
#endif
i->setVvv(rm);
break;
case BxSplitGroupN:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn + (mod_mem << 3)]);
@ -1727,7 +1710,7 @@ modrm_done:
case BxPrefixVEX:
continue;
default:
BX_PANIC(("fetchdecode: Unknown opcode group %d", group));
BX_PANIC(("fetchdecode32: Unknown opcode group %d", group));
}
/* get additional attributes from group table */
@ -1746,14 +1729,12 @@ modrm_done:
#if BX_SUPPORT_AVX
if (had_vex != 0) {
i->setVvv(vvv);
if (had_vex < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
OpcodeInfoPtr = &BxOpcodeTableAVX[(b1-256) + 768*vex_l];
}
else if (had_xop != 0) {
i->setVvv(vvv);
if (had_xop < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
@ -1767,8 +1748,8 @@ modrm_done:
}
ia_opcode = OpcodeInfoPtr->IA;
i->setRm(b1 & 7);
i->setNnn((b1 >> 3) & 0x7);
rm = b1 & 0x7;
nnn = (b1 >> 3) & 0x7;
}
if (lock) { // lock prefix invalid opcode
@ -1777,7 +1758,7 @@ modrm_done:
#if BX_CPU_LEVEL >= 6
if (BX_CPUID_SUPPORT_CPU_EXTENSION(BX_CPU_ALT_MOV_CR8) &&
(ia_opcode == BX_IA_MOV_CR0Rd || ia_opcode == BX_IA_MOV_RdCR0)) {
i->setNnn(8); // extend CR0 -> CR8
nnn = 8; // extend CR0 -> CR8
}
else
#endif
@ -1789,6 +1770,9 @@ modrm_done:
}
}
if (attr & BxRepeatable)
i->setRepUsed(rep);
unsigned imm_mode = attr & BxImmediate;
if (imm_mode) {
// make sure iptr was advanced after Ib(), Iw() and Id()
@ -1859,20 +1843,9 @@ modrm_done:
else return(-1);
}
break;
#if BX_SUPPORT_AVX
case BxImmediate_Ib4:
if (remain != 0) {
i->modRMForm.Ib = (*iptr >> 4) & 7;
remain--;
}
else {
return(-1);
}
break;
#endif
default:
BX_INFO(("b1 was %x", b1));
BX_PANIC(("fetchdecode: imm_mode = %u", imm_mode));
BX_PANIC(("fetchdecode32: imm_mode = %u", imm_mode));
}
unsigned imm_mode2 = attr & BxImmediate2;
@ -1905,9 +1878,55 @@ modrm_done:
#if BX_SUPPORT_3DNOW
if(b1 == 0x10f)
ia_opcode = Bx3DNowOpcode[i->modRMForm.Ib];
ia_opcode = Bx3DNowOpcode[i->modRMForm.Ib];
#endif
// assign sources
for (unsigned n = 0; n <= 3; n++) {
unsigned def = (unsigned) BxOpcodesTable[ia_opcode].src[n] & 0xf;
#if BX_SUPPORT_AVX
if (def == BX_SRC_RM_VIB) {
def = (vex_w) ? BX_SRC_RM : BX_SRC_VIB;
}
else if (def == BX_SRC_VIB_RM) {
def = (vex_w) ? BX_SRC_VIB : BX_SRC_RM;
}
else if (def == BX_SRC_RM_VVV) {
def = (vex_w) ? BX_SRC_RM : BX_SRC_VVV;
}
else if (def == BX_SRC_VVV_RM) {
def = (vex_w) ? BX_SRC_VVV : BX_SRC_RM;
}
#endif
switch(def) {
case BX_SRC_EAX:
i->setSrcReg(n, 0);
break;
case BX_SRC_NNN:
i->setSrcReg(n, nnn);
break;
case BX_SRC_RM:
i->setSrcReg(n, mod_mem ? BX_TMP_REGISTER : rm);
break;
#if BX_SUPPORT_AVX
case BX_SRC_MEM_NO_VVV:
if (mod_mem) break;
// else fall through
case BX_SRC_VVV:
i->setSrcReg(n, vvv);
use_vvv = 1;
break;
case BX_SRC_VIB:
i->setSrcReg(n, (i->Ib() >> 4) & 7);
break;
#endif
default:
if (def != BX_SRC_NONE)
BX_PANIC(("fetchdecode32: unknown definition %d for src %d", def, n));
}
}
// assign memory segment override
if (! BX_NULL_SEG_REG(seg_override))
seg = seg_override;
i->setSeg(seg);
@ -1915,21 +1934,20 @@ modrm_done:
i->setILen(remainingInPage - remain);
i->setIaOpcode(ia_opcode);
#if BX_CPU_LEVEL >= 6
Bit32u op_flags = BxOpcodesTable[ia_opcode].flags;
#endif
#if BX_SUPPORT_AVX
if (had_vex > 0 || had_xop > 0) {
if (! use_vvv && vvv != 0) {
ia_opcode = BX_IA_ERROR;
}
if ((attr & BxVexW0) != 0 && vex_w) {
ia_opcode = BX_IA_ERROR;
}
if ((attr & BxVexW1) != 0 && !vex_w) {
ia_opcode = BX_IA_ERROR;
}
if ((op_flags & BX_VEX_NO_VVV) && i->vvv() != 0) {
ia_opcode = BX_IA_ERROR;
}
}
else {
BX_ASSERT(! use_vvv);
}
#endif
@ -1949,16 +1967,12 @@ modrm_done:
else {
i->execute = BxOpcodesTable[ia_opcode].execute2;
i->execute2 = NULL;
if (attr & BxArithDstRM) {
i->setRm(nnn);
i->setNnn(rm);
}
}
BX_ASSERT(i->execute);
#if BX_CPU_LEVEL >= 6
Bit32u op_flags = BxOpcodesTable[ia_opcode].src[3];
if (! BX_CPU_THIS_PTR sse_ok) {
if (op_flags & BX_PREPARE_SSE) {
if (i->execute != &BX_CPU_C::BxError) i->execute = &BX_CPU_C::BxNoSSE;
@ -2007,7 +2021,7 @@ const char *get_bx_opcode_name(Bit16u ia_opcode)
{
static const char* BxOpcodeNamesTable[BX_IA_LAST] =
{
#define bx_define_opcode(a, b, c, d, e) #a,
#define bx_define_opcode(a, b, c, d, s1, s2, s3, s4, e) #a,
#include "ia_opcodes.h"
};
#undef bx_define_opcode
@ -2019,7 +2033,7 @@ void BX_CPU_C::init_FetchDecodeTables(void)
{
static Bit64u BxOpcodeFeatures[BX_IA_LAST] =
{
#define bx_define_opcode(a, b, c, d, e) d,
#define bx_define_opcode(a, b, c, d, s1, s2, s3, s4, e) d,
#include "ia_opcodes.h"
};
#undef bx_define_opcode
@ -2039,7 +2053,7 @@ void BX_CPU_C::init_FetchDecodeTables(void)
BxOpcodesTable[n].execute1 = &BX_CPU_C::BxError;
BxOpcodesTable[n].execute2 = &BX_CPU_C::BxError;
// won't allow this new #UD opcode to check prepare_SSE and similar
BxOpcodesTable[n].flags = 0;
BxOpcodesTable[n].src[3] = 0;
}
}

23
bochs/cpu/fetchdecode.h
View File

@ -59,16 +59,31 @@ BX_CPP_INLINE Bit64u FetchQWORD(const Bit8u *iptr)
}
#endif
#define BX_PREPARE_SSE (0x01)
#define BX_PREPARE_AVX (0x02)
#define BX_VEX_NO_VVV (0x04) /* no VEX.VVV allowed */
#define BX_PREPARE_SSE (0x80)
#define BX_PREPARE_AVX (0x40)
struct bxIAOpcodeTable {
BxExecutePtr_tR execute1;
BxExecutePtr_tR execute2;
Bit32u flags;
Bit8u src[4];
};
enum {
BX_SRC_NONE = 0,
BX_SRC_EAX,
BX_SRC_NNN,
BX_SRC_RM,
BX_SRC_MEM_NO_VVV,
BX_SRC_VVV,
BX_SRC_VIB,
BX_SRC_VIB_RM, // RM when VEX.W = 1, VIB otherwise
BX_SRC_RM_VIB, // RM when VEX.W = 0, VIB otherwise
BX_SRC_RM_VVV, // RM when VEX.W = 1, VVV otherwise
BX_SRC_VVV_RM // RM when VEX.W = 0, VVV otherwise
};
#define BX_SRC_XMM0 (BX_SRC_EAX)
//
// Common FetchDecode Opcode Tables
//

336
bochs/cpu/fetchdecode64.cc
View File

@ -139,64 +139,64 @@ extern struct bxIAOpcodeTable BxOpcodesTable[];
static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
// 512 entries for 16bit mode
/* 00 /w */ { BxArithDstRM | BxLockable, BX_IA_ADD_EbGb },
/* 01 /w */ { BxArithDstRM | BxLockable, BX_IA_ADD_EwGw },
/* 00 /w */ { BxLockable, BX_IA_ADD_EbGb },
/* 01 /w */ { BxLockable, BX_IA_ADD_EwGw },
/* 02 /w */ { 0, BX_IA_ADD_GbEb },
/* 03 /w */ { 0, BX_IA_ADD_GwEw },
/* 04 /w */ { BxImmediate_Ib, BX_IA_ADD_ALIb },
/* 05 /w */ { BxImmediate_Iw, BX_IA_ADD_AXIw },
/* 06 /w */ { 0, BX_IA_ERROR },
/* 07 /w */ { 0, BX_IA_ERROR },
/* 08 /w */ { BxArithDstRM | BxLockable, BX_IA_OR_EbGb },
/* 09 /w */ { BxArithDstRM | BxLockable, BX_IA_OR_EwGw },
/* 08 /w */ { BxLockable, BX_IA_OR_EbGb },
/* 09 /w */ { BxLockable, BX_IA_OR_EwGw },
/* 0A /w */ { 0, BX_IA_OR_GbEb },
/* 0B /w */ { 0, BX_IA_OR_GwEw },
/* 0C /w */ { BxImmediate_Ib, BX_IA_OR_ALIb },
/* 0D /w */ { BxImmediate_Iw, BX_IA_OR_AXIw },
/* 0E /w */ { 0, BX_IA_ERROR },
/* 0F /w */ { 0, BX_IA_ERROR }, // 2-byte escape
/* 10 /w */ { BxArithDstRM | BxLockable, BX_IA_ADC_EbGb },
/* 11 /w */ { BxArithDstRM | BxLockable, BX_IA_ADC_EwGw },
/* 10 /w */ { BxLockable, BX_IA_ADC_EbGb },
/* 11 /w */ { BxLockable, BX_IA_ADC_EwGw },
/* 12 /w */ { 0, BX_IA_ADC_GbEb },
/* 13 /w */ { 0, BX_IA_ADC_GwEw },
/* 14 /w */ { BxImmediate_Ib, BX_IA_ADC_ALIb },
/* 15 /w */ { BxImmediate_Iw, BX_IA_ADC_AXIw },
/* 16 /w */ { 0, BX_IA_ERROR },
/* 17 /w */ { 0, BX_IA_ERROR },
/* 18 /w */ { BxArithDstRM | BxLockable, BX_IA_SBB_EbGb },
/* 19 /w */ { BxArithDstRM | BxLockable, BX_IA_SBB_EwGw },
/* 18 /w */ { BxLockable, BX_IA_SBB_EbGb },
/* 19 /w */ { BxLockable, BX_IA_SBB_EwGw },
/* 1A /w */ { 0, BX_IA_SBB_GbEb },
/* 1B /w */ { 0, BX_IA_SBB_GwEw },
/* 1C /w */ { BxImmediate_Ib, BX_IA_SBB_ALIb },
/* 1D /w */ { BxImmediate_Iw, BX_IA_SBB_AXIw },
/* 1E /w */ { 0, BX_IA_ERROR },
/* 1F /w */ { 0, BX_IA_ERROR },
/* 20 /w */ { BxArithDstRM | BxLockable, BX_IA_AND_EbGb },
/* 21 /w */ { BxArithDstRM | BxLockable, BX_IA_AND_EwGw },
/* 20 /w */ { BxLockable, BX_IA_AND_EbGb },
/* 21 /w */ { BxLockable, BX_IA_AND_EwGw },
/* 22 /w */ { 0, BX_IA_AND_GbEb },
/* 23 /w */ { 0, BX_IA_AND_GwEw },
/* 24 /w */ { BxImmediate_Ib, BX_IA_AND_ALIb },
/* 25 /w */ { BxImmediate_Iw, BX_IA_AND_AXIw },
/* 26 /w */ { 0, BX_IA_ERROR }, // ES:
/* 27 /w */ { 0, BX_IA_ERROR },
/* 28 /w */ { BxArithDstRM | BxLockable, BX_IA_SUB_EbGb },
/* 29 /w */ { BxArithDstRM | BxLockable, BX_IA_SUB_EwGw },
/* 28 /w */ { BxLockable, BX_IA_SUB_EbGb },
/* 29 /w */ { BxLockable, BX_IA_SUB_EwGw },
/* 2A /w */ { 0, BX_IA_SUB_GbEb },
/* 2B /w */ { 0, BX_IA_SUB_GwEw },
/* 2C /w */ { BxImmediate_Ib, BX_IA_SUB_ALIb },
/* 2D /w */ { BxImmediate_Iw, BX_IA_SUB_AXIw },
/* 2E /w */ { 0, BX_IA_ERROR }, // CS:
/* 2F /w */ { 0, BX_IA_ERROR },
/* 30 /w */ { BxArithDstRM | BxLockable, BX_IA_XOR_EbGb },
/* 31 /w */ { BxArithDstRM | BxLockable, BX_IA_XOR_EwGw },
/* 30 /w */ { BxLockable, BX_IA_XOR_EbGb },
/* 31 /w */ { BxLockable, BX_IA_XOR_EwGw },
/* 32 /w */ { 0, BX_IA_XOR_GbEb },
/* 33 /w */ { 0, BX_IA_XOR_GwEw },
/* 34 /w */ { BxImmediate_Ib, BX_IA_XOR_ALIb },
/* 35 /w */ { BxImmediate_Iw, BX_IA_XOR_AXIw },
/* 36 /w */ { 0, BX_IA_ERROR }, // SS:
/* 37 /w */ { 0, BX_IA_ERROR },
/* 38 /w */ { BxArithDstRM, BX_IA_CMP_EbGb },
/* 39 /w */ { BxArithDstRM, BX_IA_CMP_EwGw },
/* 38 /w */ { 0, BX_IA_CMP_EbGb },
/* 39 /w */ { 0, BX_IA_CMP_EwGw },
/* 3A /w */ { 0, BX_IA_CMP_GbEb },
/* 3B /w */ { 0, BX_IA_CMP_GwEw },
/* 3C /w */ { BxImmediate_Ib, BX_IA_CMP_ALIb },
@ -247,10 +247,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 69 /w */ { BxImmediate_Iw, BX_IA_IMUL_GwEwIw },
/* 6A /w */ { BxImmediate_Ib_SE, BX_IA_PUSH_Iw },
/* 6B /w */ { BxImmediate_Ib_SE, BX_IA_IMUL_GwEwIw },
/* 6C /w */ { 0, BX_IA_REP_INSB_YbDX },
/* 6D /w */ { 0, BX_IA_REP_INSW_YwDX },
/* 6E /w */ { 0, BX_IA_REP_OUTSB_DXXb },
/* 6F /w */ { 0, BX_IA_REP_OUTSW_DXXw },
/* 6C /w */ { BxRepeatable, BX_IA_REP_INSB_YbDX },
/* 6D /w */ { BxRepeatable, BX_IA_REP_INSW_YwDX },
/* 6E /w */ { BxRepeatable, BX_IA_REP_OUTSB_DXXb },
/* 6F /w */ { BxRepeatable, BX_IA_REP_OUTSW_DXXw },
/* 70 /w */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JO_Jq },
/* 71 /w */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JNO_Jq },
/* 72 /w */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JB_Jq },
@ -275,8 +275,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 85 /w */ { 0, BX_IA_TEST_EwGw },
/* 86 /w */ { BxLockable, BX_IA_XCHG_EbGb },
/* 87 /w */ { BxLockable, BX_IA_XCHG_EwGw },
/* 88 /w */ { BxArithDstRM, BX_IA_MOV_EbGb },
/* 89 /w */ { BxArithDstRM, BX_IA_MOV_EwGw },
/* 88 /w */ { 0, BX_IA_MOV_EbGb },
/* 89 /w */ { 0, BX_IA_MOV_EwGw },
/* 8A /w */ { 0, BX_IA_MOV_GbEb },
/* 8B /w */ { 0, BX_IA_MOV_GwEw },
/* 8C /w */ { 0, BX_IA_MOV_EwSw },
@ -303,18 +303,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* A1 /w */ { BxImmediate_O, BX_IA_MOV_AXOq },
/* A2 /w */ { BxImmediate_O, BX_IA_MOV_OqAL },
/* A3 /w */ { BxImmediate_O, BX_IA_MOV_OqAX },
/* A4 /w */ { 0, BX_IA_REP_MOVSB_XbYb },
/* A5 /w */ { 0, BX_IA_REP_MOVSW_XwYw },
/* A6 /w */ { 0, BX_IA_REP_CMPSB_XbYb },
/* A7 /w */ { 0, BX_IA_REP_CMPSW_XwYw },
/* A4 /w */ { BxRepeatable, BX_IA_REP_MOVSB_XbYb },
/* A5 /w */ { BxRepeatable, BX_IA_REP_MOVSW_XwYw },
/* A6 /w */ { BxRepeatable, BX_IA_REP_CMPSB_XbYb },
/* A7 /w */ { BxRepeatable, BX_IA_REP_CMPSW_XwYw },
/* A8 /w */ { BxImmediate_Ib, BX_IA_TEST_ALIb },
/* A9 /w */ { BxImmediate_Iw, BX_IA_TEST_AXIw },
/* AA /w */ { 0, BX_IA_REP_STOSB_YbAL },
/* AB /w */ { 0, BX_IA_REP_STOSW_YwAX },
/* AC /w */ { 0, BX_IA_REP_LODSB_ALXb },
/* AD /w */ { 0, BX_IA_REP_LODSW_AXXw },
/* AE /w */ { 0, BX_IA_REP_SCASB_ALXb },
/* AF /w */ { 0, BX_IA_REP_SCASW_AXXw },
/* AA /w */ { BxRepeatable, BX_IA_REP_STOSB_YbAL },
/* AB /w */ { BxRepeatable, BX_IA_REP_STOSW_YwAX },
/* AC /w */ { BxRepeatable, BX_IA_REP_LODSB_ALXb },
/* AD /w */ { BxRepeatable, BX_IA_REP_LODSW_AXXw },
/* AE /w */ { BxRepeatable, BX_IA_REP_SCASB_ALXb },
/* AF /w */ { BxRepeatable, BX_IA_REP_SCASW_AXXw },
/* B0 /w */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
/* B1 /w */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
/* B2 /w */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
@ -412,8 +412,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 0D /w */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCHW on AMD, NOP on Intel
/* 0F 0E /w */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
/* 0F 0F /w */ { BxImmediate_Ib, BX_IA_ERROR }, // 3DNow! Opcode Table
/* 0F 10 /w */ { BxPrefixSSE, BX_IA_MOVUPS_VpsWps, BxOpcodeGroupSSE_0f10 },
/* 0F 11 /w */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVUPS_WpsVps, BxOpcodeGroupSSE_0f11 },
/* 0F 10 /w */ { BxPrefixSSE, BX_IA_MOVUPS_VpsWps, BxOpcodeGroupSSE_0f10 },
/* 0F 11 /w */ { BxPrefixSSE, BX_IA_MOVUPS_WpsVps, BxOpcodeGroupSSE_0f11 },
/* 0F 12 /w */ { BxPrefixSSE, BX_IA_MOVLPS_VpsMq, BxOpcodeGroupSSE_0f12 },
/* 0F 13 /w */ { BxPrefixSSE, BX_IA_MOVLPS_MqVps, BxOpcodeGroupSSE_0f13M },
/* 0F 14 /w */ { BxPrefixSSE, BX_IA_UNPCKLPS_VpsWdq, BxOpcodeGroupSSE_0f14 },
@ -436,8 +436,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 25 /w */ { 0, BX_IA_ERROR },
/* 0F 26 /w */ { 0, BX_IA_ERROR },
/* 0F 27 /w */ { 0, BX_IA_ERROR },
/* 0F 28 /w */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /w */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
/* 0F 28 /w */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /w */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
/* 0F 2A /w */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
/* 0F 2B /w */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
/* 0F 2C /w */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
@ -523,7 +523,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 7C /w */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
/* 0F 7D /w */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
/* 0F 7E /w */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
/* 0F 7F /w */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
/* 0F 7F /w */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
/* 0F 80 /w */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jq },
/* 0F 81 /w */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jq },
/* 0F 82 /w */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JB_Jq },
@ -654,64 +654,64 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F FF /w */ { 0, BX_IA_ERROR },
// 512 entries for 32bit mode
/* 00 /d */ { BxArithDstRM | BxLockable, BX_IA_ADD_EbGb },
/* 01 /d */ { BxArithDstRM | BxLockable, BX_IA_ADD_EdGd },
/* 00 /d */ { BxLockable, BX_IA_ADD_EbGb },
/* 01 /d */ { BxLockable, BX_IA_ADD_EdGd },
/* 02 /d */ { 0, BX_IA_ADD_GbEb },
/* 03 /d */ { 0, BX_IA_ADD_GdEd },
/* 04 /d */ { BxImmediate_Ib, BX_IA_ADD_ALIb },
/* 05 /d */ { BxImmediate_Id, BX_IA_ADD_EAXId },
/* 06 /d */ { 0, BX_IA_ERROR },
/* 07 /d */ { 0, BX_IA_ERROR },
/* 08 /d */ { BxArithDstRM | BxLockable, BX_IA_OR_EbGb },
/* 09 /d */ { BxArithDstRM | BxLockable, BX_IA_OR_EdGd },
/* 08 /d */ { BxLockable, BX_IA_OR_EbGb },
/* 09 /d */ { BxLockable, BX_IA_OR_EdGd },
/* 0A /d */ { 0, BX_IA_OR_GbEb },
/* 0B /d */ { 0, BX_IA_OR_GdEd },
/* 0C /d */ { BxImmediate_Ib, BX_IA_OR_ALIb },
/* 0D /d */ { BxImmediate_Id, BX_IA_OR_EAXId },
/* 0E /d */ { 0, BX_IA_ERROR },
/* 0F /d */ { 0, BX_IA_ERROR }, // 2-byte escape
/* 10 /d */ { BxArithDstRM | BxLockable, BX_IA_ADC_EbGb },
/* 11 /d */ { BxArithDstRM | BxLockable, BX_IA_ADC_EdGd },
/* 10 /d */ { BxLockable, BX_IA_ADC_EbGb },
/* 11 /d */ { BxLockable, BX_IA_ADC_EdGd },
/* 12 /d */ { 0, BX_IA_ADC_GbEb },
/* 13 /d */ { 0, BX_IA_ADC_GdEd },
/* 14 /d */ { BxImmediate_Ib, BX_IA_ADC_ALIb },
/* 15 /d */ { BxImmediate_Id, BX_IA_ADC_EAXId },
/* 16 /d */ { 0, BX_IA_ERROR },
/* 17 /d */ { 0, BX_IA_ERROR },
/* 18 /d */ { BxArithDstRM | BxLockable, BX_IA_SBB_EbGb },
/* 19 /d */ { BxArithDstRM | BxLockable, BX_IA_SBB_EdGd },
/* 18 /d */ { BxLockable, BX_IA_SBB_EbGb },
/* 19 /d */ { BxLockable, BX_IA_SBB_EdGd },
/* 1A /d */ { 0, BX_IA_SBB_GbEb },
/* 1B /d */ { 0, BX_IA_SBB_GdEd },
/* 1C /d */ { BxImmediate_Ib, BX_IA_SBB_ALIb },
/* 1D /d */ { BxImmediate_Id, BX_IA_SBB_EAXId },
/* 1E /d */ { 0, BX_IA_ERROR },
/* 1F /d */ { 0, BX_IA_ERROR },
/* 20 /d */ { BxArithDstRM | BxLockable, BX_IA_AND_EbGb },
/* 21 /d */ { BxArithDstRM | BxLockable, BX_IA_AND_EdGd },
/* 20 /d */ { BxLockable, BX_IA_AND_EbGb },
/* 21 /d */ { BxLockable, BX_IA_AND_EdGd },
/* 22 /d */ { 0, BX_IA_AND_GbEb },
/* 23 /d */ { 0, BX_IA_AND_GdEd },
/* 24 /d */ { BxImmediate_Ib, BX_IA_AND_ALIb },
/* 25 /d */ { BxImmediate_Id, BX_IA_AND_EAXId },
/* 26 /d */ { 0, BX_IA_ERROR }, // ES:
/* 27 /d */ { 0, BX_IA_ERROR },
/* 28 /d */ { BxArithDstRM | BxLockable, BX_IA_SUB_EbGb },
/* 29 /d */ { BxArithDstRM | BxLockable, BX_IA_SUB_EdGd },
/* 28 /d */ { BxLockable, BX_IA_SUB_EbGb },
/* 29 /d */ { BxLockable, BX_IA_SUB_EdGd },
/* 2A /d */ { 0, BX_IA_SUB_GbEb },
/* 2B /d */ { 0, BX_IA_SUB_GdEd },
/* 2C /d */ { BxImmediate_Ib, BX_IA_SUB_ALIb },
/* 2D /d */ { BxImmediate_Id, BX_IA_SUB_EAXId },
/* 2E /d */ { 0, BX_IA_ERROR }, // CS:
/* 2F /d */ { 0, BX_IA_ERROR },
/* 30 /d */ { BxArithDstRM | BxLockable, BX_IA_XOR_EbGb },
/* 31 /d */ { BxArithDstRM | BxLockable, BX_IA_XOR_EdGd },
/* 30 /d */ { BxLockable, BX_IA_XOR_EbGb },
/* 31 /d */ { BxLockable, BX_IA_XOR_EdGd },
/* 32 /d */ { 0, BX_IA_XOR_GbEb },
/* 33 /d */ { 0, BX_IA_XOR_GdEd },
/* 34 /d */ { BxImmediate_Ib, BX_IA_XOR_ALIb },
/* 35 /d */ { BxImmediate_Id, BX_IA_XOR_EAXId },
/* 36 /d */ { 0, BX_IA_ERROR }, // SS:
/* 37 /d */ { 0, BX_IA_ERROR },
/* 38 /d */ { BxArithDstRM, BX_IA_CMP_EbGb },
/* 39 /d */ { BxArithDstRM, BX_IA_CMP_EdGd },
/* 38 /d */ { 0, BX_IA_CMP_EbGb },
/* 39 /d */ { 0, BX_IA_CMP_EdGd },
/* 3A /d */ { 0, BX_IA_CMP_GbEb },
/* 3B /d */ { 0, BX_IA_CMP_GdEd },
/* 3C /d */ { BxImmediate_Ib, BX_IA_CMP_ALIb },
@ -762,10 +762,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 69 /d */ { BxImmediate_Id, BX_IA_IMUL_GdEdId },
/* 6A /d */ { BxImmediate_Ib_SE, BX_IA_PUSH64_Id },
/* 6B /d */ { BxImmediate_Ib_SE, BX_IA_IMUL_GdEdId },
/* 6C /d */ { 0, BX_IA_REP_INSB_YbDX },
/* 6D /d */ { 0, BX_IA_REP_INSD_YdDX },
/* 6E /d */ { 0, BX_IA_REP_OUTSB_DXXb },
/* 6F /d */ { 0, BX_IA_REP_OUTSD_DXXd },
/* 6C /d */ { BxRepeatable, BX_IA_REP_INSB_YbDX },
/* 6D /d */ { BxRepeatable, BX_IA_REP_INSD_YdDX },
/* 6E /d */ { BxRepeatable, BX_IA_REP_OUTSB_DXXb },
/* 6F /d */ { BxRepeatable, BX_IA_REP_OUTSD_DXXd },
/* 70 /d */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JO_Jq },
/* 71 /d */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JNO_Jq },
/* 72 /d */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JB_Jq },
@ -790,8 +790,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 85 /d */ { 0, BX_IA_TEST_EdGd },
/* 86 /d */ { BxLockable, BX_IA_XCHG_EbGb },
/* 87 /d */ { BxLockable, BX_IA_XCHG_EdGd },
/* 88 /d */ { BxArithDstRM, BX_IA_MOV_EbGb },
/* 89 /d */ { BxArithDstRM, BX_IA_MOV64_EdGd },
/* 88 /d */ { 0, BX_IA_MOV_EbGb },
/* 89 /d */ { 0, BX_IA_MOV64_EdGd },
/* 8A /d */ { 0, BX_IA_MOV_GbEb },
/* 8B /d */ { 0, BX_IA_MOV64_GdEd },
/* 8C /d */ { 0, BX_IA_MOV_EwSw },
@ -818,18 +818,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* A1 /d */ { BxImmediate_O, BX_IA_MOV_EAXOq },
/* A2 /d */ { BxImmediate_O, BX_IA_MOV_OqAL },
/* A3 /d */ { BxImmediate_O, BX_IA_MOV_OqEAX },
/* A4 /d */ { 0, BX_IA_REP_MOVSB_XbYb },
/* A5 /d */ { 0, BX_IA_REP_MOVSD_XdYd },
/* A6 /d */ { 0, BX_IA_REP_CMPSB_XbYb },
/* A7 /d */ { 0, BX_IA_REP_CMPSD_XdYd },
/* A4 /d */ { BxRepeatable, BX_IA_REP_MOVSB_XbYb },
/* A5 /d */ { BxRepeatable, BX_IA_REP_MOVSD_XdYd },
/* A6 /d */ { BxRepeatable, BX_IA_REP_CMPSB_XbYb },
/* A7 /d */ { BxRepeatable, BX_IA_REP_CMPSD_XdYd },
/* A8 /d */ { BxImmediate_Ib, BX_IA_TEST_ALIb },
/* A9 /d */ { BxImmediate_Id, BX_IA_TEST_EAXId },
/* AA /d */ { 0, BX_IA_REP_STOSB_YbAL },
/* AB /d */ { 0, BX_IA_REP_STOSD_YdEAX },
/* AC /d */ { 0, BX_IA_REP_LODSB_ALXb },
/* AD /d */ { 0, BX_IA_REP_LODSD_EAXXd },
/* AE /d */ { 0, BX_IA_REP_SCASB_ALXb },
/* AF /d */ { 0, BX_IA_REP_SCASD_EAXXd },
/* AA /d */ { BxRepeatable, BX_IA_REP_STOSB_YbAL },
/* AB /d */ { BxRepeatable, BX_IA_REP_STOSD_YdEAX },
/* AC /d */ { BxRepeatable, BX_IA_REP_LODSB_ALXb },
/* AD /d */ { BxRepeatable, BX_IA_REP_LODSD_EAXXd },
/* AE /d */ { BxRepeatable, BX_IA_REP_SCASB_ALXb },
/* AF /d */ { BxRepeatable, BX_IA_REP_SCASD_EAXXd },
/* B0 /d */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
/* B1 /d */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
/* B2 /d */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
@ -927,8 +927,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 0D /d */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCHW on AMD, NOP on Intel
/* 0F 0E /d */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
/* 0F 0F /d */ { BxImmediate_Ib, BX_IA_ERROR }, // 3DNow! Opcode Table
/* 0F 10 /d */ { BxPrefixSSE, BX_IA_MOVUPS_VpsWps, BxOpcodeGroupSSE_0f10 },
/* 0F 11 /d */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVUPS_WpsVps, BxOpcodeGroupSSE_0f11 },
/* 0F 10 /d */ { BxPrefixSSE, BX_IA_MOVUPS_VpsWps, BxOpcodeGroupSSE_0f10 },
/* 0F 11 /d */ { BxPrefixSSE, BX_IA_MOVUPS_WpsVps, BxOpcodeGroupSSE_0f11 },
/* 0F 12 /d */ { BxPrefixSSE, BX_IA_MOVLPS_VpsMq, BxOpcodeGroupSSE_0f12 },
/* 0F 13 /d */ { BxPrefixSSE, BX_IA_MOVLPS_MqVps, BxOpcodeGroupSSE_0f13M },
/* 0F 14 /d */ { BxPrefixSSE, BX_IA_UNPCKLPS_VpsWdq, BxOpcodeGroupSSE_0f14 },
@ -951,8 +951,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 25 /d */ { 0, BX_IA_ERROR },
/* 0F 26 /d */ { 0, BX_IA_ERROR },
/* 0F 27 /d */ { 0, BX_IA_ERROR },
/* 0F 28 /d */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /d */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
/* 0F 28 /d */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /d */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
/* 0F 2A /d */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2a },
/* 0F 2B /d */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
/* 0F 2C /d */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
@ -1038,7 +1038,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 7C /d */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
/* 0F 7D /d */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
/* 0F 7E /d */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
/* 0F 7F /d */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
/* 0F 7F /d */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
/* 0F 80 /d */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jq },
/* 0F 81 /d */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jq },
/* 0F 82 /d */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JB_Jq },
@ -1169,64 +1169,64 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F FF /d */ { 0, BX_IA_ERROR },
// 512 entries for 64bit mode
/* 00 /q */ { BxArithDstRM | BxLockable, BX_IA_ADD_EbGb },
/* 01 /q */ { BxArithDstRM | BxLockable, BX_IA_ADD_EqGq },
/* 00 /q */ { BxLockable, BX_IA_ADD_EbGb },
/* 01 /q */ { BxLockable, BX_IA_ADD_EqGq },
/* 02 /q */ { 0, BX_IA_ADD_GbEb },
/* 03 /q */ { 0, BX_IA_ADD_GqEq },
/* 04 /q */ { BxImmediate_Ib, BX_IA_ADD_ALIb },
/* 05 /q */ { BxImmediate_Id, BX_IA_ADD_RAXId },
/* 06 /q */ { 0, BX_IA_ERROR },
/* 07 /q */ { 0, BX_IA_ERROR },
/* 08 /q */ { BxArithDstRM | BxLockable, BX_IA_OR_EbGb },
/* 09 /q */ { BxArithDstRM | BxLockable, BX_IA_OR_EqGq },
/* 08 /q */ { BxLockable, BX_IA_OR_EbGb },
/* 09 /q */ { BxLockable, BX_IA_OR_EqGq },
/* 0A /q */ { 0, BX_IA_OR_GbEb },
/* 0B /q */ { 0, BX_IA_OR_GqEq },
/* 0C /q */ { BxImmediate_Ib, BX_IA_OR_ALIb },
/* 0D /q */ { BxImmediate_Id, BX_IA_OR_RAXId },
/* 0E /q */ { 0, BX_IA_ERROR },
/* 0F /q */ { 0, BX_IA_ERROR }, // 2-byte escape
/* 10 /q */ { BxArithDstRM | BxLockable, BX_IA_ADC_EbGb },
/* 11 /q */ { BxArithDstRM | BxLockable, BX_IA_ADC_EqGq },
/* 10 /q */ { BxLockable, BX_IA_ADC_EbGb },
/* 11 /q */ { BxLockable, BX_IA_ADC_EqGq },
/* 12 /q */ { 0, BX_IA_ADC_GbEb },
/* 13 /q */ { 0, BX_IA_ADC_GqEq },
/* 14 /q */ { BxImmediate_Ib, BX_IA_ADC_ALIb },
/* 15 /q */ { BxImmediate_Id, BX_IA_ADC_RAXId },
/* 16 /q */ { 0, BX_IA_ERROR },
/* 17 /q */ { 0, BX_IA_ERROR },
/* 18 /q */ { BxArithDstRM | BxLockable, BX_IA_SBB_EbGb },
/* 19 /q */ { BxArithDstRM | BxLockable, BX_IA_SBB_EqGq },
/* 18 /q */ { BxLockable, BX_IA_SBB_EbGb },
/* 19 /q */ { BxLockable, BX_IA_SBB_EqGq },
/* 1A /q */ { 0, BX_IA_SBB_GbEb },
/* 1B /q */ { 0, BX_IA_SBB_GqEq },
/* 1C /q */ { BxImmediate_Ib, BX_IA_SBB_ALIb },
/* 1D /q */ { BxImmediate_Id, BX_IA_SBB_RAXId },
/* 1E /q */ { 0, BX_IA_ERROR },
/* 1F /q */ { 0, BX_IA_ERROR },
/* 20 /q */ { BxArithDstRM | BxLockable, BX_IA_AND_EbGb },
/* 21 /q */ { BxArithDstRM | BxLockable, BX_IA_AND_EqGq },
/* 20 /q */ { BxLockable, BX_IA_AND_EbGb },
/* 21 /q */ { BxLockable, BX_IA_AND_EqGq },
/* 22 /q */ { 0, BX_IA_AND_GbEb },
/* 23 /q */ { 0, BX_IA_AND_GqEq },
/* 24 /q */ { BxImmediate_Ib, BX_IA_AND_ALIb },
/* 25 /q */ { BxImmediate_Id, BX_IA_AND_RAXId },
/* 26 /q */ { 0, BX_IA_ERROR }, // ES:
/* 27 /q */ { 0, BX_IA_ERROR },
/* 28 /q */ { BxArithDstRM | BxLockable, BX_IA_SUB_EbGb },
/* 29 /q */ { BxArithDstRM | BxLockable, BX_IA_SUB_EqGq },
/* 28 /q */ { BxLockable, BX_IA_SUB_EbGb },
/* 29 /q */ { BxLockable, BX_IA_SUB_EqGq },
/* 2A /q */ { 0, BX_IA_SUB_GbEb },
/* 2B /q */ { 0, BX_IA_SUB_GqEq },
/* 2C /q */ { BxImmediate_Ib, BX_IA_SUB_ALIb },
/* 2D /q */ { BxImmediate_Id, BX_IA_SUB_RAXId },
/* 2E /q */ { 0, BX_IA_ERROR }, // CS:
/* 2F /q */ { 0, BX_IA_ERROR },
/* 30 /q */ { BxArithDstRM | BxLockable, BX_IA_XOR_EbGb },
/* 31 /q */ { BxArithDstRM | BxLockable, BX_IA_XOR_EqGq },
/* 30 /q */ { BxLockable, BX_IA_XOR_EbGb },
/* 31 /q */ { BxLockable, BX_IA_XOR_EqGq },
/* 32 /q */ { 0, BX_IA_XOR_GbEb },
/* 33 /q */ { 0, BX_IA_XOR_GqEq },
/* 34 /q */ { BxImmediate_Ib, BX_IA_XOR_ALIb },
/* 35 /q */ { BxImmediate_Id, BX_IA_XOR_RAXId },
/* 36 /q */ { 0, BX_IA_ERROR }, // SS:
/* 37 /q */ { 0, BX_IA_ERROR },
/* 38 /q */ { BxArithDstRM, BX_IA_CMP_EbGb },
/* 39 /q */ { BxArithDstRM, BX_IA_CMP_EqGq },
/* 38 /q */ { 0, BX_IA_CMP_EbGb },
/* 39 /q */ { 0, BX_IA_CMP_EqGq },
/* 3A /q */ { 0, BX_IA_CMP_GbEb },
/* 3B /q */ { 0, BX_IA_CMP_GqEq },
/* 3C /q */ { BxImmediate_Ib, BX_IA_CMP_ALIb },
@ -1277,10 +1277,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 69 /q */ { BxImmediate_Id, BX_IA_IMUL_GqEqId },
/* 6A /q */ { BxImmediate_Ib_SE, BX_IA_PUSH64_Id },
/* 6B /q */ { BxImmediate_Ib_SE, BX_IA_IMUL_GqEqId },
/* 6C /q */ { 0, BX_IA_REP_INSB_YbDX },
/* 6D /q */ { 0, BX_IA_REP_INSD_YdDX },
/* 6E /q */ { 0, BX_IA_REP_OUTSB_DXXb },
/* 6F /q */ { 0, BX_IA_REP_OUTSD_DXXd },
/* 6C /q */ { BxRepeatable, BX_IA_REP_INSB_YbDX },
/* 6D /q */ { BxRepeatable, BX_IA_REP_INSD_YdDX },
/* 6E /q */ { BxRepeatable, BX_IA_REP_OUTSB_DXXb },
/* 6F /q */ { BxRepeatable, BX_IA_REP_OUTSD_DXXd },
/* 70 /q */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JO_Jq },
/* 71 /q */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JNO_Jq },
/* 72 /q */ { BxImmediate_BrOff8 | BxTraceJCC, BX_IA_JB_Jq },
@ -1305,8 +1305,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 85 /q */ { 0, BX_IA_TEST_EqGq },
/* 86 /q */ { BxLockable, BX_IA_XCHG_EbGb },
/* 87 /q */ { BxLockable, BX_IA_XCHG_EqGq },
/* 88 /q */ { BxArithDstRM, BX_IA_MOV_EbGb },
/* 89 /q */ { BxArithDstRM, BX_IA_MOV_EqGq },
/* 88 /q */ { 0, BX_IA_MOV_EbGb },
/* 89 /q */ { 0, BX_IA_MOV_EqGq },
/* 8A /q */ { 0, BX_IA_MOV_GbEb },
/* 8B /q */ { 0, BX_IA_MOV_GqEq },
/* 8C /q */ { 0, BX_IA_MOV_EwSw },
@ -1333,18 +1333,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* A1 /q */ { BxImmediate_O, BX_IA_MOV_RAXOq },
/* A2 /q */ { BxImmediate_O, BX_IA_MOV_OqAL },
/* A3 /q */ { BxImmediate_O, BX_IA_MOV_OqRAX },
/* A4 /q */ { 0, BX_IA_REP_MOVSB_XbYb },
/* A5 /q */ { 0, BX_IA_REP_MOVSQ_XqYq },
/* A6 /q */ { 0, BX_IA_REP_CMPSB_XbYb },
/* A7 /q */ { 0, BX_IA_REP_CMPSQ_XqYq },
/* A4 /q */ { BxRepeatable, BX_IA_REP_MOVSB_XbYb },
/* A5 /q */ { BxRepeatable, BX_IA_REP_MOVSQ_XqYq },
/* A6 /q */ { BxRepeatable, BX_IA_REP_CMPSB_XbYb },
/* A7 /q */ { BxRepeatable, BX_IA_REP_CMPSQ_XqYq },
/* A8 /q */ { BxImmediate_Ib, BX_IA_TEST_ALIb },
/* A9 /q */ { BxImmediate_Id, BX_IA_TEST_RAXId },
/* AA /q */ { 0, BX_IA_REP_STOSB_YbAL },
/* AB /q */ { 0, BX_IA_REP_STOSQ_YqRAX },
/* AC /q */ { 0, BX_IA_REP_LODSB_ALXb },
/* AD /q */ { 0, BX_IA_REP_LODSQ_RAXXq },
/* AE /q */ { 0, BX_IA_REP_SCASB_ALXb },
/* AF /q */ { 0, BX_IA_REP_SCASQ_RAXXq },
/* AA /q */ { BxRepeatable, BX_IA_REP_STOSB_YbAL },
/* AB /q */ { BxRepeatable, BX_IA_REP_STOSQ_YqRAX },
/* AC /q */ { BxRepeatable, BX_IA_REP_LODSB_ALXb },
/* AD /q */ { BxRepeatable, BX_IA_REP_LODSQ_RAXXq },
/* AE /q */ { BxRepeatable, BX_IA_REP_SCASB_ALXb },
/* AF /q */ { BxRepeatable, BX_IA_REP_SCASQ_RAXXq },
/* B0 /q */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
/* B1 /q */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
/* B2 /q */ { BxImmediate_Ib, BX_IA_MOV_RLIb },
@ -1442,8 +1442,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 0D /q */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCHW on AMD, NOP on Intel
/* 0F 0E /q */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
/* 0F 0F /q */ { BxImmediate_Ib, BX_IA_ERROR }, // 3DNow! Opcode Table
/* 0F 10 /q */ { BxPrefixSSE, BX_IA_MOVUPS_VpsWps, BxOpcodeGroupSSE_0f10 },
/* 0F 11 /q */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVUPS_WpsVps, BxOpcodeGroupSSE_0f11 },
/* 0F 10 /q */ { BxPrefixSSE, BX_IA_MOVUPS_VpsWps, BxOpcodeGroupSSE_0f10 },
/* 0F 11 /q */ { BxPrefixSSE, BX_IA_MOVUPS_WpsVps, BxOpcodeGroupSSE_0f11 },
/* 0F 12 /q */ { BxPrefixSSE, BX_IA_MOVLPS_VpsMq, BxOpcodeGroupSSE_0f12 },
/* 0F 13 /q */ { BxPrefixSSE, BX_IA_MOVLPS_MqVps, BxOpcodeGroupSSE_0f13M },
/* 0F 14 /q */ { BxPrefixSSE, BX_IA_UNPCKLPS_VpsWdq, BxOpcodeGroupSSE_0f14 },
@ -1466,8 +1466,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 25 /q */ { 0, BX_IA_ERROR },
/* 0F 26 /q */ { 0, BX_IA_ERROR },
/* 0F 27 /q */ { 0, BX_IA_ERROR },
/* 0F 28 /q */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /q */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
/* 0F 28 /q */ { BxPrefixSSE, BX_IA_MOVAPS_VpsWps, BxOpcodeGroupSSE_0f28 },
/* 0F 29 /q */ { BxPrefixSSE, BX_IA_MOVAPS_WpsVps, BxOpcodeGroupSSE_0f29 },
/* 0F 2A /q */ { BxPrefixSSE, BX_IA_CVTPI2PS_VpsQq, BxOpcodeGroupSSE_0f2aQ },
/* 0F 2B /q */ { BxPrefixSSE, BX_IA_MOVNTPS_MpsVps, BxOpcodeGroupSSE_0f2bM },
/* 0F 2C /q */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2cQ },
@ -1553,7 +1553,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 7C /q */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
/* 0F 7D /q */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
/* 0F 7E /q */ { BxPrefixSSE, BX_IA_MOVQ_EqPq, BxOpcodeGroupSSE_0f7eQ },
/* 0F 7F /q */ { BxPrefixSSE | BxArithDstRM, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
/* 0F 7F /q */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
/* 0F 80 /q */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jq },
/* 0F 81 /q */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jq },
/* 0F 82 /q */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JB_Jq },
@ -1693,7 +1693,7 @@ BX_CPU_C::fetchDecode64(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
unsigned b1, b2 = 0, ia_opcode = 0;
bx_bool lock=0;
unsigned offset = 512, rex_r = 0, rex_x = 0, rex_b = 0;
unsigned rm = 0, mod = 0, nnn = 0, mod_mem = 0;
unsigned rm = 0, mod = 0, nnn = 0, mod_mem = 0, rep = 0;
unsigned seg = BX_SEG_REG_DS, seg_override = BX_SEG_REG_NULL;
#define SSE_PREFIX_NONE 0
@ -1705,7 +1705,7 @@ BX_CPU_C::fetchDecode64(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
int vvv = -1;
#if BX_SUPPORT_AVX
int had_vex = 0, had_xop = 0;
int had_vex = 0, had_xop = 0, use_vvv = 0;
bx_bool vex_w = 0, vex_l = 0;
#endif
@ -1752,7 +1752,7 @@ fetch_b1:
case 0xf3: // REP/REPE/REPZ
rex_prefix = 0;
sse_prefix = (b1 & 3) ^ 1;
i->setRepUsed(b1 & 3);
rep = b1 & 3;
if (remain != 0) {
goto fetch_b1;
}
@ -1794,7 +1794,6 @@ fetch_b1:
case 0xf0: // LOCK:
rex_prefix = 0;
lock = 1;
i->assertLock();
if (remain != 0) {
goto fetch_b1;
}
@ -1854,7 +1853,6 @@ fetch_b1:
if (vex & 0x80) {
vex_w = 1;
i->assertVexW();
i->assertOs64();
i->assertOs32();
}
@ -1912,7 +1910,6 @@ fetch_b1:
if (vex & 0x80) {
vex_w = 1;
i->assertVexW();
i->assertOs64();
i->assertOs32();
}
@ -1965,13 +1962,6 @@ fetch_b1:
nnn = ((b2 >> 3) & 0x7) | rex_r;
rm = (b2 & 0x7) | rex_b;
i->setNnn(nnn);
#if BX_SUPPORT_AVX
if (had_vex == 0)
#endif
vvv = nnn;
i->setVvv(vvv);
i->setFoo((b2 | (b1 << 8)) & 0x7ff); /* for x87 */
// MOVs with CRx and DRx always use register ops and ignore the mod field.
@ -1979,15 +1969,12 @@ fetch_b1:
mod = 0xc0;
if (mod == 0xc0) { // mod == 11b
i->setRm(rm);
i->assertModC0();
goto modrm_done;
}
mod_mem = 1;
i->setRm(BX_TMP_REGISTER);
i->setSibBase(rm); // initialize with rm to use BxResolve32Base
i->setSibBase(rm); // initialize with rm to use BxResolve64Base
i->setSibIndex(BX_NIL_REGISTER);
// initialize displ32 with zero to include cases with no diplacement
i->modRMForm.displ32u = 0;
@ -2112,10 +2099,6 @@ modrm_done:
switch(group) {
case BxGroupN:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn & 0x7]);
#if BX_SUPPORT_AVX
if (had_vex == 0)
#endif
i->setVvv(rm);
break;
case BxSplitGroupN:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[(nnn & 0x7) + (mod_mem << 3)]);
@ -2151,7 +2134,7 @@ modrm_done:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[(b2 & 0x3f) + 8]);
break;
default:
BX_PANIC(("fetchdecode: Unknown opcode group %d", group));
BX_PANIC(("fetchdecode64: Unknown opcode group %d", group));
}
/* get additional attributes from group table */
@ -2170,7 +2153,6 @@ modrm_done:
#if BX_SUPPORT_AVX
if (had_vex != 0) {
i->setVvv(vvv);
if (had_vex < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
@ -2190,8 +2172,8 @@ modrm_done:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix-1]);
ia_opcode = OpcodeInfoPtr->IA;
i->setRm((b1 & 7) | rex_b);
i->setNnn((b1 >> 3) & 0x7);
rm = (b1 & 7) | rex_b;
nnn = (b1 >> 3) & 7;
}
}
@ -2200,7 +2182,7 @@ modrm_done:
if (!mod_mem || !(attr & BxLockable)) {
if (BX_CPUID_SUPPORT_CPU_EXTENSION(BX_CPU_ALT_MOV_CR8) &&
(ia_opcode == BX_IA_MOV_CR0Rq || ia_opcode == BX_IA_MOV_RqCR0)) {
i->setNnn(8); // extend CR0 -> CR8
nnn = 8; // extend CR0 -> CR8
}
else {
BX_INFO(("LOCK prefix unallowed (op1=0x%x, modrm=0x%02x)", b1, b2));
@ -2210,6 +2192,9 @@ modrm_done:
}
}
if (attr & BxRepeatable)
i->setRepUsed(rep);
unsigned imm_mode = attr & BxImmediate;
if (imm_mode) {
// make sure iptr was advanced after Ib(), Iw() and Id()
@ -2297,20 +2282,9 @@ modrm_done:
else return(-1);
}
break;
#if BX_SUPPORT_AVX
case BxImmediate_Ib4:
if (remain != 0) {
i->modRMForm.Ib = *iptr >> 4;
remain--;
}
else {
return(-1);
}
break;
#endif
default:
BX_INFO(("b1 was %x", b1));
BX_PANIC(("fetchdecode: imm_mode = %u", imm_mode));
BX_PANIC(("fetchdecode64: imm_mode = %u", imm_mode));
}
unsigned imm_mode2 = attr & BxImmediate2;
@ -2326,7 +2300,7 @@ modrm_done:
}
else {
BX_INFO(("b1 was %x", b1));
BX_PANIC(("fetchdecode: imm_mode2 = %u", imm_mode2));
BX_PANIC(("fetchdecode64: imm_mode2 = %u", imm_mode2));
}
}
}
@ -2336,6 +2310,52 @@ modrm_done:
ia_opcode = Bx3DNowOpcode[i->modRMForm.Ib];
#endif
// assign sources
for (unsigned n = 0; n <= 3; n++) {
unsigned def = (unsigned) BxOpcodesTable[ia_opcode].src[n] & 0xf;
#if BX_SUPPORT_AVX
if (def == BX_SRC_RM_VIB) {
def = (vex_w) ? BX_SRC_RM : BX_SRC_VIB;
}
else if (def == BX_SRC_VIB_RM) {
def = (vex_w) ? BX_SRC_VIB : BX_SRC_RM;
}
else if (def == BX_SRC_RM_VVV) {
def = (vex_w) ? BX_SRC_RM : BX_SRC_VVV;
}
else if (def == BX_SRC_VVV_RM) {
def = (vex_w) ? BX_SRC_VVV : BX_SRC_RM;
}
#endif
switch(def) {
case BX_SRC_EAX:
i->setSrcReg(n, 0);
break;
case BX_SRC_NNN:
i->setSrcReg(n, nnn);
break;
case BX_SRC_RM:
i->setSrcReg(n, mod_mem ? BX_TMP_REGISTER : rm);
break;
#if BX_SUPPORT_AVX
case BX_SRC_MEM_NO_VVV:
if (mod_mem) break;
// else fall through
case BX_SRC_VVV:
i->setSrcReg(n, vvv);
use_vvv = 1;
break;
case BX_SRC_VIB:
i->setSrcReg(n, i->Ib() >> 4);
break;
#endif
default:
if (def != BX_SRC_NONE)
BX_PANIC(("fetchdecode64: unknown definition %d for src %d", def, n));
}
}
// assign memory segment override
if (! BX_NULL_SEG_REG(seg_override))
seg = seg_override;
i->setSeg(seg);
@ -2343,18 +2363,20 @@ modrm_done:
i->setILen(remainingInPage - remain);
i->setIaOpcode(ia_opcode);
Bit32u op_flags = BxOpcodesTable[ia_opcode].flags;
#if BX_SUPPORT_AVX
if (had_vex > 0 || had_xop > 0) {
if (! use_vvv && vvv != 0) {
ia_opcode = BX_IA_ERROR;
}
if ((attr & BxVexW0) != 0 && vex_w) {
ia_opcode = BX_IA_ERROR;
}
if ((attr & BxVexW1) != 0 && !vex_w) {
ia_opcode = BX_IA_ERROR;
}
if ((op_flags & BX_VEX_NO_VVV) && i->vvv() != 0) {
ia_opcode = BX_IA_ERROR;
}
}
else {
BX_ASSERT(! use_vvv);
}
#endif
@ -2374,15 +2396,11 @@ modrm_done:
else {
i->execute = BxOpcodesTable[ia_opcode].execute2;
i->execute2 = NULL;
if (attr & BxArithDstRM) {
i->setRm(nnn);
i->setNnn(rm);
}
}
BX_ASSERT(i->execute);
Bit32u op_flags = BxOpcodesTable[ia_opcode].src[3];
if (! BX_CPU_THIS_PTR sse_ok) {
if (op_flags & BX_PREPARE_SSE) {
if (i->execute != &BX_CPU_C::BxError) i->execute = &BX_CPU_C::BxNoSSE;

42
bochs/cpu/fetchdecode_avx.h
View File

@ -377,13 +377,13 @@ static const BxOpcodeInfo_t BxOpcodeGroupAVX256_0f10[3] = {
};
static const BxOpcodeInfo_t BxOpcodeGroupAVX128_0f11[3] = {
/* 66 */ { BxArithDstRM, BX_IA_VMOVUPD_WpdVpd },
/* F3 */ { BxArithDstRM, BX_IA_V128_VMOVSS_WssHpsVss },
/* F2 */ { BxArithDstRM, BX_IA_V128_VMOVSD_WsdHpdVsd }
/* 66 */ { 0, BX_IA_VMOVUPD_WpdVpd },
/* F3 */ { 0, BX_IA_V128_VMOVSS_WssHpsVss },
/* F2 */ { 0, BX_IA_V128_VMOVSD_WsdHpdVsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupAVX256_0f11[3] = {
/* 66 */ { BxArithDstRM, BX_IA_VMOVUPD_WpdVpd },
/* 66 */ { 0, BX_IA_VMOVUPD_WpdVpd },
/* F3 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_ERROR }
};
@ -437,7 +437,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f28[3] = {
};
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f29[3] = {
/* 66 */ { BxArithDstRM, BX_IA_VMOVAPD_WpdVpd },
/* 66 */ { 0, BX_IA_VMOVAPD_WpdVpd },
/* F3 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_ERROR }
};
@ -611,8 +611,8 @@ static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f7e[3] = {
};
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f7f[3] = {
/* 66 */ { BxArithDstRM, BX_IA_VMOVDQA_WdqVdq },
/* F3 */ { BxArithDstRM, BX_IA_VMOVDQU_WdqVdq },
/* 66 */ { 0, BX_IA_VMOVDQA_WdqVdq },
/* F3 */ { 0, BX_IA_VMOVDQU_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
@ -760,7 +760,7 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3*2] = {
/* 0E /0 */ { 0, BX_IA_ERROR },
/* 0F /0 */ { 0, BX_IA_ERROR },
/* 10 /0 */ { BxPrefixSSE, BX_IA_VMOVUPS_VpsWps, BxOpcodeGroupAVX128_0f10 },
/* 11 /0 */ { BxPrefixSSE | BxArithDstRM, BX_IA_VMOVUPS_WpsVps, BxOpcodeGroupAVX128_0f11 },
/* 11 /0 */ { BxPrefixSSE, BX_IA_VMOVUPS_WpsVps, BxOpcodeGroupAVX128_0f11 },
/* 12 /0 */ { BxPrefixSSE, BX_IA_V128_VMOVLPS_VpsHpsMq, BxOpcodeGroupAVX128_0f12 },
/* 13 /0 */ { BxPrefixSSE, BX_IA_V128_VMOVLPS_MqVps, BxOpcodeGroupAVX128_0f13M },
/* 14 /0 */ { BxPrefixSSE, BX_IA_VUNPCKLPS_VpsHpsWps, BxOpcodeGroupAVX_0f14 },
@ -784,7 +784,7 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3*2] = {
/* 26 /0 */ { 0, BX_IA_ERROR },
/* 27 /0 */ { 0, BX_IA_ERROR },
/* 28 /0 */ { BxPrefixSSE, BX_IA_VMOVAPS_VpsWps, BxOpcodeGroupAVX_0f28 },
/* 29 /0 */ { BxPrefixSSE | BxArithDstRM, BX_IA_VMOVAPS_WpsVps, BxOpcodeGroupAVX_0f29 },
/* 29 /0 */ { BxPrefixSSE, BX_IA_VMOVAPS_WpsVps, BxOpcodeGroupAVX_0f29 },
/* 2A /0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupAVX_0f2a },
/* 2B /0 */ { BxPrefixSSE, BX_IA_VMOVNTPS_MpsVps, BxOpcodeGroupAVX_0f2bM },
/* 2C /0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupAVX_0f2c },
@ -957,7 +957,7 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3*2] = {
/* D3 /0 */ { BxPrefixSSE66, BX_IA_V128_VPSRLQ_VdqHdqWdq },
/* D4 /0 */ { BxPrefixSSE66, BX_IA_V128_VPADDQ_VdqHdqWdq },
/* D5 /0 */ { BxPrefixSSE66, BX_IA_V128_VPMULLW_VdqHdqWdq },
/* D6 /0 */ { BxPrefixSSE66 | BxArithDstRM, BX_IA_VMOVQ_WqVq },
/* D6 /0 */ { BxPrefixSSE66, BX_IA_VMOVQ_WqVq },
/* D7 /0 */ { BxPrefixSSE66, BX_IA_V128_VPMOVMSKB_GdUdq },
/* D8 /0 */ { BxPrefixSSE66, BX_IA_V128_VPSUBUSB_VdqHdqWdq },
/* D9 /0 */ { BxPrefixSSE66, BX_IA_V128_VPSUBUSW_VdqHdqWdq },
@ -1221,10 +1221,10 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3*2] = {
/* D9 /0 */ { 0, BX_IA_ERROR },
/* DA /0 */ { 0, BX_IA_ERROR },
/* DB /0 */ { BxPrefixSSE66, BX_IA_V128_VAESIMC_VdqWdq },
/* DC /0 */ { BxPrefixSSE66, BX_IA_V128_VAESENC_VdqWdq },
/* DD /0 */ { BxPrefixSSE66, BX_IA_V128_VAESENCLAST_VdqWdq },
/* DE /0 */ { BxPrefixSSE66, BX_IA_V128_VAESDEC_VdqWdq },
/* DF /0 */ { BxPrefixSSE66, BX_IA_V128_VAESDECLAST_VdqWdq },
/* DC /0 */ { BxPrefixSSE66, BX_IA_V128_VAESENC_VdqHdqWdq },
/* DD /0 */ { BxPrefixSSE66, BX_IA_V128_VAESENCLAST_VdqHdqWdq },
/* DE /0 */ { BxPrefixSSE66, BX_IA_V128_VAESDEC_VdqHdqWdq },
/* DF /0 */ { BxPrefixSSE66, BX_IA_V128_VAESDECLAST_VdqHdqWdq },
/* E0 /0 */ { 0, BX_IA_ERROR },
/* E1 /0 */ { 0, BX_IA_ERROR },
/* E2 /0 */ { 0, BX_IA_ERROR },
@ -1327,12 +1327,12 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3*2] = {
/* 41 /0 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VDPPD_VpdHpdWpdIb },
/* 42 /0 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V128_VMPSADBW_VdqWdqIb },
/* 43 /0 */ { 0, BX_IA_ERROR },
/* 44 /0 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V128_VPCLMULQDQ_VdqWdqIb },
/* 44 /0 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V128_VPCLMULQDQ_VdqHdqWdqIb },
/* 45 /0 */ { 0, BX_IA_ERROR },
/* 46 /0 */ { 0, BX_IA_ERROR },
/* 47 /0 */ { 0, BX_IA_ERROR },
/* 48 /0 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VPERMIL2PS_VdqHdqWdqIb },
/* 49 /0 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VPERMIL2PD_VdqHdqWdqIb },
/* 48 /0 */ { BxPrefixSSE66 | BxImmediate_Ib5, BX_IA_VPERMIL2PS_VdqHdqWdqIb },
/* 49 /0 */ { BxPrefixSSE66 | BxImmediate_Ib5, BX_IA_VPERMIL2PD_VdqHdqWdqIb },
/* 4A /0 */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_VBLENDVPS_VpsHpsWpsIb },
/* 4B /0 */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_VBLENDVPD_VpdHpdWpdIb },
/* 4C /0 */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_V128_VPBLENDVB_VdqHdqWdqIb },
@ -1534,7 +1534,7 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3*2] = {
/* 0E /1 */ { 0, BX_IA_ERROR },
/* 0F /1 */ { 0, BX_IA_ERROR },
/* 10 /1 */ { BxPrefixSSE, BX_IA_VMOVUPS_VpsWps, BxOpcodeGroupAVX256_0f10 },
/* 11 /1 */ { BxPrefixSSE | BxArithDstRM, BX_IA_VMOVUPS_WpsVps, BxOpcodeGroupAVX256_0f11 },
/* 11 /1 */ { BxPrefixSSE, BX_IA_VMOVUPS_WpsVps, BxOpcodeGroupAVX256_0f11 },
/* 12 /1 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupAVX256_0f12 },
/* 13 /1 */ { 0, BX_IA_ERROR },
/* 14 /1 */ { BxPrefixSSE, BX_IA_VUNPCKLPS_VpsHpsWps, BxOpcodeGroupAVX_0f14 },
@ -1558,7 +1558,7 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3*2] = {
/* 26 /1 */ { 0, BX_IA_ERROR },
/* 27 /1 */ { 0, BX_IA_ERROR },
/* 28 /1 */ { BxPrefixSSE, BX_IA_VMOVAPS_VpsWps, BxOpcodeGroupAVX_0f28 },
/* 29 /1 */ { BxPrefixSSE | BxArithDstRM, BX_IA_VMOVAPS_WpsVps, BxOpcodeGroupAVX_0f29 },
/* 29 /1 */ { BxPrefixSSE, BX_IA_VMOVAPS_WpsVps, BxOpcodeGroupAVX_0f29 },
/* 2A /1 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupAVX_0f2a },
/* 2B /1 */ { BxPrefixSSE, BX_IA_VMOVNTPS_MpsVps, BxOpcodeGroupAVX_0f2bM },
/* 2C /1 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupAVX_0f2c },
@ -2105,8 +2105,8 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3*2] = {
/* 45 /1 */ { 0, BX_IA_ERROR },
/* 46 /1 */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib, BX_IA_V256_VPERM2I128_VdqHdqWdqIb },
/* 47 /1 */ { 0, BX_IA_ERROR },
/* 48 /1 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VPERMIL2PS_VdqHdqWdqIb },
/* 49 /1 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VPERMIL2PD_VdqHdqWdqIb },
/* 48 /1 */ { BxPrefixSSE66 | BxImmediate_Ib5, BX_IA_VPERMIL2PS_VdqHdqWdqIb },
/* 49 /1 */ { BxPrefixSSE66 | BxImmediate_Ib5, BX_IA_VPERMIL2PD_VdqHdqWdqIb },
/* 4A /1 */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_VBLENDVPS_VpsHpsWpsIb },
/* 4B /1 */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_VBLENDVPD_VpdHpdWpdIb },
/* 4C /1 */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_V256_VPBLENDVB_VdqHdqWdqIb },

18
bochs/cpu/fetchdecode_sse.h
View File

@ -110,9 +110,9 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f10[3] = {
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f11[3] = {
/* 66 */ { BxArithDstRM, BX_IA_MOVUPD_WpdVpd },
/* F3 */ { BxArithDstRM, BX_IA_MOVSS_WssVss },
/* F2 */ { BxArithDstRM, BX_IA_MOVSD_WsdVsd }
/* 66 */ { 0, BX_IA_MOVUPD_WpdVpd },
/* F3 */ { 0, BX_IA_MOVSS_WssVss },
/* F2 */ { 0, BX_IA_MOVSD_WsdVsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f12[3] = {
@ -158,7 +158,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f28[3] = {
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f29[3] = {
/* 66 */ { BxArithDstRM, BX_IA_MOVAPD_WpdVpd },
/* 66 */ { 0, BX_IA_MOVAPD_WpdVpd },
/* F3 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_ERROR }
};
@ -462,8 +462,8 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7eQ[3] = {
#endif
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7f[3] = {
/* 66 */ { BxArithDstRM, BX_IA_MOVDQA_WdqVdq },
/* F3 */ { BxArithDstRM, BX_IA_MOVDQU_WdqVdq },
/* 66 */ { 0, BX_IA_MOVDQA_WdqVdq },
/* F3 */ { 0, BX_IA_MOVDQU_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
@ -528,9 +528,9 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fd5[3] = {
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fd6[3] = {
/* 66 */ { BxArithDstRM, BX_IA_MOVQ_WqVq },
/* F3 */ { 0, BX_IA_MOVQ2DQ_VdqQq },
/* F2 */ { 0, BX_IA_MOVDQ2Q_PqVRq }
/* 66 */ { 0, BX_IA_MOVQ_WqVq },
/* F3 */ { 0, BX_IA_MOVQ2DQ_VdqQq },
/* F2 */ { 0, BX_IA_MOVDQ2Q_PqVRq }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fd7R[3] = {

20
bochs/cpu/gather.cc
View File

@ -60,12 +60,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERDPS_VpsHps(bxInstruction_c
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == i->vvv() || i->sibIndex() == i->nnn() || i->vvv() == i->nnn()) {
if (i->sibIndex() == i->src2() || i->sibIndex() == i->dst() || i->src2() == i->dst()) {
BX_ERROR(("VGATHERDPS_VpsHps: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
BxPackedAvxRegister *mask = &BX_AVX_REG(i->vvv()), *dest = &BX_AVX_REG(i->nnn());
BxPackedAvxRegister *mask = &BX_AVX_REG(i->src2()), *dest = &BX_AVX_REG(i->dst());
// index size = 32, element_size = 32, max vector size = 256
// num_elements:
@ -110,7 +110,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERQPS_VpsHps(bxInstruction_c
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == i->vvv() || i->sibIndex() == i->nnn() || i->vvv() == i->nnn()) {
if (i->sibIndex() == i->src2() || i->sibIndex() == i->dst() || i->src2() == i->dst()) {
BX_ERROR(("VGATHERQPS_VpsHps: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
@ -120,7 +120,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERQPS_VpsHps(bxInstruction_c
// 128 bit => 2
// 256 bit => 4
BxPackedAvxRegister *mask = &BX_AVX_REG(i->vvv()), *dest = &BX_AVX_REG(i->nnn());
BxPackedAvxRegister *mask = &BX_AVX_REG(i->src2()), *dest = &BX_AVX_REG(i->dst());
unsigned n, num_elements = 2 * i->getVL();
for (n=0; n < num_elements; n++) {
@ -144,8 +144,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERQPS_VpsHps(bxInstruction_c
mask->avx32u(n) = 0;
}
BX_CLEAR_AVX_HIGH(i->vvv());
BX_CLEAR_AVX_HIGH(i->nnn());
BX_CLEAR_AVX_HIGH(i->dst());
BX_CLEAR_AVX_HIGH(i->src2());
BX_NEXT_INSTR(i);
}
@ -162,7 +162,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERDPD_VpdHpd(bxInstruction_c
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == i->vvv() || i->sibIndex() == i->nnn() || i->vvv() == i->nnn()) {
if (i->sibIndex() == i->src2() || i->sibIndex() == i->dst() || i->src2() == i->dst()) {
BX_ERROR(("VGATHERDPD_VpdHpd: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
@ -172,7 +172,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERDPD_VpdHpd(bxInstruction_c
// 128 bit => 2
// 256 bit => 4
BxPackedAvxRegister *mask = &BX_AVX_REG(i->vvv()), *dest = &BX_AVX_REG(i->nnn());
BxPackedAvxRegister *mask = &BX_AVX_REG(i->src2()), *dest = &BX_AVX_REG(i->dst());
unsigned n, num_elements = 2 * i->getVL();
for (n=0; n < num_elements; n++) {
@ -211,7 +211,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERQPD_VpdHpd(bxInstruction_c
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == i->vvv() || i->sibIndex() == i->nnn() || i->vvv() == i->nnn()) {
if (i->sibIndex() == i->src2() || i->sibIndex() == i->dst() || i->src2() == i->dst()) {
BX_ERROR(("VGATHERQPD_VpdHpd: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
@ -221,7 +221,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERQPD_VpdHpd(bxInstruction_c
// 128 bit => 2
// 256 bit => 4
BxPackedAvxRegister *mask = &BX_AVX_REG(i->vvv()), *dest = &BX_AVX_REG(i->nnn());
BxPackedAvxRegister *mask = &BX_AVX_REG(i->src2()), *dest = &BX_AVX_REG(i->dst());
unsigned n, num_elements = 2 * i->getVL();
for (n=0; n < num_elements; n++) {

3975
bochs/cpu/ia_opcodes.h
View File

File diff suppressed because it is too large Load Diff

93
bochs/cpu/instr.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2011 Stanislav Shwartsman
// Copyright (c) 2008-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -102,15 +102,15 @@ public:
BxResolvePtr_tR ResolveModrm;
struct {
// 15..12 (unused)
// 11...0 opcode
// 15...0 opcode
Bit16u ia_opcode;
// 7...4 (unused)
// 3...0 ilen (0..15)
Bit8u ilen;
// 7...6 repUsed (0=none, 2=0xF2, 3=0xF3)
// 7...6 VEX Vector Length (0=no VL, 1=128 bit, 2=256 bit)
// repUsed (0=none, 2=0xF2, 3=0xF3)
// 5...5 extend8bit
// 4...4 mod==c0 (modrm)
// 3...3 os64
@ -120,21 +120,14 @@ public:
Bit8u metaInfo1;
} metaInfo;
// METADATA FLAGS:
// 7...4 (unused)
// 3...3 lock prefix
// 2...2 VEX.W
// 1...0 VEX Vector Length (0=no VL, 1=128 bit, 2=256 bit)
#define BX_INSTR_METADATA_NNN 0
#define BX_INSTR_METADATA_RM 1
#define BX_INSTR_METADATA_SEG 2
#define BX_INSTR_METADATA_BASE 3
#define BX_INSTR_METADATA_INDEX 4
#define BX_INSTR_METADATA_SCALE 5
#define BX_INSTR_METADATA_VVV 6
#define BX_INSTR_METADATA_FLAGS 7
#define BX_INSTR_METADATA_DST 0
#define BX_INSTR_METADATA_SRC1 1
#define BX_INSTR_METADATA_SRC2 2
#define BX_INSTR_METADATA_SRC3 3
#define BX_INSTR_METADATA_SEG 4
#define BX_INSTR_METADATA_BASE 5
#define BX_INSTR_METADATA_INDEX 6
#define BX_INSTR_METADATA_SCALE 7
// using 5-bit field for registers (16 regs in 64-bit, RIP, NIL)
Bit8u metaData[8];
@ -193,18 +186,6 @@ public:
return modRMForm.Iw >> 8;
}
BX_CPP_INLINE void setNnn(unsigned nnn) {
metaData[BX_INSTR_METADATA_NNN] = nnn;
}
BX_CPP_INLINE unsigned nnn() const {
return metaData[BX_INSTR_METADATA_NNN];
}
BX_CPP_INLINE void setRm(unsigned rm) {
metaData[BX_INSTR_METADATA_RM] = rm;
}
BX_CPP_INLINE unsigned rm() const {
return metaData[BX_INSTR_METADATA_RM];
}
BX_CPP_INLINE void setSibScale(unsigned scale) {
metaData[BX_INSTR_METADATA_SCALE] = scale;
}
@ -241,8 +222,7 @@ public:
// code, when a strict 0 or 1 is not necessary.
BX_CPP_INLINE void init(unsigned os32, unsigned as32, unsigned os64, unsigned as64)
{
metaInfo.metaInfo1 = (os32<<2) | (os64<<3) | (as32<<0) | (as64<<1);
metaData[BX_INSTR_METADATA_FLAGS] = 0; // clear VEX.W and VEX.VL
metaInfo.metaInfo1 = (os32<<2) | (os64<<3) | (as32<<0) | (as64<<1); // VL = 0
}
BX_CPP_INLINE unsigned os32L(void) const {
@ -330,33 +310,34 @@ public:
BX_CPP_INLINE unsigned getVL(void) const {
#if BX_SUPPORT_AVX
return metaData[BX_INSTR_METADATA_FLAGS] & 0x3;
return metaInfo.metaInfo1 >> 6;
#else
return 0;
#endif
}
BX_CPP_INLINE void setVL(unsigned value) {
metaData[BX_INSTR_METADATA_FLAGS] = (metaData[BX_INSTR_METADATA_FLAGS] & ~0x3) | (value & 0x3);
metaInfo.metaInfo1 = (metaInfo.metaInfo1 & 0x3f) | (value << 6);
}
#if BX_SUPPORT_AVX
BX_CPP_INLINE unsigned getVexW(void) const {
return metaData[BX_INSTR_METADATA_FLAGS] & (1<<2);
BX_CPP_INLINE void setSrcReg(unsigned src, unsigned reg) {
metaData[src] = reg;
}
BX_CPP_INLINE void setVexW(unsigned bit) {
metaData[BX_INSTR_METADATA_FLAGS] = (metaData[BX_INSTR_METADATA_FLAGS] & ~(1<<2)) | (bit<<2);
}
BX_CPP_INLINE void assertVexW(void) {
metaData[BX_INSTR_METADATA_FLAGS] |= (1<<2);
}
#endif
BX_CPP_INLINE void setVvv(unsigned vvv) {
metaData[BX_INSTR_METADATA_VVV] = vvv;
BX_CPP_INLINE unsigned dst() const {
return metaData[BX_INSTR_METADATA_DST];
}
BX_CPP_INLINE unsigned vvv() const {
return metaData[BX_INSTR_METADATA_VVV];
BX_CPP_INLINE unsigned src1() const {
return metaData[BX_INSTR_METADATA_SRC1];
}
BX_CPP_INLINE unsigned src2() const {
return metaData[BX_INSTR_METADATA_SRC2];
}
BX_CPP_INLINE unsigned src3() const {
return metaData[BX_INSTR_METADATA_SRC3];
}
BX_CPP_INLINE unsigned src() const { return src1(); }
BX_CPP_INLINE unsigned modC0() const
{
@ -368,21 +349,11 @@ public:
BX_CPP_INLINE void assertModC0()
{
metaInfo.metaInfo1 |= (1<<4);
}
BX_CPP_INLINE unsigned lock() const
{
return metaData[BX_INSTR_METADATA_FLAGS] & (1<<3);
}
BX_CPP_INLINE void assertLock()
{
metaData[BX_INSTR_METADATA_FLAGS] |= (1<<3);
}
};
}};
// <TAG-CLASS-INSTRUCTION-END>
enum {
#define bx_define_opcode(a, b, c, d, e) a,
#define bx_define_opcode(a, b, c, d, s1, s2, s3, s4, e) a,
#include "ia_opcodes.h"
BX_IA_LAST
};

99
bochs/cpu/logical16.cc
View File

@ -31,7 +31,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->src());
op1_16 ^= op2_16;
write_RMW_virtual_word(op1_16);
@ -44,10 +44,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GwEwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->rm());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = BX_READ_16BIT_REG(i->src());
op1_16 ^= op2_16;
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
@ -60,26 +60,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GwEwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = read_virtual_word(i->seg(), eaddr);
op1_16 ^= op2_16;
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_AXIw(bxInstruction_c *i)
{
Bit16u op_16 = AX ^ i->Iw();
AX = op_16;
SET_FLAGS_OSZAPC_LOGIC_16(op_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwIwM(bxInstruction_c *i)
{
Bit16u op1_16;
@ -97,9 +87,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwIwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwIwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
op1_16 ^= i->Iw();
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
@ -123,9 +113,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EwIwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EwIwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
op1_16 |= i->Iw();
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
@ -145,9 +135,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
op1_16 = ~op1_16;
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
BX_NEXT_INSTR(i);
}
@ -159,7 +149,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->src());
op1_16 |= op2_16;
write_RMW_virtual_word(op1_16);
@ -172,10 +162,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GwEwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->rm());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = BX_READ_16BIT_REG(i->src());
op1_16 |= op2_16;
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
@ -188,26 +178,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GwEwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = read_virtual_word(i->seg(), eaddr);
op1_16 |= op2_16;
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_AXIw(bxInstruction_c *i)
{
Bit16u op_16 = AX | i->Iw();
AX = op_16;
SET_FLAGS_OSZAPC_LOGIC_16(op_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
@ -215,7 +195,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->src());
op1_16 &= op2_16;
write_RMW_virtual_word(op1_16);
@ -228,10 +208,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GwEwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->rm());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = BX_READ_16BIT_REG(i->src());
op1_16 &= op2_16;
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
@ -244,26 +224,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GwEwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = read_virtual_word(i->seg(), eaddr);
op1_16 &= op2_16;
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_AXIw(bxInstruction_c *i)
{
Bit16u op_16 = AX & i->Iw();
AX = op_16;
SET_FLAGS_OSZAPC_LOGIC_16(op_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwIwM(bxInstruction_c *i)
{
Bit16u op1_16;
@ -281,9 +251,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwIwM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwIwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
op1_16 &= i->Iw();
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
@ -294,8 +264,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwR(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op1_16 = BX_READ_16BIT_REG(i->dst());
op2_16 = BX_READ_16BIT_REG(i->src());
op1_16 &= op2_16;
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
@ -309,25 +279,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = read_virtual_word(i->seg(), eaddr);
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->src());
op1_16 &= op2_16;
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_AXIw(bxInstruction_c *i)
{
Bit16u op_16 = AX & i->Iw();
SET_FLAGS_OSZAPC_LOGIC_16(op_16);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwIwR(bxInstruction_c *i)
{
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
op1_16 &= i->Iw();
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);

99
bochs/cpu/logical32.cc
View File

@ -31,7 +31,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
op1_32 ^= op2_32;
write_RMW_virtual_dword(op1_32);
@ -44,10 +44,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
op1_32 ^= op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
@ -60,26 +60,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GdEdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = read_virtual_dword(i->seg(), eaddr);
op1_32 ^= op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EAXId(bxInstruction_c *i)
{
Bit32u op_32 = EAX ^ i->Id();
RAX = op_32;
SET_FLAGS_OSZAPC_LOGIC_32(op_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdIdM(bxInstruction_c *i)
{
Bit32u op1_32;
@ -97,9 +87,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdIdM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdIdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
op1_32 ^= i->Id();
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
@ -123,9 +113,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EdIdM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EdIdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
op1_32 |= i->Id();
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
@ -145,9 +135,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EdM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
op1_32 = ~op1_32;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
@ -159,7 +149,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
op1_32 |= op2_32;
write_RMW_virtual_dword(op1_32);
@ -172,10 +162,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
op1_32 |= op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
@ -188,26 +178,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GdEdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = read_virtual_dword(i->seg(), eaddr);
op1_32 |= op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EAXId(bxInstruction_c *i)
{
Bit32u op_32 = EAX | i->Id();
RAX = op_32;
SET_FLAGS_OSZAPC_LOGIC_32(op_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdGdM(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
@ -215,7 +195,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
op1_32 &= op2_32;
write_RMW_virtual_dword(op1_32);
@ -228,10 +208,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
op1_32 &= op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
@ -244,26 +224,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GdEdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = read_virtual_dword(i->seg(), eaddr);
op1_32 &= op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EAXId(bxInstruction_c *i)
{
Bit32u op_32 = EAX & i->Id();
RAX = op_32;
SET_FLAGS_OSZAPC_LOGIC_32(op_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdIdM(bxInstruction_c *i)
{
Bit32u op1_32;
@ -281,9 +251,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdIdM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdIdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
op1_32 &= i->Id();
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
@ -294,8 +264,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
op1_32 &= op2_32;
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
@ -310,7 +280,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->src());
op1_32 &= op2_32;
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
@ -318,18 +288,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdM(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
{
Bit32u op_32 = EAX & i->Id();
SET_FLAGS_OSZAPC_LOGIC_32(op_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdIdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
op1_32 &= i->Id();
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);

117
bochs/cpu/logical64.cc
View File

@ -33,7 +33,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EqGqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 ^= op2_64;
write_RMW_virtual_qword(op1_64);
@ -46,11 +46,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 ^= op2_64;
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -63,26 +63,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GqEqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
op1_64 ^= op2_64;
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_RAXId(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
op1_64 ^= op2_64;
RAX = op1_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -108,9 +93,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64 = (Bit32s) i->Id();
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op1_64 ^= op2_64;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -136,9 +121,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64 = (Bit32s) i->Id();
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op1_64 |= op2_64;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -158,9 +143,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EqM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EqR(bxInstruction_c *i)
{
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
op1_64 = ~op1_64;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
@ -172,7 +157,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EqGqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 |= op2_64;
write_RMW_virtual_qword(op1_64);
@ -185,11 +170,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 |= op2_64;
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -202,26 +187,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GqEqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
op1_64 |= op2_64;
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_RAXId(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
op1_64 |= op2_64;
RAX = op1_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -235,7 +205,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EqGqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 &= op2_64;
write_RMW_virtual_qword(op1_64);
@ -248,11 +218,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GqEqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 &= op2_64;
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -265,25 +235,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GqEqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = read_virtual_qword_64(i->seg(), eaddr);
op1_64 &= op2_64;
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_RAXId(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
op1_64 &= op2_64;
RAX = op1_64;
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -309,9 +265,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64 = (Bit32s) i->Id();
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op1_64 &= op2_64;
BX_WRITE_64BIT_REG(i->rm(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -322,8 +278,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqGqR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 &= op2_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -338,20 +294,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqGqM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_virtual_qword_64(i->seg(), eaddr);
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 &= op2_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_RAXId(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = RAX;
op2_64 = (Bit32s) i->Id();
op2_64 = BX_READ_64BIT_REG(i->src());
op1_64 &= op2_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
@ -363,7 +306,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EqIdR(bxInstruction_c *i)
{
Bit64u op1_64, op2_64;
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = (Bit32s) i->Id();
op1_64 &= op2_64;

99
bochs/cpu/logical8.cc
View File

@ -31,7 +31,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = read_RMW_virtual_byte(i->seg(), eaddr);
op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
op1 ^= op2;
write_RMW_virtual_byte(op1);
@ -44,10 +44,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GbEbR(bxInstruction_c *i)
{
Bit8u op1, op2;
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
op1 ^= op2;
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_LOGIC_8(op1);
@ -60,26 +60,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GbEbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op2 = read_virtual_byte(i->seg(), eaddr);
op1 ^= op2;
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_LOGIC_8(op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_ALIb(bxInstruction_c *i)
{
Bit8u op_8 = AL ^ i->Ib();
AL = op_8;
SET_FLAGS_OSZAPC_LOGIC_8(op_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EbIbM(bxInstruction_c *i)
{
Bit8u op1, op2 = i->Ib();
@ -99,9 +89,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EbIbR(bxInstruction_c *i)
{
Bit8u op1, op2 = i->Ib();
op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op1 ^= op2;
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_LOGIC_8(op1);
@ -127,9 +117,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EbIbR(bxInstruction_c *i)
{
Bit8u op1, op2 = i->Ib();
op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op1 |= op2;
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_LOGIC_8(op1);
@ -149,9 +139,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EbR(bxInstruction_c *i)
{
Bit8u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op1_8 = ~op1_8;
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op1_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1_8);
BX_NEXT_INSTR(i);
}
@ -163,7 +153,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = read_RMW_virtual_byte(i->seg(), eaddr);
op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
op1 |= op2;
write_RMW_virtual_byte(op1);
@ -176,10 +166,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GbEbR(bxInstruction_c *i)
{
Bit8u op1, op2;
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
op1 |= op2;
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_LOGIC_8(op1);
@ -192,26 +182,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GbEbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op2 = read_virtual_byte(i->seg(), eaddr);
op1 |= op2;
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_LOGIC_8(op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_ALIb(bxInstruction_c *i)
{
Bit8u op_8 = AL | i->Ib();
AL = op_8;
SET_FLAGS_OSZAPC_LOGIC_8(op_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EbGbM(bxInstruction_c *i)
{
Bit8u op1, op2;
@ -219,7 +199,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = read_RMW_virtual_byte(i->seg(), eaddr);
op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
op1 &= op2;
write_RMW_virtual_byte(op1);
@ -232,10 +212,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GbEbR(bxInstruction_c *i)
{
Bit8u op1, op2;
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
op1 &= op2;
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_LOGIC_8(op1);
@ -248,26 +228,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GbEbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op2 = read_virtual_byte(i->seg(), eaddr);
op1 &= op2;
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_LOGIC_8(op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_ALIb(bxInstruction_c *i)
{
Bit8u op_8 = AL & i->Ib();
AL = op_8;
SET_FLAGS_OSZAPC_LOGIC_8(op_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EbIbM(bxInstruction_c *i)
{
Bit8u op1, op2 = i->Ib();
@ -287,9 +257,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EbIbR(bxInstruction_c *i)
{
Bit8u op1, op2 = i->Ib();
op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op1 &= op2;
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op1);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), op1);
SET_FLAGS_OSZAPC_LOGIC_8(op1);
@ -300,8 +270,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbGbR(bxInstruction_c *i)
{
Bit8u op1, op2;
op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
op1 &= op2;
SET_FLAGS_OSZAPC_LOGIC_8(op1);
@ -316,7 +286,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbGbM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1 = read_virtual_byte(i->seg(), eaddr);
op2 = BX_READ_8BIT_REGx(i->nnn(), i->extend8bitL());
op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
op1 &= op2;
SET_FLAGS_OSZAPC_LOGIC_8(op1);
@ -324,18 +294,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbGbM(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_ALIb(bxInstruction_c *i)
{
Bit8u op_8 = AL & i->Ib();
SET_FLAGS_OSZAPC_LOGIC_8(op_8);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EbIbR(bxInstruction_c *i)
{
Bit8u op1 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op1 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
op1 &= i->Ib();
SET_FLAGS_OSZAPC_LOGIC_8(op1);

500
bochs/cpu/mmx.cc
View File

File diff suppressed because it is too large Load Diff

20
bochs/cpu/mult16.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -27,7 +27,7 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_AXEwR(bxInstruction_c *i)
{
Bit16u op1_16 = AX;
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
Bit32u product_32 = ((Bit32u) op1_16) * ((Bit32u) op2_16);
Bit16u product_16l = (product_32 & 0xFFFF);
@ -50,7 +50,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_AXEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_AXEwR(bxInstruction_c *i)
{
Bit16s op1_16 = AX;
Bit16s op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16s op2_16 = BX_READ_16BIT_REG(i->src());
Bit32s product_32 = ((Bit32s) op1_16) * ((Bit32s) op2_16);
Bit16u product_16l = (product_32 & 0xFFFF);
@ -75,7 +75,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_AXEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIV_AXEwR(bxInstruction_c *i)
{
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
if (op2_16 == 0)
exception(BX_DE_EXCEPTION, 0);
@ -103,7 +103,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IDIV_AXEwR(bxInstruction_c *i)
if (op1_32 == ((Bit32s)0x80000000))
exception(BX_DE_EXCEPTION, 0);
Bit16s op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16s op2_16 = BX_READ_16BIT_REG(i->src());
if (op2_16 == 0)
exception(BX_DE_EXCEPTION, 0);
@ -124,14 +124,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IDIV_AXEwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GwEwIwR(bxInstruction_c *i)
{
Bit16s op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16s op2_16 = BX_READ_16BIT_REG(i->src());
Bit16s op3_16 = i->Iw();
Bit32s product_32 = op2_16 * op3_16;
Bit16u product_16 = (product_32 & 0xFFFF);
/* now write product back to destination */
BX_WRITE_16BIT_REG(i->nnn(), product_16);
BX_WRITE_16BIT_REG(i->dst(), product_16);
/* set eflags:
* IMUL r16,r/m16,imm16: condition for clearing CF & OF:
@ -148,14 +148,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GwEwIwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GwEwR(bxInstruction_c *i)
{
Bit16s op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit16s op2_16 = BX_READ_16BIT_REG(i->rm());
Bit16s op1_16 = BX_READ_16BIT_REG(i->dst());
Bit16s op2_16 = BX_READ_16BIT_REG(i->src());
Bit32s product_32 = op1_16 * op2_16;
Bit16u product_16 = (product_32 & 0xFFFF);
/* now write product back to destination */
BX_WRITE_16BIT_REG(i->nnn(), product_16);
BX_WRITE_16BIT_REG(i->dst(), product_16);
/* set eflags:
* IMUL r16,r/m16: condition for clearing CF & OF:

20
bochs/cpu/mult32.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -27,7 +27,7 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_EAXEdR(bxInstruction_c *i)
{
Bit32u op1_32 = EAX;
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
Bit64u product_64 = ((Bit64u) op1_32) * ((Bit64u) op2_32);
Bit32u product_32l = GET32L(product_64);
@ -50,7 +50,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_EAXEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_EAXEdR(bxInstruction_c *i)
{
Bit32s op1_32 = EAX;
Bit32s op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32s op2_32 = BX_READ_32BIT_REG(i->src());
Bit64s product_64 = ((Bit64s) op1_32) * ((Bit64s) op2_32);
Bit32u product_32l = GET32L(product_64);
@ -75,7 +75,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_EAXEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIV_EAXEdR(bxInstruction_c *i)
{
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
if (op2_32 == 0) {
exception(BX_DE_EXCEPTION, 0);
}
@ -110,7 +110,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IDIV_EAXEdR(bxInstruction_c *i)
if (op1_64 == ((Bit64s)BX_CONST64(0x8000000000000000)))
exception(BX_DE_EXCEPTION, 0);
Bit32s op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32s op2_32 = BX_READ_32BIT_REG(i->src());
if (op2_32 == 0)
exception(BX_DE_EXCEPTION, 0);
@ -137,14 +137,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IDIV_EAXEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GdEdIdR(bxInstruction_c *i)
{
Bit32s op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32s op2_32 = BX_READ_32BIT_REG(i->src());
Bit32s op3_32 = i->Id();
Bit64s product_64 = ((Bit64s) op2_32) * ((Bit64s) op3_32);
Bit32u product_32 = (Bit32u)(product_64 & 0xFFFFFFFF);
/* now write product back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), product_32);
BX_WRITE_32BIT_REGZ(i->dst(), product_32);
/* set eflags:
* IMUL r32,r/m32,imm32: condition for clearing CF & OF:
@ -161,14 +161,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GdEdIdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GdEdR(bxInstruction_c *i)
{
Bit32s op1_32 = BX_READ_32BIT_REG(i->nnn());
Bit32s op2_32 = BX_READ_32BIT_REG(i->rm());
Bit32s op1_32 = BX_READ_32BIT_REG(i->dst());
Bit32s op2_32 = BX_READ_32BIT_REG(i->src());
Bit64s product_64 = ((Bit64s) op1_32) * ((Bit64s) op2_32);
Bit32u product_32 = (Bit32u)(product_64 & 0xFFFFFFFF);
/* now write product back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), product_32);
BX_WRITE_32BIT_REGZ(i->dst(), product_32);
/* set eflags:
* IMUL r32,r/m32: condition for clearing CF & OF:

20
bochs/cpu/mult64.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -204,7 +204,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_RAXEqR(bxInstruction_c *i)
Bit128u product_128;
Bit64u op1_64 = RAX;
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
// product_128 = ((Bit128u) op1_64) * ((Bit128u) op2_64);
// product_64l = (Bit64u) (product_128 & 0xFFFFFFFFFFFFFFFF);
@ -231,7 +231,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_RAXEqR(bxInstruction_c *i)
Bit128s product_128;
Bit64s op1_64 = RAX;
Bit64s op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64s op2_64 = BX_READ_64BIT_REG(i->src());
// product_128 = ((Bit128s) op1_64) * ((Bit128s) op2_64);
// product_64l = (Bit64u) (product_128 & 0xFFFFFFFFFFFFFFFF);
@ -263,7 +263,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIV_RAXEqR(bxInstruction_c *i)
Bit64u remainder_64, quotient_64l;
Bit128u op1_128, quotient_128;
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
if (op2_64 == 0) {
exception(BX_DE_EXCEPTION, 0);
}
@ -304,7 +304,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IDIV_RAXEqR(bxInstruction_c *i)
if ((op1_128.hi == (Bit64s) BX_CONST64(0x8000000000000000)) && (!op1_128.lo))
exception(BX_DE_EXCEPTION, 0);
Bit64s op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64s op2_64 = BX_READ_64BIT_REG(i->src());
if (op2_64 == 0) {
exception(BX_DE_EXCEPTION, 0);
@ -338,13 +338,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GqEqIdR(bxInstruction_c *i)
{
Bit128s product_128;
Bit64s op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64s op1_64 = BX_READ_64BIT_REG(i->src());
Bit64s op2_64 = (Bit32s) i->Id();
long_imul(&product_128,op1_64,op2_64);
/* now write product back to destination */
BX_WRITE_64BIT_REG(i->nnn(), product_128.lo);
BX_WRITE_64BIT_REG(i->dst(), product_128.lo);
SET_FLAGS_OSZAPC_LOGIC_64(product_128.lo);
@ -359,13 +359,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GqEqR(bxInstruction_c *i)
{
Bit128s product_128;
Bit64s op1_64 = BX_READ_64BIT_REG(i->nnn());
Bit64s op2_64 = BX_READ_64BIT_REG(i->rm());
Bit64s op1_64 = BX_READ_64BIT_REG(i->dst());
Bit64s op2_64 = BX_READ_64BIT_REG(i->src());
long_imul(&product_128,op1_64,op2_64);
/* now write product back to destination */
BX_WRITE_64BIT_REG(i->nnn(), product_128.lo);
BX_WRITE_64BIT_REG(i->dst(), product_128.lo);
SET_FLAGS_OSZAPC_LOGIC_64(product_128.lo);

10
bochs/cpu/mult8.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -27,7 +27,7 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_ALEbR(bxInstruction_c *i)
{
Bit8u op1 = AL;
Bit8u op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit32u product_16 = ((Bit16u) op1) * ((Bit16u) op2);
@ -50,7 +50,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_ALEbR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_ALEbR(bxInstruction_c *i)
{
Bit8s op1 = AL;
Bit8s op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8s op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
Bit16s product_16 = op1 * op2;
Bit8u product_8 = (product_16 & 0xFF);
@ -74,7 +74,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_ALEbR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIV_ALEbR(bxInstruction_c *i)
{
Bit8u op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
if (op2 == 0) {
exception(BX_DE_EXCEPTION, 0);
}
@ -105,7 +105,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IDIV_ALEbR(bxInstruction_c *i)
if (op1 == ((Bit16s)0x8000))
exception(BX_DE_EXCEPTION, 0);
Bit8s op2 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8s op2 = BX_READ_8BIT_REGx(i->src(), i->extend8bitL());
if (op2 == 0)
exception(BX_DE_EXCEPTION, 0);

19
bochs/cpu/proc_ctrl.cc
View File

@ -60,8 +60,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PAUSE(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PREFETCH(bxInstruction_c *i)
{
#if BX_INSTRUMENTATION
BX_INSTR_PREFETCH_HINT(BX_CPU_ID, i->nnn(), i->seg(),
BX_CPU_CALL_METHODR(i->ResolveModrm, (i)));
BX_INSTR_PREFETCH_HINT(BX_CPU_ID, i->src(), i->seg(), BX_CPU_CALL_METHODR(i->ResolveModrm, (i)));
#endif
BX_NEXT_INSTR(i);
@ -1284,10 +1283,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDFSBASE(bxInstruction_c *i)
exception(BX_UD_EXCEPTION, 0);
if (i->os64L()) {
BX_WRITE_64BIT_REG(i->rm(), MSR_FSBASE);
BX_WRITE_64BIT_REG(i->dst(), MSR_FSBASE);
}
else {
BX_WRITE_32BIT_REGZ(i->rm(), (Bit32u) MSR_FSBASE);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) MSR_FSBASE);
}
BX_NEXT_INSTR(i);
@ -1300,10 +1299,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDGSBASE(bxInstruction_c *i)
exception(BX_UD_EXCEPTION, 0);
if (i->os64L()) {
BX_WRITE_64BIT_REG(i->rm(), MSR_GSBASE);
BX_WRITE_64BIT_REG(i->dst(), MSR_GSBASE);
}
else {
BX_WRITE_32BIT_REGZ(i->rm(), (Bit32u) MSR_GSBASE);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) MSR_GSBASE);
}
BX_NEXT_INSTR(i);
@ -1316,7 +1315,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRFSBASE(bxInstruction_c *i)
exception(BX_UD_EXCEPTION, 0);
if (i->os64L()) {
Bit64u fsbase = BX_READ_64BIT_REG(i->rm());
Bit64u fsbase = BX_READ_64BIT_REG(i->src());
if (!IsCanonical(fsbase)) {
BX_ERROR(("WRFSBASE: canonical failure !"));
exception(BX_GP_EXCEPTION, 0);
@ -1325,7 +1324,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRFSBASE(bxInstruction_c *i)
}
else {
// 32-bit value is always canonical
MSR_FSBASE = BX_READ_32BIT_REG(i->rm());
MSR_FSBASE = BX_READ_32BIT_REG(i->src());
}
BX_NEXT_INSTR(i);
@ -1338,7 +1337,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRGSBASE(bxInstruction_c *i)
exception(BX_UD_EXCEPTION, 0);
if (i->os64L()) {
Bit64u gsbase = BX_READ_64BIT_REG(i->rm());
Bit64u gsbase = BX_READ_64BIT_REG(i->src());
if (!IsCanonical(gsbase)) {
BX_ERROR(("WRGSBASE: canonical failure !"));
exception(BX_GP_EXCEPTION, 0);
@ -1347,7 +1346,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRGSBASE(bxInstruction_c *i)
}
else {
// 32-bit value is always canonical
MSR_GSBASE = BX_READ_32BIT_REG(i->rm());
MSR_GSBASE = BX_READ_32BIT_REG(i->src());
}
BX_NEXT_INSTR(i);

58
bochs/cpu/protect_ctrl.cc
View File

@ -35,7 +35,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ARPL_EwGw(bxInstruction_c *i)
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
op1_16 = BX_READ_16BIT_REG(i->dst());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -43,13 +43,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ARPL_EwGw(bxInstruction_c *i)
op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
}
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->src());
if ((op1_16 & 0x03) < (op2_16 & 0x03)) {
op1_16 = (op1_16 & 0xfffc) | (op2_16 & 0x03);
/* now write back to destination */
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), op1_16);
BX_WRITE_16BIT_REG(i->dst(), op1_16);
}
else {
write_RMW_virtual_word(op1_16);
@ -80,7 +80,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LAR_GvEw(bxInstruction_c *i)
}
if (i->modC0()) {
raw_selector = BX_READ_16BIT_REG(i->rm());
raw_selector = BX_READ_16BIT_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -167,10 +167,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LAR_GvEw(bxInstruction_c *i)
assert_ZF();
if (i->os32L()) {
/* masked by 00FxFF00, where x is undefined */
BX_WRITE_32BIT_REGZ(i->nnn(), dword2 & 0x00ffff00);
BX_WRITE_32BIT_REGZ(i->dst(), dword2 & 0x00ffff00);
}
else {
BX_WRITE_16BIT_REG(i->nnn(), dword2 & 0xff00);
BX_WRITE_16BIT_REG(i->dst(), dword2 & 0xff00);
}
BX_NEXT_INSTR(i);
@ -193,7 +193,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LSL_GvEw(bxInstruction_c *i)
}
if (i->modC0()) {
raw_selector = BX_READ_16BIT_REG(i->rm());
raw_selector = BX_READ_16BIT_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -269,11 +269,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LSL_GvEw(bxInstruction_c *i)
assert_ZF();
if (i->os32L()) {
BX_WRITE_32BIT_REGZ(i->nnn(), limit32);
BX_WRITE_32BIT_REGZ(i->dst(), limit32);
}
else {
// chop off upper 16 bits
BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) limit32);
BX_WRITE_16BIT_REG(i->dst(), (Bit16u) limit32);
}
BX_NEXT_INSTR(i);
@ -289,16 +289,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SLDT_Ew(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_LDTR_TR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_LDTR_TR_ACCESS, BX_WRITE);
#endif
Bit16u val16 = BX_CPU_THIS_PTR ldtr.selector.value;
if (i->modC0()) {
if (i->os32L()) {
BX_WRITE_32BIT_REGZ(i->rm(), val16);
BX_WRITE_32BIT_REGZ(i->dst(), val16);
}
else {
BX_WRITE_16BIT_REG(i->rm(), val16);
BX_WRITE_16BIT_REG(i->dst(), val16);
}
}
else {
@ -320,16 +320,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::STR_Ew(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_LDTR_TR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_LDTR_TR_ACCESS, BX_WRITE);
#endif
Bit16u val16 = BX_CPU_THIS_PTR tr.selector.value;
if (i->modC0()) {
if (i->os32L()) {
BX_WRITE_32BIT_REGZ(i->rm(), val16);
BX_WRITE_32BIT_REGZ(i->dst(), val16);
}
else {
BX_WRITE_16BIT_REG(i->rm(), val16);
BX_WRITE_16BIT_REG(i->dst(), val16);
}
}
else {
@ -365,11 +365,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LLDT_Ew(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_LDTR_TR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_LDTR_TR_ACCESS, BX_READ);
#endif
if (i->modC0()) {
raw_selector = BX_READ_16BIT_REG(i->rm());
raw_selector = BX_READ_16BIT_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -462,11 +462,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LTR_Ew(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_LDTR_TR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_LDTR_TR_ACCESS, BX_READ);
#endif
if (i->modC0()) {
raw_selector = BX_READ_16BIT_REG(i->rm());
raw_selector = BX_READ_16BIT_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -566,7 +566,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VERR_Ew(bxInstruction_c *i)
}
if (i->modC0()) {
raw_selector = BX_READ_16BIT_REG(i->rm());
raw_selector = BX_READ_16BIT_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -658,7 +658,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VERW_Ew(bxInstruction_c *i)
}
if (i->modC0()) {
raw_selector = BX_READ_16BIT_REG(i->rm());
raw_selector = BX_READ_16BIT_REG(i->src());
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -725,7 +725,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SGDT_Ms(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS, BX_WRITE);
#endif
#if BX_SUPPORT_SVM
@ -752,7 +752,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SIDT_Ms(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS, BX_WRITE);
#endif
#if BX_SUPPORT_SVM
@ -785,7 +785,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LGDT_Ms(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS, BX_READ);
#endif
#if BX_SUPPORT_SVM
@ -820,7 +820,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LIDT_Ms(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS, BX_READ);
#endif
#if BX_SUPPORT_SVM
@ -851,7 +851,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SGDT64_Ms(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS, BX_WRITE);
#endif
#if BX_SUPPORT_SVM
@ -878,7 +878,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SIDT64_Ms(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS, BX_WRITE);
#endif
#if BX_SUPPORT_SVM
@ -910,7 +910,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LGDT64_Ms(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS, BX_READ);
#endif
#if BX_SUPPORT_SVM
@ -946,7 +946,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LIDT64_Ms(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS);
VMexit_Instruction(i, VMX_VMEXIT_GDTR_IDTR_ACCESS, BX_READ);
#endif
#if BX_SUPPORT_SVM

28
bochs/cpu/segment_ctrl.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -37,7 +37,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LES_GwMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
BX_WRITE_16BIT_REG(i->dst(), reg_16);
BX_NEXT_INSTR(i);
}
@ -54,7 +54,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LES_GdMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
BX_WRITE_32BIT_REGZ(i->dst(), reg_32);
BX_NEXT_INSTR(i);
}
@ -71,7 +71,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LDS_GwMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
BX_WRITE_16BIT_REG(i->dst(), reg_16);
BX_NEXT_INSTR(i);
}
@ -88,7 +88,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LDS_GdMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
BX_WRITE_32BIT_REGZ(i->dst(), reg_32);
BX_NEXT_INSTR(i);
}
@ -102,7 +102,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LFS_GwMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
BX_WRITE_16BIT_REG(i->dst(), reg_16);
BX_NEXT_INSTR(i);
}
@ -116,7 +116,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LFS_GdMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
BX_WRITE_32BIT_REGZ(i->dst(), reg_32);
BX_NEXT_INSTR(i);
}
@ -131,7 +131,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LFS_GqMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
BX_WRITE_64BIT_REG(i->nnn(), reg_64);
BX_WRITE_64BIT_REG(i->dst(), reg_64);
BX_NEXT_INSTR(i);
}
@ -146,7 +146,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LGS_GwMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
BX_WRITE_16BIT_REG(i->dst(), reg_16);
BX_NEXT_INSTR(i);
}
@ -160,7 +160,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LGS_GdMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
BX_WRITE_32BIT_REGZ(i->dst(), reg_32);
BX_NEXT_INSTR(i);
}
@ -175,7 +175,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LGS_GqMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
BX_WRITE_64BIT_REG(i->nnn(), reg_64);
BX_WRITE_64BIT_REG(i->dst(), reg_64);
BX_NEXT_INSTR(i);
}
@ -190,7 +190,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LSS_GwMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
BX_WRITE_16BIT_REG(i->dst(), reg_16);
BX_NEXT_INSTR(i);
}
@ -204,7 +204,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LSS_GdMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
BX_WRITE_32BIT_REGZ(i->dst(), reg_32);
BX_NEXT_INSTR(i);
}
@ -219,7 +219,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LSS_GqMp(bxInstruction_c *i)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
BX_WRITE_64BIT_REG(i->nnn(), reg_64);
BX_WRITE_64BIT_REG(i->dst(), reg_64);
BX_NEXT_INSTR(i);
}

46
bochs/cpu/shift16.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -43,7 +43,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGwM(bxInstruction_c *i)
Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
if (count) {
Bit16u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
/* count < 32, since only lower 5 bits used */
temp_32 = ((Bit32u)(op1_16) << 16) | (op2_16); // double formed by op1:op2
@ -85,8 +85,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGwR(bxInstruction_c *i)
count &= 0x1f; // use only 5 LSB's
if (count) {
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
/* count < 32, since only lower 5 bits used */
temp_32 = ((Bit32u)(op1_16) << 16) | (op2_16); // double formed by op1:op2
@ -101,7 +101,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGwR(bxInstruction_c *i)
Bit16u result_16 = (Bit16u)(result_32 >> 16);
BX_WRITE_16BIT_REG(i->rm(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
SET_FLAGS_OSZAPC_LOGIC_16(result_16);
@ -131,7 +131,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EwGwM(bxInstruction_c *i)
Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
if (count) {
Bit16u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
/* count < 32, since only lower 5 bits used */
temp_32 = (op2_16 << 16) | op1_16; // double formed by op2:op1
@ -172,8 +172,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EwGwR(bxInstruction_c *i)
count &= 0x1f; /* use only 5 LSB's */
if (count) {
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op2_16 = BX_READ_16BIT_REG(i->nnn());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
/* count < 32, since only lower 5 bits used */
temp_32 = (op2_16 << 16) | op1_16; // double formed by op2:op1
@ -188,7 +188,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EwGwR(bxInstruction_c *i)
Bit16u result_16 = (Bit16u) result_32;
BX_WRITE_16BIT_REG(i->rm(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
SET_FLAGS_OSZAPC_LOGIC_16(result_16);
@ -248,7 +248,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EwR(bxInstruction_c *i)
else
count = i->Ib();
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
if ((count & 0x0f) == 0) {
if (count & 0x10) {
@ -263,7 +263,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EwR(bxInstruction_c *i)
Bit16u result_16 = (op1_16 << count) | (op1_16 >> (16 - count));
BX_WRITE_16BIT_REG(i->rm(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
bit0 = (result_16 & 0x1);
bit15 = (result_16 >> 15);
@ -322,7 +322,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EwR(bxInstruction_c *i)
else
count = i->Ib();
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
if ((count & 0x0f) == 0) {
if (count & 0x10) {
@ -337,7 +337,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EwR(bxInstruction_c *i)
Bit16u result_16 = (op1_16 >> count) | (op1_16 << (16 - count));
BX_WRITE_16BIT_REG(i->rm(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
bit14 = (result_16 >> 14) & 1;
bit15 = (result_16 >> 15) & 1;
@ -401,7 +401,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EwR(bxInstruction_c *i)
count = (count & 0x1f) % 17;
if (count) {
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
if (count==1) {
result_16 = (op1_16 << 1) | getB_CF();
@ -414,7 +414,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EwR(bxInstruction_c *i)
(op1_16 >> (17 - count));
}
BX_WRITE_16BIT_REG(i->rm(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
cf = (op1_16 >> (16 - count)) & 0x1;
of = cf ^ (result_16 >> 15); // of = cf ^ result15
@ -467,12 +467,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EwR(bxInstruction_c *i)
count = (count & 0x1f) % 17;
if (count) {
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit16u result_16 = (op1_16 >> count) | (getB_CF() << (16 - count)) |
(op1_16 << (17 - count));
BX_WRITE_16BIT_REG(i->rm(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
cf = (op1_16 >> (count - 1)) & 0x1;
of = ((Bit16u)((result_16 << 1) ^ result_16) >> 15) & 0x1; // of = result15 ^ result14
@ -532,7 +532,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EwR(bxInstruction_c *i)
count &= 0x1f; /* use only 5 LSB's */
if (count) {
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
if (count <= 16) {
result_16 = (op1_16 << count);
@ -543,7 +543,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EwR(bxInstruction_c *i)
result_16 = 0;
}
BX_WRITE_16BIT_REG(i->rm(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
SET_FLAGS_OSZAPC_LOGIC_16(result_16);
SET_FLAGS_OxxxxC(of, cf);
@ -598,9 +598,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EwR(bxInstruction_c *i)
count &= 0x1f; /* use only 5 LSB's */
if (count) {
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit16u result_16 = (op1_16 >> count);
BX_WRITE_16BIT_REG(i->rm(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
cf = (op1_16 >> (count - 1)) & 0x1;
// note, that of == result15 if count == 1 and
@ -656,9 +656,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EwR(bxInstruction_c *i)
count &= 0x1f; /* use only 5 LSB's */
if (count) {
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
Bit16u result_16 = ((Bit16s) op1_16) >> count;
BX_WRITE_16BIT_REG(i->rm(), result_16);
BX_WRITE_16BIT_REG(i->dst(), result_16);
cf = (((Bit16s) op1_16) >> (count - 1)) & 0x1;

66
bochs/cpu/shift32.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -41,7 +41,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGdM(bxInstruction_c *i)
count &= 0x1f; // use only 5 LSB's
if (count) {
Bit32u op2_32 = BX_READ_32BIT_REG(i->nnn());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
@ -71,15 +71,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGdR(bxInstruction_c *i)
count &= 0x1f; // use only 5 LSB's
if (!count) {
BX_CLEAR_64BIT_HIGH(i->rm()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
}
else {
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
@ -108,7 +108,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGdM(bxInstruction_c *i)
count &= 0x1f; // use only 5 LSB's
if (count) {
Bit32u op2_32 = BX_READ_32BIT_REG(i->nnn());
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
@ -138,15 +138,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGdR(bxInstruction_c *i)
count &= 0x1f; // use only 5 LSB's
if (!count) {
BX_CLEAR_64BIT_HIGH(i->rm()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
}
else {
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->dst());
op2_32 = BX_READ_32BIT_REG(i->src());
result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
@ -201,12 +201,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EdR(bxInstruction_c *i)
count &= 0x1f;
if (!count) {
BX_CLEAR_64BIT_HIGH(i->rm()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
}
else {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
result_32 = (op1_32 << count) | (op1_32 >> (32 - count));
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
bit0 = (result_32 & 0x1);
bit31 = (result_32 >> 31);
@ -261,12 +261,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EdR(bxInstruction_c *i)
count &= 0x1f;
if (!count) {
BX_CLEAR_64BIT_HIGH(i->rm()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
}
else {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->dst());
result_32 = (op1_32 >> count) | (op1_32 << (32 - count));
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
bit31 = (result_32 >> 31) & 1;
bit30 = (result_32 >> 30) & 1;
@ -327,11 +327,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EdR(bxInstruction_c *i)
count &= 0x1f;
if (!count) {
BX_CLEAR_64BIT_HIGH(i->rm()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
if (count==1) {
result_32 = (op1_32 << 1) | getB_CF();
@ -341,7 +341,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EdR(bxInstruction_c *i)
(op1_32 >> (33 - count));
}
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
cf = (op1_32 >> (32 - count)) & 0x1;
of = cf ^ (result_32 >> 31); // of = cf ^ result31
@ -402,11 +402,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EdR(bxInstruction_c *i)
count &= 0x1f;
if (!count) {
BX_CLEAR_64BIT_HIGH(i->rm()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
BX_NEXT_INSTR(i);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
if (count==1) {
result_32 = (op1_32 >> 1) | (getB_CF() << 31);
@ -416,7 +416,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EdR(bxInstruction_c *i)
(op1_32 << (33 - count));
}
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
cf = (op1_32 >> (count - 1)) & 0x1;
of = ((result_32 << 1) ^ result_32) >> 31; // of = result30 ^ result31
@ -468,19 +468,19 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EdR(bxInstruction_c *i)
count &= 0x1f;
if (!count) {
BX_CLEAR_64BIT_HIGH(i->rm()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
}
else {
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
/* count < 32, since only lower 5 bits used */
Bit32u result_32 = (op1_32 << count);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
unsigned cf = (op1_32 >> (32 - count)) & 0x1;
unsigned of = cf ^ (result_32 >> 31);
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
SET_FLAGS_OxxxxC(of, cf);
}
@ -532,12 +532,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EdR(bxInstruction_c *i)
count &= 0x1f;
if (!count) {
BX_CLEAR_64BIT_HIGH(i->rm()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
}
else {
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
Bit32u result_32 = (op1_32 >> count);
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
unsigned cf = (op1_32 >> (count - 1)) & 0x1;
// note, that of == result31 if count == 1 and
@ -592,15 +592,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EdR(bxInstruction_c *i)
count &= 0x1f;
if (!count) {
BX_CLEAR_64BIT_HIGH(i->rm()); // always clear upper part of the register
BX_CLEAR_64BIT_HIGH(i->dst()); // always clear upper part of the register
}
else {
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op1_32 = BX_READ_32BIT_REG(i->dst());
/* count < 32, since only lower 5 bits used */
Bit32u result_32 = ((Bit32s) op1_32) >> count;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
unsigned cf = (op1_32 >> (count - 1)) & 1;

46
bochs/cpu/shift64.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -45,7 +45,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGqM(bxInstruction_c *i)
count &= 0x3f; // use only 6 LSB's
if (count) {
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
@ -75,12 +75,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGqR(bxInstruction_c *i)
count &= 0x3f; // use only 6 LSB's
if (count) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
BX_WRITE_64BIT_REG(i->rm(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
@ -111,7 +111,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGqM(bxInstruction_c *i)
count &= 0x3f; // use only 6 LSB's
if (count) {
op2_64 = BX_READ_64BIT_REG(i->nnn());
op2_64 = BX_READ_64BIT_REG(i->src());
result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
@ -141,12 +141,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGqR(bxInstruction_c *i)
count &= 0x3f; // use only 6 LSB's
if (count) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op2_64 = BX_READ_64BIT_REG(i->nnn());
op1_64 = BX_READ_64BIT_REG(i->dst());
op2_64 = BX_READ_64BIT_REG(i->src());
result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
BX_WRITE_64BIT_REG(i->rm(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
@ -199,9 +199,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EqR(bxInstruction_c *i)
count &= 0x3f;
if (count) {
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
Bit64u result_64 = (op1_64 << count) | (op1_64 >> (64 - count));
BX_WRITE_64BIT_REG(i->rm(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
unsigned bit0 = (result_64 & 0x1);
unsigned bit63 = (result_64 >> 63);
@ -253,9 +253,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EqR(bxInstruction_c *i)
count &= 0x3f;
if (count) {
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
Bit64u result_64 = (op1_64 >> count) | (op1_64 << (64 - count));
BX_WRITE_64BIT_REG(i->rm(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
unsigned bit63 = (result_64 >> 63) & 1;
unsigned bit62 = (result_64 >> 62) & 1;
@ -321,7 +321,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EqR(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
if (count==1) {
result_64 = (op1_64 << 1) | getB_CF();
@ -331,7 +331,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EqR(bxInstruction_c *i)
(op1_64 >> (65 - count));
}
BX_WRITE_64BIT_REG(i->rm(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
cf = (op1_64 >> (64 - count)) & 0x1;
of = cf ^ (result_64 >> 63); // of = cf ^ result63
@ -395,7 +395,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EqR(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
if (count==1) {
result_64 = (op1_64 >> 1) | (((Bit64u) getB_CF()) << 63);
@ -405,7 +405,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EqR(bxInstruction_c *i)
(op1_64 << (65 - count));
}
BX_WRITE_64BIT_REG(i->rm(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
cf = (op1_64 >> (count - 1)) & 0x1;
of = ((result_64 << 1) ^ result_64) >> 63;
@ -459,10 +459,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EqR(bxInstruction_c *i)
count &= 0x3f;
if (count) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->dst());
/* count < 64, since only lower 6 bits used */
result_64 = (op1_64 << count);
BX_WRITE_64BIT_REG(i->rm(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
cf = (op1_64 >> (64 - count)) & 0x1;
of = cf ^ (result_64 >> 63);
@ -517,9 +517,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EqR(bxInstruction_c *i)
count &= 0x3f;
if (count) {
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
Bit64u result_64 = (op1_64 >> count);
BX_WRITE_64BIT_REG(i->rm(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
unsigned cf = (op1_64 >> (count - 1)) & 0x1;
// note, that of == result63 if count == 1 and
@ -574,12 +574,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EqR(bxInstruction_c *i)
count &= 0x3f;
if (count) {
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
/* count < 64, since only lower 6 bits used */
Bit64u result_64 = ((Bit64s) op1_64) >> count;
BX_WRITE_64BIT_REG(i->rm(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
unsigned cf = (op1_64 >> (count - 1)) & 1;

30
bochs/cpu/shift8.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
// Copyright (C) 2001-2012 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -34,7 +34,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EbR(bxInstruction_c *i)
else
count = i->Ib();
Bit8u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
if ((count & 0x07) == 0) {
if (count & 0x18) {
@ -48,7 +48,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EbR(bxInstruction_c *i)
Bit8u result_8 = (op1_8 << count) | (op1_8 >> (8 - count));
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
/* set eflags:
* ROL count affects the following flags: C, O
@ -112,7 +112,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EbR(bxInstruction_c *i)
else
count = i->Ib();
Bit8u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
if ((count & 0x07) == 0) {
if (count & 0x18) {
@ -127,7 +127,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EbR(bxInstruction_c *i)
Bit8u result_8 = (op1_8 >> count) | (op1_8 << (8 - count));
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
/* set eflags:
* ROR count affects the following flags: C, O
@ -199,7 +199,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EbR(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
Bit8u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
if (count==1) {
result_8 = (op1_8 << 1) | getB_CF();
@ -209,7 +209,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EbR(bxInstruction_c *i)
(op1_8 >> (9 - count));
}
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
cf = (op1_8 >> (8 - count)) & 0x01;
of = cf ^ (result_8 >> 7); // of = cf ^ result7
@ -269,12 +269,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EbR(bxInstruction_c *i)
count = (count & 0x1f) % 9;
if (count) {
Bit8u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit8u result_8 = (op1_8 >> count) | (getB_CF() << (8 - count)) |
(op1_8 << (9 - count));
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
cf = (op1_8 >> (count - 1)) & 0x1;
of = (((result_8 << 1) ^ result_8) >> 7) & 0x1; // of = result6 ^ result7
@ -331,7 +331,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EbR(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
Bit8u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
if (count <= 8) {
result_8 = (op1_8 << count);
@ -342,7 +342,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EbR(bxInstruction_c *i)
result_8 = 0;
}
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
SET_FLAGS_OSZAPC_LOGIC_8(result_8);
SET_FLAGS_OxxxxC(of, cf);
@ -400,9 +400,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EbR(bxInstruction_c *i)
count &= 0x1f;
if (count) {
Bit8u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit8u result_8 = (op1_8 >> count);
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
unsigned cf = (op1_8 >> (count - 1)) & 0x1;
// note, that of == result7 if count == 1 and
@ -460,9 +460,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EbR(bxInstruction_c *i)
count &= 0x1f;
if (count) {
Bit8u op1_8 = BX_READ_8BIT_REGx(i->rm(), i->extend8bitL());
Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
Bit8u result_8 = ((Bit8s) op1_8) >> count;
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
unsigned cf = (((Bit8s) op1_8) >> (count - 1)) & 0x1;

4
bochs/cpu/soft_int.cc
View File

@ -26,7 +26,7 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BOUND_GwMa(bxInstruction_c *i)
{
Bit16s op1_16 = BX_READ_16BIT_REG(i->nnn());
Bit16s op1_16 = BX_READ_16BIT_REG(i->dst());
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -43,7 +43,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BOUND_GwMa(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BOUND_GdMa(bxInstruction_c *i)
{
Bit32s op1_32 = BX_READ_32BIT_REG(i->nnn());
Bit32s op1_32 = BX_READ_32BIT_REG(i->dst());
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));

168
bochs/cpu/sse.cc
View File

@ -1,8 +1,8 @@
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////6////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2011 Stanislav Shwartsman
// Copyright (c) 2003-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -39,9 +39,9 @@
/* SSE instruction with two src operands */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C :: HANDLER (bxInstruction_c *i) \
{ \
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm()); \
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst()), op2 = BX_READ_XMM_REG(i->src()); \
(func)(&op1, &op2); \
BX_WRITE_XMM_REG(i->nnn(), op1); \
BX_WRITE_XMM_REG(i->dst(), op1); \
\
BX_NEXT_INSTR(i); \
}
@ -161,9 +161,9 @@ SSE_2OP_CPU_LEVEL6(PSADBW_VdqWdqR, sse_psadbw)
/* SSE instruction with single src operand */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C :: HANDLER (bxInstruction_c *i) \
{ \
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm()); \
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src()); \
(func)(&op); \
BX_WRITE_XMM_REG(i->nnn(), op); \
BX_WRITE_XMM_REG(i->dst(), op); \
\
BX_NEXT_INSTR(i); \
}
@ -174,40 +174,40 @@ SSE_1OP(PABSD_VdqWdqR, sse_pabsd)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFB_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src()), result;
sse_pshufb(&result, &op1, &op2);
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PBLENDVB_VdqWdqR(bxInstruction_c *i)
{
sse_pblendvb(&BX_XMM_REG(i->nnn()), &BX_XMM_REG(i->rm()), &BX_XMM_REG(0));
sse_pblendvb(&BX_XMM_REG(i->dst()), &BX_XMM_REG(i->src()), &BX_XMM_REG(0));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLENDVPS_VpsWpsR(bxInstruction_c *i)
{
sse_blendvps(&BX_XMM_REG(i->nnn()), &BX_XMM_REG(i->rm()), &BX_XMM_REG(0));
{
sse_blendvps(&BX_XMM_REG(i->dst()), &BX_XMM_REG(i->src()), &BX_XMM_REG(0));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLENDVPD_VpdWpdR(bxInstruction_c *i)
{
sse_blendvpd(&BX_XMM_REG(i->nnn()), &BX_XMM_REG(i->rm()), &BX_XMM_REG(0));
sse_blendvpd(&BX_XMM_REG(i->dst()), &BX_XMM_REG(i->src()), &BX_XMM_REG(0));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PTEST_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst()), op2 = BX_READ_XMM_REG(i->src());
unsigned result = 0;
if ((op2.xmm64u(0) & op1.xmm64u(0)) == 0 &&
@ -223,7 +223,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PTEST_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PHMINPOSUW_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
unsigned min = 0;
@ -236,44 +236,44 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PHMINPOSUW_VdqWdqR(bxInstruction_c
op.xmm32u(1) = 0;
op.xmm64u(1) = 0;
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op, i->getVL());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLENDPS_VpsWpsIbR(bxInstruction_c *i)
{
sse_blendps(&BX_XMM_REG(i->nnn()), &BX_XMM_REG(i->rm()), i->Ib());
sse_blendps(&BX_XMM_REG(i->dst()), &BX_XMM_REG(i->src()), i->Ib());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLENDPD_VpdWpdIbR(bxInstruction_c *i)
{
sse_blendpd(&BX_XMM_REG(i->nnn()), &BX_XMM_REG(i->rm()), i->Ib());
sse_blendpd(&BX_XMM_REG(i->dst()), &BX_XMM_REG(i->src()), i->Ib());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PBLENDW_VdqWdqIbR(bxInstruction_c *i)
{
sse_pblendw(&BX_XMM_REG(i->nnn()), &BX_XMM_REG(i->rm()), i->Ib());
sse_pblendw(&BX_XMM_REG(i->dst()), &BX_XMM_REG(i->src()), i->Ib());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRB_EbdVdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit8u result = op.xmmubyte(i->Ib() & 0xF);
BX_WRITE_32BIT_REGZ(i->rm(), (Bit32u) result);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRB_EbdVdqIbM(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit8u result = op.xmmubyte(i->Ib() & 0xF);
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -284,16 +284,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRB_EbdVdqIbM(bxInstruction_c *
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_EwdVdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit16u result = op.xmm16u(i->Ib() & 7);
BX_WRITE_32BIT_REGZ(i->rm(), (Bit32u) result);
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_EwdVdqIbM(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit16u result = op.xmm16u(i->Ib() & 7);
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -304,19 +304,19 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_EwdVdqIbM(bxInstruction_c *
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRD_EdVdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
#if BX_SUPPORT_X86_64
if (i->os64L()) /* 64 bit operand size mode */
{
Bit64u result = op.xmm64u(i->Ib() & 1);
BX_WRITE_64BIT_REG(i->rm(), result);
BX_WRITE_64BIT_REG(i->dst(), result);
}
else
#endif
{
Bit32u result = op.xmm32u(i->Ib() & 3);
BX_WRITE_32BIT_REGZ(i->rm(), result);
BX_WRITE_32BIT_REGZ(i->dst(), result);
}
BX_NEXT_INSTR(i);
@ -324,7 +324,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRD_EdVdqIbR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRD_EdVdqIbM(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -346,16 +346,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRD_EdVdqIbM(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRACTPS_EdVpsIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit32u result = op.xmm32u(i->Ib() & 3);
BX_WRITE_32BIT_REGZ(i->rm(), result);
BX_WRITE_32BIT_REGZ(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRACTPS_EdVpsIbM(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit32u result = op.xmm32u(i->Ib() & 3);
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -364,14 +364,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRACTPS_EdVpsIbM(bxInstruction_c
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRB_VdqEbIb(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRB_VdqHdqEbIb(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
Bit8u op2;
/* op2 is a register or memory reference */
if (i->modC0()) {
op2 = (Bit8u) BX_READ_16BIT_REG(i->rm()); // won't allow reading of AH/CH/BH/DH
op2 = (Bit8u) BX_READ_16BIT_REG(i->src2()); // won't allow reading of AH/CH/BH/DH
}
else {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -380,20 +380,20 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRB_VdqEbIb(bxInstruction_c *i)
op1.xmmubyte(i->Ib() & 0xF) = op2;
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op1, i->getVL());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INSERTPS_VpsWssIb(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INSERTPS_VpsHpsWssIb(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
Bit8u control = i->Ib();
Bit32u op2;
/* op2 is a register or memory reference */
if (i->modC0()) {
BxPackedXmmRegister temp = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister temp = BX_READ_XMM_REG(i->src2());
op2 = temp.xmm32u((control >> 6) & 3);
}
else {
@ -408,40 +408,38 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INSERTPS_VpsWssIb(bxInstruction_c
if (control & 4) op1.xmm32u(2) = 0;
if (control & 8) op1.xmm32u(3) = 0;
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op1, i->getVL());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRD_VdqEdIbR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRD_VdqHdqEdIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
#if BX_SUPPORT_X86_64
if (i->os64L()) /* 64 bit operand size mode */
{
op1.xmm64u(i->Ib() & 1) = BX_READ_64BIT_REG(i->rm());
if (i->os64L()) { /* 64 bit operand size mode */
op1.xmm64u(i->Ib() & 1) = BX_READ_64BIT_REG(i->src2());
}
else
#endif
{
op1.xmm32u(i->Ib() & 3) = BX_READ_32BIT_REG(i->rm());
op1.xmm32u(i->Ib() & 3) = BX_READ_32BIT_REG(i->src2());
}
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op1, i->getVL());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRD_VdqEdIbM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRD_VdqHdqEdIbM(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
#if BX_SUPPORT_X86_64
if (i->os64L()) /* 64 bit operand size mode */
{
if (i->os64L()) { /* 64 bit operand size mode */
Bit64u op2 = read_virtual_qword_64(i->seg(), eaddr);
op1.xmm64u(i->Ib() & 1) = op2;
}
@ -452,19 +450,19 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRD_VdqEdIbM(bxInstruction_c *i
op1.xmm32u(i->Ib() & 3) = op2;
}
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op1, i->getVL());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MPSADBW_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src()), result;
sse_mpsadbw(&result, &op1, &op2, i->Ib() & 0x7);
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
@ -474,11 +472,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MPSADBW_VdqWdqIbR(bxInstruction_c
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFD_VdqWdqIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src()), result;
sse_shufps(&result, &op, &op, i->Ib());
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REG(i->dst(), result);
#endif
BX_NEXT_INSTR(i);
@ -487,11 +485,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFD_VdqWdqIbR(bxInstruction_c *
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFHW_VdqWdqIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src()), result;
sse_pshufhw(&result, &op, i->Ib());
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REG(i->dst(), result);
#endif
BX_NEXT_INSTR(i);
@ -500,25 +498,25 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFHW_VdqWdqIbR(bxInstruction_c
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFLW_VdqWdqIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src()), result;
sse_pshuflw(&result, &op, i->Ib());
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REG(i->dst(), result);
#endif
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRW_VdqEwIbR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRW_VdqHdqEwIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
Bit8u count = i->Ib() & 0x7;
op1.xmm16u(count) = BX_READ_16BIT_REG(i->rm());
op1.xmm16u(count) = BX_READ_16BIT_REG(i->src2());
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op1, i->getVL());
#endif
BX_NEXT_INSTR(i);
@ -527,10 +525,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRW_VdqEwIbR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_GdUdqIb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit8u count = i->Ib() & 0x7;
Bit32u result = (Bit32u) op.xmm16u(count);
BX_WRITE_32BIT_REGZ(i->nnn(), result);
BX_WRITE_32BIT_REGZ(i->dst(), result);
#endif
BX_NEXT_INSTR(i);
@ -539,12 +537,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_GdUdqIb(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHUFPS_VpsWpsIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src()), result;
sse_shufps(&result, &op1, &op2, i->Ib());
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REG(i->dst(), result);
#endif
BX_NEXT_INSTR(i);
@ -553,12 +551,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHUFPS_VpsWpsIbR(bxInstruction_c *
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHUFPD_VpdWpdIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src()), result;
sse_shufpd(&result, &op1, &op2, i->Ib());
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REG(i->dst(), result);
#endif
BX_NEXT_INSTR(i);
@ -570,11 +568,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHUFPD_VpdWpdIbR(bxInstruction_c *
/* SSE packed shift instruction */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn()); \
BxPackedXmmRegister op = BX_READ_XMM_REG(i->dst()); \
\
(func)(&op, BX_READ_XMM_REG_LO_QWORD(i->rm())); \
(func)(&op, BX_READ_XMM_REG_LO_QWORD(i->src())); \
\
BX_WRITE_XMM_REG(i->nnn(), op); \
BX_WRITE_XMM_REG(i->dst(), op); \
\
BX_NEXT_INSTR(i); \
}
@ -605,7 +603,7 @@ SSE_PSHIFT_CPU_LEVEL6(PSLLQ_VdqWdqR, sse_psllq);
/* SSE packed shift with imm8 instruction */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
(func)(&BX_XMM_REG(i->rm()), i->Ib()); \
(func)(&BX_XMM_REG(i->dst()), i->Ib()); \
\
BX_NEXT_INSTR(i); \
}
@ -672,7 +670,7 @@ BX_CPP_INLINE Bit64u sse_insertq(Bit64u dest, Bit64u src, unsigned shift, unsign
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRQ_UdqIbIb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BX_WRITE_XMM_REG_LO_QWORD(i->rm(), sse_extrq(BX_READ_XMM_REG_LO_QWORD(i->rm()), i->Ib2(), i->Ib()));
BX_WRITE_XMM_REG_LO_QWORD(i->dst(), sse_extrq(BX_READ_XMM_REG_LO_QWORD(i->dst()), i->Ib2(), i->Ib()));
#endif
BX_NEXT_INSTR(i);
@ -681,9 +679,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRQ_UdqIbIb(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRQ_VdqUq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
Bit16u ctrl = BX_READ_XMM_REG_LO_WORD(i->rm());
Bit16u ctrl = BX_READ_XMM_REG_LO_WORD(i->src());
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), sse_extrq(BX_READ_XMM_REG_LO_QWORD(i->nnn()), ctrl >> 8, ctrl));
BX_WRITE_XMM_REG_LO_QWORD(i->dst(), sse_extrq(BX_READ_XMM_REG_LO_QWORD(i->dst()), ctrl >> 8, ctrl));
#endif
BX_NEXT_INSTR(i);
@ -692,9 +690,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRQ_VdqUq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INSERTQ_VdqUqIbIb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
Bit64u dest = BX_READ_XMM_REG_LO_QWORD(i->nnn()), src = BX_READ_XMM_REG_LO_QWORD(i->rm());
Bit64u dst = BX_READ_XMM_REG_LO_QWORD(i->dst()), src = BX_READ_XMM_REG_LO_QWORD(i->src());
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), sse_insertq(dest, src, i->Ib2(), i->Ib()));
BX_WRITE_XMM_REG_LO_QWORD(i->dst(), sse_insertq(dst, src, i->Ib2(), i->Ib()));
#endif
BX_NEXT_INSTR(i);
@ -703,11 +701,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INSERTQ_VdqUqIbIb(bxInstruction_c
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INSERTQ_VdqUdq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister src = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister src = BX_READ_XMM_REG(i->src());
Bit64u dest = BX_READ_XMM_REG_LO_QWORD(i->nnn());
Bit64u dst = BX_READ_XMM_REG_LO_QWORD(i->dst());
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), sse_insertq(dest, src.xmm64u(0), src.xmmubyte(9), src.xmmubyte(8)));
BX_WRITE_XMM_REG_LO_QWORD(i->dst(), sse_insertq(dst, src.xmm64u(0), src.xmmubyte(9), src.xmmubyte(8)));
#endif
BX_NEXT_INSTR(i);

136
bochs/cpu/sse_move.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2011 Stanislav Shwartsman
// Copyright (c) 2003-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -403,7 +403,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_VpsWpsM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
read_virtual_dqword(i->seg(), eaddr, &BX_XMM_REG(i->nnn()));
read_virtual_dqword(i->seg(), eaddr, &BX_XMM_REG(i->dst()));
#endif
BX_NEXT_INSTR(i);
@ -413,7 +413,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_WpsVpsM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dqword(i->seg(), eaddr, &BX_XMM_REG(i->nnn()));
write_virtual_dqword(i->seg(), eaddr, &BX_XMM_REG(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -425,7 +425,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_WpsVpsM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BX_WRITE_XMM_REG(i->nnn(), BX_READ_XMM_REG(i->rm()));
BX_WRITE_XMM_REG(i->dst(), BX_READ_XMM_REG(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -435,7 +435,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_VpsWpsM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
read_virtual_dqword_aligned(i->seg(), eaddr, &BX_XMM_REG(i->nnn()));
read_virtual_dqword_aligned(i->seg(), eaddr, &BX_XMM_REG(i->dst()));
#endif
BX_NEXT_INSTR(i);
@ -449,7 +449,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_WpsVpsM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dqword_aligned(i->seg(), eaddr, &BX_XMM_REG(i->nnn()));
write_virtual_dqword_aligned(i->seg(), eaddr, &BX_XMM_REG(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -461,7 +461,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWssR(bxInstruction_c *i)
#if BX_CPU_LEVEL >= 6
/* If the source operand is an XMM register, the high-order
96 bits of the destination XMM register are not modified. */
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), BX_READ_XMM_REG_LO_DWORD(i->rm()));
BX_WRITE_XMM_REG_LO_DWORD(i->dst(), BX_READ_XMM_REG_LO_DWORD(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -479,7 +479,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWssM(bxInstruction_c *i)
op.xmm64u(0) = (Bit64u) read_virtual_dword(i->seg(), eaddr);
op.xmm64u(1) = 0;
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op, i->getVL());
#endif
BX_NEXT_INSTR(i);
@ -490,7 +490,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_WssVssM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dword(i->seg(), eaddr, BX_READ_XMM_REG_LO_DWORD(i->nnn()));
write_virtual_dword(i->seg(), eaddr, BX_READ_XMM_REG_LO_DWORD(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -502,7 +502,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_WsdVsdM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_qword(i->seg(), eaddr, BX_XMM_REG_LO_QWORD(i->nnn()));
write_virtual_qword(i->seg(), eaddr, BX_XMM_REG_LO_QWORD(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -514,7 +514,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_VsdWsdR(bxInstruction_c *i)
#if BX_CPU_LEVEL >= 6
/* If the source operand is an XMM register, the high-order
64 bits of the destination XMM register are not modified. */
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), BX_READ_XMM_REG_LO_QWORD(i->rm()));
BX_WRITE_XMM_REG_LO_QWORD(i->dst(), BX_READ_XMM_REG_LO_QWORD(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -524,7 +524,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_VsdWsdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVHLPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), BX_READ_XMM_REG_HI_QWORD(i->rm()));
BX_WRITE_XMM_REG_LO_QWORD(i->dst(), BX_READ_XMM_REG_HI_QWORD(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -539,7 +539,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
/* pointer, segment address pair */
Bit64u val64 = read_virtual_qword(i->seg(), eaddr);
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), val64);
BX_WRITE_XMM_REG_LO_QWORD(i->dst(), val64);
#endif
BX_NEXT_INSTR(i);
@ -549,7 +549,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDDUP_VpdWqR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
sse_pbroadcastq(&BX_XMM_REG(i->nnn()), BX_READ_XMM_REG_LO_QWORD(i->rm()));
sse_pbroadcastq(&BX_XMM_REG(i->dst()), BX_READ_XMM_REG_LO_QWORD(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -559,12 +559,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDDUP_VpdWqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSLDUP_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm32u(1) = op.xmm32u(0);
op.xmm32u(3) = op.xmm32u(2);
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REG(i->dst(), op);
#endif
BX_NEXT_INSTR(i);
@ -574,12 +574,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSLDUP_VpsWpsR(bxInstruction_c *
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSHDUP_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm32u(0) = op.xmm32u(1);
op.xmm32u(2) = op.xmm32u(3);
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REG(i->dst(), op);
#endif
BX_NEXT_INSTR(i);
@ -589,7 +589,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSHDUP_VpsWpsR(bxInstruction_c *
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVLHPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BX_WRITE_XMM_REG_HI_QWORD(i->nnn(), BX_READ_XMM_REG_LO_QWORD(i->rm()));
BX_WRITE_XMM_REG_HI_QWORD(i->dst(), BX_READ_XMM_REG_LO_QWORD(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -604,7 +604,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVHPS_VpsMq(bxInstruction_c *i)
/* pointer, segment address pair */
Bit64u val64 = read_virtual_qword(i->seg(), eaddr);
BX_WRITE_XMM_REG_HI_QWORD(i->nnn(), val64);
BX_WRITE_XMM_REG_HI_QWORD(i->dst(), val64);
#endif
BX_NEXT_INSTR(i);
@ -616,7 +616,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_qword(i->seg(), eaddr, BX_XMM_REG_HI_QWORD(i->nnn()));
write_virtual_qword(i->seg(), eaddr, BX_XMM_REG_HI_QWORD(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -627,8 +627,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MASKMOVDQU_VdqUdq(bxInstruction_c
{
#if BX_CPU_LEVEL >= 6
bx_address rdi = RDI & i->asize_mask();
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn()),
mask = BX_READ_XMM_REG(i->rm()), temp;
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src1()),
mask = BX_READ_XMM_REG(i->src2()), temp;
// check for write permissions before writing even if mask is all 0s
temp.xmm64u(0) = read_RMW_virtual_qword(i->seg(), rdi);
@ -656,8 +656,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MASKMOVDQU_VdqUdq(bxInstruction_c
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
Bit32u mask = sse_pmovmskd(&BX_XMM_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
Bit32u mask = sse_pmovmskd(&BX_XMM_REG(i->src()));
BX_WRITE_32BIT_REGZ(i->dst(), mask);
#endif
BX_NEXT_INSTR(i);
@ -667,8 +667,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPD_GdVRpd(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
Bit32u mask = sse_pmovmskq(&BX_XMM_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
Bit32u mask = sse_pmovmskq(&BX_XMM_REG(i->src()));
BX_WRITE_32BIT_REGZ(i->dst(), mask);
#endif
BX_NEXT_INSTR(i);
@ -679,10 +679,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_VdqEdR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op;
op.xmm64u(0) = (Bit64u) BX_READ_32BIT_REG(i->rm());
op.xmm64u(0) = (Bit64u) BX_READ_32BIT_REG(i->src());
op.xmm64u(1) = 0;
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op, i->getVL());
#endif
BX_NEXT_INSTR(i);
@ -694,10 +694,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_VdqEdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VdqEqR(bxInstruction_c *i)
{
BxPackedXmmRegister op;
op.xmm64u(0) = BX_READ_64BIT_REG(i->rm());
op.xmm64u(0) = BX_READ_64BIT_REG(i->src());
op.xmm64u(1) = 0;
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op, i->getVL());
BX_NEXT_INSTR(i);
}
@ -708,7 +708,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VdqEqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdVdR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BX_WRITE_32BIT_REGZ(i->rm(), BX_READ_XMM_REG_LO_DWORD(i->nnn()));
BX_WRITE_32BIT_REGZ(i->dst(), BX_READ_XMM_REG_LO_DWORD(i->src()));
#endif
BX_NEXT_INSTR(i);
@ -719,7 +719,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdVdR(bxInstruction_c *i)
/* 66 0F 7E */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_EqVqR(bxInstruction_c *i)
{
BX_WRITE_64BIT_REG(i->rm(), BX_READ_XMM_REG_LO_QWORD(i->nnn()));
BX_WRITE_64BIT_REG(i->dst(), BX_READ_XMM_REG_LO_QWORD(i->src()));
BX_NEXT_INSTR(i);
}
@ -732,10 +732,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqR(bxInstruction_c *i)
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op;
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->rm());
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->src());
op.xmm64u(1) = 0; /* zero-extension to 128 bit */
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op, i->getVL());
#endif
BX_NEXT_INSTR(i);
@ -749,7 +749,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqM(bxInstruction_c *i)
op.xmm64u(0) = read_virtual_qword(i->seg(), eaddr);
op.xmm64u(1) = 0; /* zero-extension to 128 bit */
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), op, i->getVL());
#endif
BX_NEXT_INSTR(i);
@ -763,9 +763,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDQ2Q_PqVRq(bxInstruction_c *i)
BX_CPU_THIS_PTR prepareFPU2MMX();
BxPackedMmxRegister mm;
MMXUQ(mm) = BX_READ_XMM_REG_LO_QWORD(i->rm());
MMXUQ(mm) = BX_READ_XMM_REG_LO_QWORD(i->src());
BX_WRITE_MMX_REG(i->nnn(), mm);
BX_WRITE_MMX_REG(i->dst(), mm);
#endif
BX_NEXT_INSTR(i);
@ -780,10 +780,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ2DQ_VdqQq(bxInstruction_c *i)
BxPackedXmmRegister op;
op.xmm64u(0) = BX_MMX_REG(i->rm());
op.xmm64u(0) = BX_MMX_REG(i->src());
op.xmm64u(1) = 0;
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REG(i->dst(), op);
#endif
BX_NEXT_INSTR(i);
@ -793,8 +793,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ2DQ_VdqQq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVMSKB_GdUdq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
Bit32u mask = sse_pmovmskb(&BX_XMM_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
Bit32u mask = sse_pmovmskb(&BX_XMM_REG(i->src()));
BX_WRITE_32BIT_REGZ(i->dst(), mask);
#endif
BX_NEXT_INSTR(i);
@ -813,7 +813,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBW_VdqWqR(bxInstruction_c *i
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.xmm16u(0) = MMXSB0(op);
result.xmm16u(1) = MMXSB1(op);
@ -824,7 +824,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBW_VdqWqR(bxInstruction_c *i
result.xmm16u(6) = MMXSB6(op);
result.xmm16u(7) = MMXSB7(op);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -833,14 +833,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBW_VdqWqR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBD_VdqWdR(bxInstruction_c *i)
{
BxPackedXmmRegister result;
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->src());
result.xmm32u(0) = (Bit8s) (val32 & 0xFF);
result.xmm32u(1) = (Bit8s) ((val32 >> 8) & 0xFF);
result.xmm32u(2) = (Bit8s) ((val32 >> 16) & 0xFF);
result.xmm32u(3) = (Bit8s) (val32 >> 24);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -849,12 +849,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBD_VdqWdR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBQ_VdqWwR(bxInstruction_c *i)
{
BxPackedXmmRegister result;
Bit16u val16 = BX_READ_XMM_REG_LO_WORD(i->rm());
Bit16u val16 = BX_READ_XMM_REG_LO_WORD(i->src());
result.xmm64u(0) = (Bit8s) (val16 & 0xFF);
result.xmm64u(1) = (Bit8s) (val16 >> 8);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -866,14 +866,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWD_VdqWqR(bxInstruction_c *i
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.xmm32u(0) = (Bit16s) MMXSW0(op);
result.xmm32u(1) = (Bit16s) MMXSW1(op);
result.xmm32u(2) = (Bit16s) MMXSW2(op);
result.xmm32u(3) = (Bit16s) MMXSW3(op);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -882,12 +882,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWD_VdqWqR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWQ_VdqWdR(bxInstruction_c *i)
{
BxPackedXmmRegister result;
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->src());
result.xmm64u(0) = (Bit16s) (val32 & 0xFFFF);
result.xmm64u(1) = (Bit16s) (val32 >> 16);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -896,12 +896,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWQ_VdqWdR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXDQ_VdqWqR(bxInstruction_c *i)
{
BxPackedXmmRegister result;
Bit64u val64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
Bit64u val64 = BX_READ_XMM_REG_LO_QWORD(i->src());
result.xmm64u(0) = (Bit32s) (val64 & 0xFFFFFFFF);
result.xmm64u(1) = (Bit32s) (val64 >> 32);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -913,7 +913,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBW_VdqWqR(bxInstruction_c *i
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.xmm16u(0) = MMXUB0(op);
result.xmm16u(1) = MMXUB1(op);
@ -924,7 +924,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBW_VdqWqR(bxInstruction_c *i
result.xmm16u(6) = MMXUB6(op);
result.xmm16u(7) = MMXUB7(op);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -933,14 +933,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBW_VdqWqR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBD_VdqWdR(bxInstruction_c *i)
{
BxPackedXmmRegister result;
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->src());
result.xmm32u(0) = val32 & 0xFF;
result.xmm32u(1) = (val32 >> 8) & 0xFF;
result.xmm32u(2) = (val32 >> 16) & 0xFF;
result.xmm32u(3) = val32 >> 24;
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -949,12 +949,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBD_VdqWdR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBQ_VdqWwR(bxInstruction_c *i)
{
BxPackedXmmRegister result;
Bit16u val16 = BX_READ_XMM_REG_LO_WORD(i->rm());
Bit16u val16 = BX_READ_XMM_REG_LO_WORD(i->src());
result.xmm64u(0) = val16 & 0xFF;
result.xmm64u(1) = val16 >> 8;
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -966,14 +966,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWD_VdqWqR(bxInstruction_c *i
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.xmm32u(0) = MMXUW0(op);
result.xmm32u(1) = MMXUW1(op);
result.xmm32u(2) = MMXUW2(op);
result.xmm32u(3) = MMXUW3(op);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -982,12 +982,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWD_VdqWqR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWQ_VdqWdR(bxInstruction_c *i)
{
BxPackedXmmRegister result;
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->src());
result.xmm64u(0) = val32 & 0xFFFF;
result.xmm64u(1) = val32 >> 16;
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -996,12 +996,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWQ_VdqWdR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXDQ_VdqWqR(bxInstruction_c *i)
{
BxPackedXmmRegister result;
Bit64u val64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
Bit64u val64 = BX_READ_XMM_REG_LO_QWORD(i->src());
result.xmm64u(0) = val64 & 0xFFFFFFFF;
result.xmm64u(1) = val64 >> 32;
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REGZ(i->dst(), result, i->getVL());
BX_NEXT_INSTR(i);
}
@ -1009,11 +1009,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXDQ_VdqWqR(bxInstruction_c *i
/* 66 0F 3A 0F */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst()), op2 = BX_READ_XMM_REG(i->src());
sse_palignr(&op2, &op1, i->Ib());
BX_WRITE_XMM_REG(i->nnn(), op2);
BX_WRITE_XMM_REG(i->dst(), op2);
BX_NEXT_INSTR(i);
}

308
bochs/cpu/sse_pfp.cc
View File

File diff suppressed because it is too large Load Diff

18
bochs/cpu/sse_rcp.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2011 Stanislav Shwartsman
// Copyright (c) 2003-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -347,14 +347,14 @@ float32 approximate_rcp(float32 op)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCPPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm32u(0) = approximate_rcp(op.xmm32u(0));
op.xmm32u(1) = approximate_rcp(op.xmm32u(1));
op.xmm32u(2) = approximate_rcp(op.xmm32u(2));
op.xmm32u(3) = approximate_rcp(op.xmm32u(3));
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REG(i->dst(), op);
#endif
BX_NEXT_INSTR(i);
@ -368,9 +368,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCPPS_VpsWpsR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCPSS_VssWssR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
float32 op = BX_READ_XMM_REG_LO_DWORD(i->rm());
float32 op = BX_READ_XMM_REG_LO_DWORD(i->src());
op = approximate_rcp(op);
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op);
BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op);
#endif
BX_NEXT_INSTR(i);
@ -704,9 +704,9 @@ float32 approximate_rsqrt(float32 op)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RSQRTSS_VssWssR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
float32 op = BX_READ_XMM_REG_LO_DWORD(i->rm());
float32 op = BX_READ_XMM_REG_LO_DWORD(i->src());
op = approximate_rsqrt(op);
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op);
BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op);
#endif
BX_NEXT_INSTR(i);
@ -721,14 +721,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RSQRTSS_VssWssR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RSQRTPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm32u(0) = approximate_rsqrt(op.xmm32u(0));
op.xmm32u(1) = approximate_rsqrt(op.xmm32u(1));
op.xmm32u(2) = approximate_rsqrt(op.xmm32u(2));
op.xmm32u(3) = approximate_rsqrt(op.xmm32u(3));
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REG(i->dst(), op);
#endif
BX_NEXT_INSTR(i);

14
bochs/cpu/sse_string.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007-2011 Stanislav Shwartsman
// Copyright (c) 2007-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -281,8 +281,8 @@ static Bit16u aggregate(Bit8u BoolRes[16][16], unsigned len1, unsigned len2, Bit
/* 66 0F 3A 60 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRM_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src()), result;
Bit8u imm8 = i->Ib();
// compare all pairs of Ai, Bj
@ -337,7 +337,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRM_VdqWdqIbR(bxInstruction_
/* 66 0F 3A 61 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRI_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst()), op2 = BX_READ_XMM_REG(i->src());
Bit8u imm8 = i->Ib();
// compare all pairs of Ai, Bj
@ -388,8 +388,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRI_VdqWdqIbR(bxInstruction_
/* 66 0F 3A 62 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRM_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src()), result;
Bit8u imm8 = i->Ib();
// compare all pairs of Ai, Bj
@ -435,7 +435,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRM_VdqWdqIbR(bxInstruction_
/* 66 0F 3A 63 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRI_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->dst()), op2 = BX_READ_XMM_REG(i->src());
Bit8u imm8 = i->Ib();
// compare all pairs of Ai, Bj

10
bochs/cpu/stack16.cc
View File

@ -26,14 +26,14 @@
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_RX(bxInstruction_c *i)
{
push_16(BX_READ_16BIT_REG(i->rm()));
push_16(BX_READ_16BIT_REG(i->dst()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH16_Sw(bxInstruction_c *i)
{
push_16(BX_CPU_THIS_PTR sregs[i->nnn()].selector.value);
push_16(BX_CPU_THIS_PTR sregs[i->src()].selector.value);
BX_NEXT_INSTR(i);
}
@ -43,11 +43,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP16_Sw(bxInstruction_c *i)
RSP_SPECULATIVE;
Bit16u selector = pop_16();
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->nnn()], selector);
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->dst()], selector);
RSP_COMMIT;
if (i->nnn() == BX_SEG_REG_SS) {
if (i->dst() == BX_SEG_REG_SS) {
// POP SS inhibits interrupts, debug exceptions and single-step
// trap exceptions until the execution boundary following the
// next instruction is reached.
@ -60,7 +60,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP16_Sw(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_RX(bxInstruction_c *i)
{
BX_WRITE_16BIT_REG(i->rm(), pop_16());
BX_WRITE_16BIT_REG(i->dst(), pop_16());
BX_NEXT_INSTR(i);
}

12
bochs/cpu/stack32.cc
View File

@ -44,21 +44,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_EdM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_ERX(bxInstruction_c *i)
{
push_32(BX_READ_32BIT_REG(i->rm()));
push_32(BX_READ_32BIT_REG(i->dst()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_ERX(bxInstruction_c *i)
{
BX_WRITE_32BIT_REGZ(i->rm(), pop_32());
BX_WRITE_32BIT_REGZ(i->dst(), pop_32());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH32_Sw(bxInstruction_c *i)
{
Bit16u val_16 = BX_CPU_THIS_PTR sregs[i->nnn()].selector.value;
Bit16u val_16 = BX_CPU_THIS_PTR sregs[i->src()].selector.value;
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
stack_write_word((Bit32u) (ESP-4), val_16);
@ -79,16 +79,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP32_Sw(bxInstruction_c *i)
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
selector = stack_read_word(ESP);
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->nnn()], selector);
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->dst()], selector);
ESP += 4;
}
else {
selector = stack_read_word(SP);
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->nnn()], selector);
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->dst()], selector);
SP += 4;
}
if (i->nnn() == BX_SEG_REG_SS) {
if (i->dst() == BX_SEG_REG_SS) {
// POP SS inhibits interrupts, debug exceptions and single-step
// trap exceptions until the execution boundary following the
// next instruction is reached.

8
bochs/cpu/stack64.cc
View File

@ -46,21 +46,21 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_EqM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_RRX(bxInstruction_c *i)
{
push_64(BX_READ_64BIT_REG(i->rm()));
push_64(BX_READ_64BIT_REG(i->dst()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_RRX(bxInstruction_c *i)
{
BX_WRITE_64BIT_REG(i->rm(), pop_64());
BX_WRITE_64BIT_REG(i->dst(), pop_64());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH64_Sw(bxInstruction_c *i)
{
push_64(BX_CPU_THIS_PTR sregs[i->nnn()].selector.value);
push_64(BX_CPU_THIS_PTR sregs[i->src()].selector.value);
BX_NEXT_INSTR(i);
}
@ -68,7 +68,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH64_Sw(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POP64_Sw(bxInstruction_c *i)
{
Bit16u selector = stack_read_word(RSP);
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->nnn()], selector);
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->dst()], selector);
RSP += 8;
BX_NEXT_INSTR(i);

42
bochs/cpu/tbm32.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011 Stanislav Shwartsman
// Copyright (c) 2011-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -35,7 +35,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GdEdIdR(bxInstruction_c *i)
Bit32u op1_32 = 0;
if (start < 32 && len > 0) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = BX_READ_32BIT_REG(i->src());
op1_32 >>= start;
if (len < 32) {
@ -46,133 +46,133 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GdEdIdR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_WRITE_32BIT_REGZ(i->dst(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLCFILL_BdEdR(bxInstruction_c *i)
{
Bit32u op_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = (op_32 + 1) & op_32;
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF((op_32 + 1) == 0);
BX_WRITE_32BIT_REGZ(i->vvv(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLCI_BdEdR(bxInstruction_c *i)
{
Bit32u op_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = ~(op_32 + 1) | op_32;
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF((op_32 + 1) == 0);
BX_WRITE_32BIT_REGZ(i->vvv(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLCIC_BdEdR(bxInstruction_c *i)
{
Bit32u op_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = (op_32 + 1) & ~op_32;
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF((op_32 + 1) == 0);
BX_WRITE_32BIT_REGZ(i->vvv(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLCMSK_BdEdR(bxInstruction_c *i)
{
Bit32u op_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = (op_32 + 1) ^ op_32;
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF((op_32 + 1) == 0);
BX_WRITE_32BIT_REGZ(i->vvv(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLCS_BdEdR(bxInstruction_c *i)
{
Bit32u op_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = (op_32 + 1) | op_32;
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF((op_32 + 1) == 0);
BX_WRITE_32BIT_REGZ(i->vvv(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSFILL_BdEdR(bxInstruction_c *i)
{
Bit32u op_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = (op_32 - 1) | op_32;
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF(op_32 == 0);
BX_WRITE_32BIT_REGZ(i->vvv(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSIC_BdEdR(bxInstruction_c *i)
{
Bit32u op_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = (op_32 - 1) | ~op_32;
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF(op_32 == 0);
BX_WRITE_32BIT_REGZ(i->vvv(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::T1MSKC_BdEdR(bxInstruction_c *i)
{
Bit32u op_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = (op_32 + 1) | ~op_32;
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF((op_32 + 1) == 0);
BX_WRITE_32BIT_REGZ(i->vvv(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZMSK_BdEdR(bxInstruction_c *i)
{
Bit32u op_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op_32 = BX_READ_32BIT_REG(i->src());
Bit32u result_32 = (op_32 - 1) & ~op_32;
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF(op_32 == 0);
BX_WRITE_32BIT_REGZ(i->vvv(), result_32);
BX_WRITE_32BIT_REGZ(i->dst(), result_32);
BX_NEXT_INSTR(i);
}

42
bochs/cpu/tbm64.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011 Stanislav Shwartsman
// Copyright (c) 2011-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -35,7 +35,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GqEqIdR(bxInstruction_c *i)
Bit64u op1_64 = 0;
if (start < 64 && len > 0) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 = BX_READ_64BIT_REG(i->src());
op1_64 >>= start;
if (len < 64) {
@ -46,133 +46,133 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GqEqIdR(bxInstruction_c *i)
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_WRITE_64BIT_REG(i->dst(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLCFILL_BqEqR(bxInstruction_c *i)
{
Bit64u op_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op_64 = BX_READ_64BIT_REG(i->src());
Bit64u result_64 = (op_64 + 1) & op_64;
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF((op_64 + 1) == 0);
BX_WRITE_64BIT_REG(i->vvv(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLCI_BqEqR(bxInstruction_c *i)
{
Bit64u op_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op_64 = BX_READ_64BIT_REG(i->src());
Bit64u result_64 = ~(op_64 + 1) | op_64;
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF((op_64 + 1) == 0);
BX_WRITE_64BIT_REG(i->vvv(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLCIC_BqEqR(bxInstruction_c *i)
{
Bit64u op_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op_64 = BX_READ_64BIT_REG(i->src());
Bit64u result_64 = (op_64 + 1) & ~op_64;
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF((op_64 + 1) == 0);
BX_WRITE_64BIT_REG(i->vvv(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLCMSK_BqEqR(bxInstruction_c *i)
{
Bit64u op_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op_64 = BX_READ_64BIT_REG(i->src());
Bit64u result_64 = (op_64 + 1) ^ op_64;
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF((op_64 + 1) == 0);
BX_WRITE_64BIT_REG(i->vvv(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLCS_BqEqR(bxInstruction_c *i)
{
Bit64u op_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op_64 = BX_READ_64BIT_REG(i->src());
Bit64u result_64 = (op_64 + 1) | op_64;
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF((op_64 + 1) == 0);
BX_WRITE_64BIT_REG(i->vvv(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSFILL_BqEqR(bxInstruction_c *i)
{
Bit64u op_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op_64 = BX_READ_64BIT_REG(i->src());
Bit64u result_64 = (op_64 - 1) | op_64;
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF(op_64 == 0);
BX_WRITE_64BIT_REG(i->vvv(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSIC_BqEqR(bxInstruction_c *i)
{
Bit64u op_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op_64 = BX_READ_64BIT_REG(i->src());
Bit64u result_64 = (op_64 - 1) | ~op_64;
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF(op_64 == 0);
BX_WRITE_64BIT_REG(i->vvv(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::T1MSKC_BqEqR(bxInstruction_c *i)
{
Bit64u op_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op_64 = BX_READ_64BIT_REG(i->src());
Bit64u result_64 = (op_64 + 1) | ~op_64;
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF((op_64 + 1) == 0);
BX_WRITE_64BIT_REG(i->vvv(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZMSK_BqEqR(bxInstruction_c *i)
{
Bit64u op_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op_64 = BX_READ_64BIT_REG(i->src());
Bit64u result_64 = (op_64 - 1) & ~op_64;
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF(op_64 == 0);
BX_WRITE_64BIT_REG(i->vvv(), result_64);
BX_WRITE_64BIT_REG(i->dst(), result_64);
BX_NEXT_INSTR(i);
}

38
bochs/cpu/vmexit.cc
View File

@ -28,7 +28,8 @@
#if BX_SUPPORT_VMX
Bit32u gen_instruction_info(bxInstruction_c *i, Bit32u reason)
// BX_READ(0) form means nnn(), rm(); BX_WRITE(1) form means rm(), nnn()
Bit32u gen_instruction_info(bxInstruction_c *i, Bit32u reason, bx_bool rw_form)
{
Bit32u instr_info = 0;
@ -42,7 +43,10 @@ Bit32u gen_instruction_info(bxInstruction_c *i, Bit32u reason)
case VMX_VMEXIT_INVVPID:
case VMX_VMEXIT_INVPCID:
#endif
instr_info |= i->nnn() << 28;
if (rw_form == BX_READ)
instr_info = i->dst() << 28;
else
instr_info = i->src() << 28;
break;
default:
@ -67,7 +71,11 @@ Bit32u gen_instruction_info(bxInstruction_c *i, Bit32u reason)
//
if (i->modC0()) {
// reg/reg format
instr_info |= (1 << 10) | (i->rm() << 3);
instr_info |= (1 << 10);
if (rw_form == BX_READ)
instr_info = i->src() << 3;
else
instr_info = i->dst() << 3;
}
else {
// memory format
@ -92,7 +100,7 @@ Bit32u gen_instruction_info(bxInstruction_c *i, Bit32u reason)
return instr_info;
}
void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_Instruction(bxInstruction_c *i, Bit32u reason)
void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_Instruction(bxInstruction_c *i, Bit32u reason, bx_bool rw_form)
{
Bit64u qualification = 0;
Bit32u instr_info = 0;
@ -120,7 +128,7 @@ void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_Instruction(bxInstruction_c *i, Bit
#endif
qualification = (Bit64u) ((Bit32u) i->displ32s());
instr_info = gen_instruction_info(i, reason);
instr_info = gen_instruction_info(i, reason, rw_form);
VMwrite32(VMCS_32BIT_VMEXIT_INSTRUCTION_INFO, instr_info);
break;
@ -536,7 +544,7 @@ bx_address BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_CR0_Write(bxInstruction_c *i,
if ((vm->vm_cr0_mask & vm->vm_cr0_read_shadow) != (vm->vm_cr0_mask & val))
{
BX_DEBUG(("VMEXIT: CR0 write"));
Bit64u qualification = i->rm() << 8;
Bit64u qualification = i->src() << 8;
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
}
@ -551,8 +559,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CR3_Read(bxInstruction_c *i)
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR3_READ_VMEXIT)) {
BX_DEBUG(("VMEXIT: CR3 read"));
Bit64u qualification = 3 | (VMX_VMEXIT_CR_ACCESS_CR_READ << 4);
qualification |= (i->rm() << 8);
Bit64u qualification = 3 | (VMX_VMEXIT_CR_ACCESS_CR_READ << 4) | (i->dst() << 8);
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
}
@ -570,7 +577,7 @@ void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_CR3_Write(bxInstruction_c *i, bx_ad
}
BX_DEBUG(("VMEXIT: CR3 write"));
Bit64u qualification = 3 | (i->rm() << 8);
Bit64u qualification = 3 | (i->src() << 8);
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
}
}
@ -584,7 +591,7 @@ bx_address BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_CR4_Write(bxInstruction_c *i,
if ((vm->vm_cr4_mask & vm->vm_cr4_read_shadow) != (vm->vm_cr4_mask & val))
{
BX_DEBUG(("VMEXIT: CR4 write"));
Bit64u qualification = 4 | (i->rm() << 8);
Bit64u qualification = 4 | (i->src() << 8);
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
}
@ -599,8 +606,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CR8_Read(bxInstruction_c *i)
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR8_READ_VMEXIT)) {
BX_DEBUG(("VMEXIT: CR8 read"));
Bit64u qualification = 8 | (VMX_VMEXIT_CR_ACCESS_CR_READ << 4);
qualification |= (i->rm() << 8);
Bit64u qualification = 8 | (VMX_VMEXIT_CR_ACCESS_CR_READ << 4) | (i->dst() << 8);
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
}
@ -612,7 +618,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CR8_Write(bxInstruction_c *i)
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR8_WRITE_VMEXIT)) {
BX_DEBUG(("VMEXIT: CR8 write"));
Bit64u qualification = 8 | (i->rm() << 8);
Bit64u qualification = 8 | (i->src() << 8);
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
}
}
@ -628,15 +634,15 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CR8_Write(bxInstruction_c *i)
// [63:12] | reserved
//
void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_DR_Access(bxInstruction_c *i, unsigned read)
void BX_CPU_C::VMexit_DR_Access(unsigned read, unsigned dr, unsigned reg)
{
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
if (VMEXIT(VMX_VM_EXEC_CTRL2_DRx_ACCESS_VMEXIT))
{
BX_DEBUG(("VMEXIT: DR%d %s access", i->nnn(), read ? "READ" : "WRITE"));
BX_DEBUG(("VMEXIT: DR%d %s access", dr, read ? "READ" : "WRITE"));
Bit64u qualification = i->nnn() | (i->rm() << 8);
Bit64u qualification = dr | (reg << 8);
if (read)
qualification |= (1 << 4);

42
bochs/cpu/vmx.cc
View File

@ -2607,7 +2607,7 @@ BX_CPP_INLINE Bit32u rotate_l(Bit32u val_32)
return (val_32 << 8) | (val_32 >> 24);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMREAD(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMREAD_EdGd(bxInstruction_c *i)
{
#if BX_SUPPORT_VMX
if (! BX_CPU_THIS_PTR in_vmx || ! protected_mode() || BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_COMPAT)
@ -2615,7 +2615,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMREAD(bxInstruction_c *i)
if (BX_CPU_THIS_PTR in_vmx_guest) {
BX_ERROR(("VMEXIT: VMREAD in VMX non-root operation"));
VMexit_Instruction(i, VMX_VMEXIT_VMREAD);
VMexit_Instruction(i, VMX_VMEXIT_VMREAD, BX_READ);
}
if (CPL != 0) {
@ -2631,14 +2631,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMREAD(bxInstruction_c *i)
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
if (BX_READ_64BIT_REG_HIGH(i->nnn())) {
if (BX_READ_64BIT_REG_HIGH(i->src())) {
BX_ERROR(("VMREAD: not supported field (upper 32-bit not zero)"));
VMfail(VMXERR_UNSUPPORTED_VMCS_COMPONENT_ACCESS);
BX_NEXT_INSTR(i);
}
}
#endif
unsigned encoding = BX_READ_32BIT_REG(i->nnn());
unsigned encoding = BX_READ_32BIT_REG(i->src());
if (vmcs_field_offset(encoding) == 0xffffffff) {
BX_ERROR(("VMREAD: not supported field 0x%08x", encoding));
@ -2672,7 +2672,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMREAD(bxInstruction_c *i)
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
if (i->modC0()) {
BX_WRITE_64BIT_REG(i->rm(), field_64);
BX_WRITE_64BIT_REG(i->dst(), field_64);
}
else {
Bit64u eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -2685,7 +2685,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMREAD(bxInstruction_c *i)
Bit32u field_32 = GET32L(field_64);
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), field_32);
BX_WRITE_32BIT_REGZ(i->dst(), field_32);
}
else {
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -2699,7 +2699,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMREAD(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMWRITE(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMWRITE_GdEd(bxInstruction_c *i)
{
#if BX_SUPPORT_VMX
if (! BX_CPU_THIS_PTR in_vmx || ! protected_mode() || BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_COMPAT)
@ -2707,7 +2707,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMWRITE(bxInstruction_c *i)
if (BX_CPU_THIS_PTR in_vmx_guest) {
BX_ERROR(("VMEXIT: VMWRITE in VMX non-root operation"));
VMexit_Instruction(i, VMX_VMEXIT_VMWRITE);
VMexit_Instruction(i, VMX_VMEXIT_VMWRITE, BX_WRITE);
}
if (CPL != 0) {
@ -2727,14 +2727,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMWRITE(bxInstruction_c *i)
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
if (i->modC0()) {
val_64 = BX_READ_64BIT_REG(i->rm());
val_64 = BX_READ_64BIT_REG(i->src());
}
else {
Bit64u eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
val_64 = read_virtual_qword_64(i->seg(), eaddr);
}
if (BX_READ_64BIT_REG_HIGH(i->nnn())) {
if (BX_READ_64BIT_REG_HIGH(i->dst())) {
BX_ERROR(("VMWRITE: not supported field (upper 32-bit not zero)"));
VMfail(VMXERR_UNSUPPORTED_VMCS_COMPONENT_ACCESS);
BX_NEXT_INSTR(i);
@ -2746,7 +2746,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMWRITE(bxInstruction_c *i)
#endif
{
if (i->modC0()) {
val_32 = BX_READ_32BIT_REG(i->rm());
val_32 = BX_READ_32BIT_REG(i->src());
}
else {
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -2756,7 +2756,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMWRITE(bxInstruction_c *i)
val_64 = (Bit64u) val_32;
}
Bit32u encoding = BX_READ_32BIT_REG(i->nnn());
Bit32u encoding = BX_READ_32BIT_REG(i->dst());
if (vmcs_field_offset(encoding) == 0xffffffff) {
BX_ERROR(("VMWRITE: not supported field 0x%08x", encoding));
@ -2859,7 +2859,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INVEPT(bxInstruction_c *i)
if (BX_CPU_THIS_PTR in_vmx_guest) {
BX_ERROR(("VMEXIT: INVEPT in VMX non-root operation"));
VMexit_Instruction(i, VMX_VMEXIT_INVEPT);
VMexit_Instruction(i, VMX_VMEXIT_INVEPT, BX_READ);
}
if (CPL != 0) {
@ -2869,10 +2869,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INVEPT(bxInstruction_c *i)
bx_address type;
if (i->os64L()) {
type = BX_READ_64BIT_REG(i->nnn());
type = BX_READ_64BIT_REG(i->dst());
}
else {
type = BX_READ_32BIT_REG(i->nnn());
type = BX_READ_32BIT_REG(i->dst());
}
BxPackedXmmRegister inv_eptp;
@ -2918,7 +2918,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INVVPID(bxInstruction_c *i)
if (BX_CPU_THIS_PTR in_vmx_guest) {
BX_ERROR(("VMEXIT: INVVPID in VMX non-root operation"));
VMexit_Instruction(i, VMX_VMEXIT_INVVPID);
VMexit_Instruction(i, VMX_VMEXIT_INVVPID, BX_READ);
}
if (CPL != 0) {
@ -2928,10 +2928,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INVVPID(bxInstruction_c *i)
bx_address type;
if (i->os64L()) {
type = BX_READ_64BIT_REG(i->nnn());
type = BX_READ_64BIT_REG(i->dst());
}
else {
type = BX_READ_32BIT_REG(i->nnn());
type = BX_READ_32BIT_REG(i->dst());
}
BxPackedXmmRegister invvpid_desc;
@ -3009,7 +3009,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INVPCID(bxInstruction_c *i)
#if BX_SUPPORT_VMX >= 2
if (VMEXIT(VMX_VM_EXEC_CTRL2_INVLPG_VMEXIT)) {
BX_ERROR(("VMEXIT: INVPCID in VMX non-root operation"));
VMexit_Instruction(i, VMX_VMEXIT_INVPCID);
VMexit_Instruction(i, VMX_VMEXIT_INVPCID, BX_READ);
}
#endif
@ -3024,12 +3024,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INVPCID(bxInstruction_c *i)
bx_address type;
#if BX_SUPPORT_X86_64
if (i->os64L()) {
type = BX_READ_64BIT_REG(i->nnn());
type = BX_READ_64BIT_REG(i->dst());
}
else
#endif
{
type = BX_READ_32BIT_REG(i->nnn());
type = BX_READ_32BIT_REG(i->dst());
}
BxPackedXmmRegister invpcid_desc;

320
bochs/cpu/xop.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011 Stanislav Shwartsman
// Copyright (c) 2011-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -167,72 +167,52 @@ static vpperm_operation vpperm_op[8] = {
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCMOV_VdqHdqWdqVIb(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2, op3;
if (i->getVexW()) {
op2 = BX_READ_AVX_REG(i->Ib());
op3 = BX_READ_AVX_REG(i->rm());
}
else {
op2 = BX_READ_AVX_REG(i->rm());
op3 = BX_READ_AVX_REG(i->Ib());
}
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++) {
sse_pselect(&op1.avx128(n), &op2.avx128(n), &op3.avx128(n));
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPPERM_VdqHdqWdqVIb(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2, op3, dest;
if (i->getVexW()) {
op2 = BX_READ_XMM_REG(i->Ib());
op3 = BX_READ_XMM_REG(i->rm());
}
else {
op2 = BX_READ_XMM_REG(i->rm());
op3 = BX_READ_XMM_REG(i->Ib());
}
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3()), dst;
for (unsigned n=0;n<16;n++) {
unsigned control = op3.xmmubyte(n);
if (control & 0x10)
dest.xmmubyte(n) = op1.xmmubyte(control & 0xf);
dst.xmmubyte(n) = op1.xmmubyte(control & 0xf);
else
dest.xmmubyte(n) = op2.xmmubyte(control & 0xf);
dst.xmmubyte(n) = op2.xmmubyte(control & 0xf);
dest.xmmubyte(n) = vpperm_op[control >> 5](dest.xmmubyte(n));
dst.xmmubyte(n) = vpperm_op[control >> 5](dst.xmmubyte(n));
}
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), dest);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), dst);
BX_NEXT_INSTR(i);
}
#define XOP_SHIFT_ROTATE(HANDLER, func) \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
BxPackedXmmRegister op1, op2; \
if (i->getVexW()) { \
op1 = BX_READ_XMM_REG(i->rm()); \
op2 = BX_READ_XMM_REG(i->vvv()); \
} \
else { \
op1 = BX_READ_XMM_REG(i->vvv()); \
op2 = BX_READ_XMM_REG(i->rm()); \
} \
\
(func)(&op1, &op2); \
\
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1); \
\
BX_NEXT_INSTR(i); \
#define XOP_SHIFT_ROTATE(HANDLER, func) \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2()); \
\
(func)(&op1, &op2); \
\
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1); \
\
BX_NEXT_INSTR(i); \
}
XOP_SHIFT_ROTATE(VPSHAB_VdqWdqHdq, sse_pshab);
@ -252,31 +232,31 @@ XOP_SHIFT_ROTATE(VPROTQ_VdqWdqHdq, sse_protq);
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSSWW_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
for(unsigned n=0;n<8;n++) {
op1.xmm16s(n) = SaturateDwordSToWordS(((Bit32s) op1.xmm16s(n) * (Bit32s) op2.xmm16s(n)) + (Bit32s) op3.xmm16s(n));
}
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSSWD_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
op1.xmm32s(0) = SaturateQwordSToDwordS(((Bit32s) op1.xmm16s(1) * (Bit32s) op2.xmm16s(1)) + (Bit64s) op3.xmm32s(0));
op1.xmm32s(1) = SaturateQwordSToDwordS(((Bit32s) op1.xmm16s(3) * (Bit32s) op2.xmm16s(3)) + (Bit64s) op3.xmm32s(1));
op1.xmm32s(2) = SaturateQwordSToDwordS(((Bit32s) op1.xmm16s(5) * (Bit32s) op2.xmm16s(5)) + (Bit64s) op3.xmm32s(2));
op1.xmm32s(3) = SaturateQwordSToDwordS(((Bit32s) op1.xmm16s(7) * (Bit32s) op2.xmm16s(7)) + (Bit64s) op3.xmm32s(3));
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
@ -293,9 +273,9 @@ BX_CPP_INLINE Bit64s add_saturate64(Bit64s a, Bit64s b)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSSDQL_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
Bit64s product1 = (Bit64s) op1.xmm32s(0) * (Bit64s) op2.xmm32s(0);
Bit64s product2 = (Bit64s) op1.xmm32s(2) * (Bit64s) op2.xmm32s(2);
@ -303,31 +283,31 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSSDQL_VdqHdqWdqVIbR(bxInstruc
op1.xmm64s(0) = add_saturate64(product1, op3.xmm64s(0));
op1.xmm64s(1) = add_saturate64(product2, op3.xmm64s(1));
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSSDD_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
for(unsigned n=0;n<4;n++) {
op1.xmm32s(n) = SaturateQwordSToDwordS(((Bit64s) op1.xmm32s(n) * (Bit64s) op2.xmm32s(n)) + (Bit64s) op3.xmm32s(n));
}
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSSDQH_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
Bit64s product1 = (Bit64s) op1.xmm32s(1) * (Bit64s) op2.xmm32s(1);
Bit64s product2 = (Bit64s) op1.xmm32s(3) * (Bit64s) op2.xmm32s(3);
@ -335,47 +315,47 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSSDQH_VdqHdqWdqVIbR(bxInstruc
op1.xmm64s(0) = add_saturate64(product1, op3.xmm64s(0));
op1.xmm64s(1) = add_saturate64(product2, op3.xmm64s(1));
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSWW_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
for(unsigned n=0;n<8;n++) {
op1.xmm16s(n) = ((Bit32s) op1.xmm16s(n) * (Bit32s) op2.xmm16s(n)) + (Bit32s) op3.xmm16s(n);
}
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSWD_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
op1.xmm32s(0) = ((Bit32s) op1.xmm16s(1) * (Bit32s) op2.xmm16s(1)) + (Bit64s) op3.xmm32s(0);
op1.xmm32s(1) = ((Bit32s) op1.xmm16s(3) * (Bit32s) op2.xmm16s(3)) + (Bit64s) op3.xmm32s(1);
op1.xmm32s(2) = ((Bit32s) op1.xmm16s(5) * (Bit32s) op2.xmm16s(5)) + (Bit64s) op3.xmm32s(2);
op1.xmm32s(3) = ((Bit32s) op1.xmm16s(7) * (Bit32s) op2.xmm16s(7)) + (Bit64s) op3.xmm32s(3);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSDQL_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
Bit64s product1 = (Bit64s) op1.xmm32s(0) * (Bit64s) op2.xmm32s(0);
Bit64s product2 = (Bit64s) op1.xmm32s(2) * (Bit64s) op2.xmm32s(2);
@ -383,31 +363,31 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSDQL_VdqHdqWdqVIbR(bxInstruct
op1.xmm64s(0) = product1 + op3.xmm64s(0);
op1.xmm64s(1) = product2 + op3.xmm64s(1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSDD_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
for(unsigned n=0;n<4;n++) {
op1.xmm32s(n) = ((Bit64s) op1.xmm32s(n) * (Bit64s) op2.xmm32s(n)) + (Bit64s) op3.xmm32s(n);
}
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSDQH_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
Bit64s product1 = (Bit64s) op1.xmm32s(1) * (Bit64s) op2.xmm32s(1);
Bit64s product2 = (Bit64s) op1.xmm32s(3) * (Bit64s) op2.xmm32s(3);
@ -415,16 +395,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMACSDQH_VdqHdqWdqVIbR(bxInstruct
op1.xmm64s(0) = product1 + op3.xmm64s(0);
op1.xmm64s(1) = product2 + op3.xmm64s(1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMADCSSWD_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
Bit32s product[8];
@ -436,16 +416,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMADCSSWD_VdqHdqWdqVIbR(bxInstruc
op1.xmm32s(2) = SaturateQwordSToDwordS((Bit64s) product[4] + (Bit64s) product[5] + (Bit64s) op3.xmm32s(2));
op1.xmm32s(3) = SaturateQwordSToDwordS((Bit64s) product[6] + (Bit64s) product[7] + (Bit64s) op3.xmm32s(3));
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMADCSWD_VdqHdqWdqVIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->Ib());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->src2());
BxPackedXmmRegister op3 = BX_READ_XMM_REG(i->src3());
Bit32s product[8];
@ -457,14 +437,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMADCSWD_VdqHdqWdqVIbR(bxInstruct
op1.xmm32s(2) = product[4] + product[5] + op3.xmm32s(2);
op1.xmm32s(3) = product[6] + product[7] + op3.xmm32s(3);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPROTB_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
int count = i->Ib();
if (count > 0) {
@ -476,14 +456,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPROTB_VdqWdqIbR(bxInstruction_c *
sse_prorb(&op, -count);
}
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPROTW_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
int count = i->Ib();
if (count > 0) {
@ -495,14 +475,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPROTW_VdqWdqIbR(bxInstruction_c *
sse_prorw(&op, -count);
}
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPROTD_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
int count = i->Ib();
if (count > 0) {
@ -514,14 +494,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPROTD_VdqWdqIbR(bxInstruction_c *
sse_prord(&op, -count);
}
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPROTQ_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
int count = i->Ib();
if (count > 0) {
@ -533,102 +513,102 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPROTQ_VdqWdqIbR(bxInstruction_c *
sse_prorq(&op, -count);
}
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCOMB_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
compare8[i->Ib() & 7](&op1, &op2);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCOMW_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
compare16[i->Ib() & 7](&op1, &op2);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCOMD_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
compare32[i->Ib() & 7](&op1, &op2);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCOMQ_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
compare64[i->Ib() & 7](&op1, &op2);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCOMUB_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
compare8u[i->Ib() & 7](&op1, &op2);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCOMUW_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
compare16u[i->Ib() & 7](&op1, &op2);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCOMUD_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
compare32u[i->Ib() & 7](&op1, &op2);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPCOMUQ_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1()), op2 = BX_READ_XMM_REG(i->src2());
compare64u[i->Ib() & 7](&op1, &op2);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZPS_VpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
float_status_t status;
@ -639,14 +619,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZPS_VpsWpsR(bxInstruction_c *i
}
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZPD_VpdWpdR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
float_status_t status;
@ -658,14 +638,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZPD_VpdWpdR(bxInstruction_c *i
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZSS_VssWssR(bxInstruction_c *i)
{
float32 op = BX_READ_XMM_REG_LO_DWORD(i->rm());
float32 op = BX_READ_XMM_REG_LO_DWORD(i->src());
BxPackedXmmRegister r;
float_status_t status;
@ -675,14 +655,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZSS_VssWssR(bxInstruction_c *i
r.xmm64u(1) = 0;
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), r);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), r);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZSD_VsdWsdR(bxInstruction_c *i)
{
float64 op = BX_READ_XMM_REG_LO_QWORD(i->rm());
float64 op = BX_READ_XMM_REG_LO_QWORD(i->src());
BxPackedXmmRegister r;
float_status_t status;
@ -692,14 +672,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZSD_VsdWsdR(bxInstruction_c *i
r.xmm64u(1) = 0;
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), r);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), r);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDBW_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm16s(0) = (Bit16s) op.xmmsbyte(0x0) + (Bit16s) op.xmmsbyte(0x1);
op.xmm16s(1) = (Bit16s) op.xmmsbyte(0x2) + (Bit16s) op.xmmsbyte(0x3);
@ -710,14 +690,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDBW_VdqWdqR(bxInstruction_c *
op.xmm16s(6) = (Bit16s) op.xmmsbyte(0xC) + (Bit16s) op.xmmsbyte(0xD);
op.xmm16s(7) = (Bit16s) op.xmmsbyte(0xE) + (Bit16s) op.xmmsbyte(0xF);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDBD_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm32s(0) = (Bit32s) op.xmmsbyte(0x0) + (Bit32s) op.xmmsbyte(0x1) +
(Bit32s) op.xmmsbyte(0x2) + (Bit32s) op.xmmsbyte(0x3);
@ -728,14 +708,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDBD_VdqWdqR(bxInstruction_c *
op.xmm32s(3) = (Bit32s) op.xmmsbyte(0xC) + (Bit32s) op.xmmsbyte(0xD) +
(Bit32s) op.xmmsbyte(0xE) + (Bit32s) op.xmmsbyte(0xF);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDBQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm64s(0) = (Bit32s) op.xmmsbyte(0x0) + (Bit32s) op.xmmsbyte(0x1) +
(Bit32s) op.xmmsbyte(0x2) + (Bit32s) op.xmmsbyte(0x3) +
@ -746,54 +726,54 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDBQ_VdqWdqR(bxInstruction_c *
(Bit32s) op.xmmsbyte(0xC) + (Bit32s) op.xmmsbyte(0xD) +
(Bit32s) op.xmmsbyte(0xE) + (Bit32s) op.xmmsbyte(0xF);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDWD_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm32s(0) = (Bit32s) op.xmm16s(0) + (Bit32s) op.xmm16s(1);
op.xmm32s(1) = (Bit32s) op.xmm16s(2) + (Bit32s) op.xmm16s(3);
op.xmm32s(2) = (Bit32s) op.xmm16s(4) + (Bit32s) op.xmm16s(5);
op.xmm32s(3) = (Bit32s) op.xmm16s(6) + (Bit32s) op.xmm16s(7);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDWQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm64s(0) = (Bit32s) op.xmm16s(0) + (Bit32s) op.xmm16s(1) +
(Bit32s) op.xmm16s(2) + (Bit32s) op.xmm16s(3);
op.xmm64s(1) = (Bit32s) op.xmm16s(4) + (Bit32s) op.xmm16s(5) +
(Bit32s) op.xmm16s(6) + (Bit32s) op.xmm16s(7);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDDQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm64s(0) = (Bit64s) op.xmm32s(0) + (Bit64s) op.xmm32s(1);
op.xmm64s(1) = (Bit64s) op.xmm32s(2) + (Bit64s) op.xmm32s(3);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDUBW_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm16u(0) = (Bit16u) op.xmmubyte(0x0) + (Bit16u) op.xmmubyte(0x1);
op.xmm16u(1) = (Bit16u) op.xmmubyte(0x2) + (Bit16u) op.xmmubyte(0x3);
@ -804,14 +784,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDUBW_VdqWdqR(bxInstruction_c
op.xmm16u(6) = (Bit16u) op.xmmubyte(0xC) + (Bit16u) op.xmmubyte(0xD);
op.xmm16u(7) = (Bit16u) op.xmmubyte(0xE) + (Bit16u) op.xmmubyte(0xF);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDUBD_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm32u(0) = (Bit32u) op.xmmubyte(0x0) + (Bit32s) op.xmmubyte(0x1) +
(Bit32u) op.xmmubyte(0x2) + (Bit32s) op.xmmubyte(0x3);
@ -822,14 +802,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDUBD_VdqWdqR(bxInstruction_c
op.xmm32u(3) = (Bit32u) op.xmmubyte(0xC) + (Bit32s) op.xmmubyte(0xD) +
(Bit32u) op.xmmubyte(0xE) + (Bit32s) op.xmmubyte(0xF);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDUBQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm64u(0) = (Bit32u) op.xmmubyte(0x0) + (Bit32u) op.xmmubyte(0x1) +
(Bit32u) op.xmmubyte(0x2) + (Bit32u) op.xmmubyte(0x3) +
@ -840,54 +820,54 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDUBQ_VdqWdqR(bxInstruction_c
(Bit32u) op.xmmubyte(0xC) + (Bit32u) op.xmmubyte(0xD) +
(Bit32u) op.xmmubyte(0xE) + (Bit32u) op.xmmubyte(0xF);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDUWD_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm32u(0) = (Bit32u) op.xmm16u(0) + (Bit32u) op.xmm16u(1);
op.xmm32u(1) = (Bit32u) op.xmm16u(2) + (Bit32u) op.xmm16u(3);
op.xmm32u(2) = (Bit32u) op.xmm16u(4) + (Bit32u) op.xmm16u(5);
op.xmm32u(3) = (Bit32u) op.xmm16u(6) + (Bit32u) op.xmm16u(7);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDUWQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm64u(0) = (Bit32u) op.xmm16u(0) + (Bit32u) op.xmm16u(1) +
(Bit32u) op.xmm16u(2) + (Bit32u) op.xmm16u(3);
op.xmm64u(1) = (Bit32u) op.xmm16u(4) + (Bit32u) op.xmm16u(5) +
(Bit32u) op.xmm16u(6) + (Bit32u) op.xmm16u(7);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHADDUDQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm64u(0) = (Bit64u) op.xmm32u(0) + (Bit64u) op.xmm32u(1);
op.xmm64u(1) = (Bit64u) op.xmm32u(2) + (Bit64u) op.xmm32u(3);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHSUBBW_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm16s(0) = (Bit16s) op.xmmsbyte(0x0) - (Bit16s) op.xmmsbyte(0x1);
op.xmm16s(1) = (Bit16s) op.xmmsbyte(0x2) - (Bit16s) op.xmmsbyte(0x3);
@ -898,85 +878,65 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHSUBBW_VdqWdqR(bxInstruction_c *
op.xmm16s(6) = (Bit16s) op.xmmsbyte(0xC) - (Bit16s) op.xmmsbyte(0xD);
op.xmm16s(7) = (Bit16s) op.xmmsbyte(0xE) - (Bit16s) op.xmmsbyte(0xF);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHSUBWD_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm32s(0) = (Bit32s) op.xmm16s(0) - (Bit32s) op.xmm16s(1);
op.xmm32s(1) = (Bit32s) op.xmm16s(2) - (Bit32s) op.xmm16s(3);
op.xmm32s(2) = (Bit32s) op.xmm16s(4) - (Bit32s) op.xmm16s(5);
op.xmm32s(3) = (Bit32s) op.xmm16s(6) - (Bit32s) op.xmm16s(7);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPHSUBDQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
op.xmm64s(0) = (Bit64s) op.xmm32s(0) - (Bit64s) op.xmm32s(1);
op.xmm64s(1) = (Bit64s) op.xmm32s(2) - (Bit64s) op.xmm32s(3);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMIL2PS_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2, op3, result;
int imm_reg = i->Ib() >> 4;
if (! long64_mode()) imm_reg &= 0x7;
if (i->getVexW()) {
op2 = BX_READ_AVX_REG(imm_reg);
op3 = BX_READ_AVX_REG(i->rm());
}
else {
op2 = BX_READ_AVX_REG(i->rm());
op3 = BX_READ_AVX_REG(imm_reg);
}
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++) {
sse_permil2ps(&result.avx128(n), &op1.avx128(n), &op2.avx128(n), &op3.avx128(n), i->Ib() & 3);
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMIL2PD_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2, op3, result;
int imm_reg = i->Ib() >> 4;
if (! long64_mode()) imm_reg &= 0x7;
if (i->getVexW()) {
op2 = BX_READ_AVX_REG(imm_reg);
op3 = BX_READ_AVX_REG(i->rm());
}
else {
op2 = BX_READ_AVX_REG(i->rm());
op3 = BX_READ_AVX_REG(imm_reg);
}
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2());
BxPackedAvxRegister op3 = BX_READ_AVX_REG(i->src3()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++) {
sse_permil2pd(&result.avx128(n), &op1.avx128(n), &op2.avx128(n), &op3.avx128(n), i->Ib() & 3);
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}

74
bochs/fpu/fpu_arith.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2009 Stanislav Shwartsman
// Copyright (c) 2003-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -169,14 +169,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FADD_ST0_STj(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
{
FPU_stack_underflow(0);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(0);
floatx80 b = BX_READ_FPU_REG(i->rm());
floatx80 b = BX_READ_FPU_REG(i->src());
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
@ -198,13 +198,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FADD_STi_ST0(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->dst()))
{
FPU_stack_underflow(i->rm(), pop_stack);
FPU_stack_underflow(i->dst(), pop_stack);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(i->rm());
floatx80 a = BX_READ_FPU_REG(i->dst());
floatx80 b = BX_READ_FPU_REG(0);
float_status_t status =
@ -213,7 +213,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FADD_STi_ST0(bxInstruction_c *i)
floatx80 result = floatx80_add(a, b, status);
if (! FPU_exception(status.float_exception_flags)) {
BX_WRITE_FPU_REG(result, i->rm());
BX_WRITE_FPU_REG(result, i->dst());
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}
@ -346,14 +346,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FMUL_ST0_STj(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
{
FPU_stack_underflow(0);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(0);
floatx80 b = BX_READ_FPU_REG(i->rm());
floatx80 b = BX_READ_FPU_REG(i->src());
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
@ -375,13 +375,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FMUL_STi_ST0(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->dst()))
{
FPU_stack_underflow(i->rm(), pop_stack);
FPU_stack_underflow(i->dst(), pop_stack);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(i->rm());
floatx80 a = BX_READ_FPU_REG(i->dst());
floatx80 b = BX_READ_FPU_REG(0);
float_status_t status =
@ -390,7 +390,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FMUL_STi_ST0(bxInstruction_c *i)
floatx80 result = floatx80_mul(a, b, status);
if (! FPU_exception(status.float_exception_flags)) {
BX_WRITE_FPU_REG(result, i->rm());
BX_WRITE_FPU_REG(result, i->dst());
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}
@ -523,14 +523,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FSUB_ST0_STj(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
{
FPU_stack_underflow(0);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(0);
floatx80 b = BX_READ_FPU_REG(i->rm());
floatx80 b = BX_READ_FPU_REG(i->src());
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
@ -550,13 +550,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FSUBR_ST0_STj(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
{
FPU_stack_underflow(0);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(i->rm());
floatx80 a = BX_READ_FPU_REG(i->src());
floatx80 b = BX_READ_FPU_REG(0);
float_status_t status =
@ -579,13 +579,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FSUB_STi_ST0(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->dst()))
{
FPU_stack_underflow(i->rm(), pop_stack);
FPU_stack_underflow(i->dst(), pop_stack);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(i->rm());
floatx80 a = BX_READ_FPU_REG(i->dst());
floatx80 b = BX_READ_FPU_REG(0);
float_status_t status =
@ -594,7 +594,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FSUB_STi_ST0(bxInstruction_c *i)
floatx80 result = floatx80_sub(a, b, status);
if (! FPU_exception(status.float_exception_flags)) {
BX_WRITE_FPU_REG(result, i->rm());
BX_WRITE_FPU_REG(result, i->dst());
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}
@ -611,14 +611,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FSUBR_STi_ST0(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->dst()))
{
FPU_stack_underflow(i->rm(), pop_stack);
FPU_stack_underflow(i->dst(), pop_stack);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(0);
floatx80 b = BX_READ_FPU_REG(i->rm());
floatx80 b = BX_READ_FPU_REG(i->dst());
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
@ -626,7 +626,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FSUBR_STi_ST0(bxInstruction_c *i)
floatx80 result = floatx80_sub(a, b, status);
if (! FPU_exception(status.float_exception_flags)) {
BX_WRITE_FPU_REG(result, i->rm());
BX_WRITE_FPU_REG(result, i->dst());
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}
@ -875,14 +875,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FDIV_ST0_STj(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
{
FPU_stack_underflow(0);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(0);
floatx80 b = BX_READ_FPU_REG(i->rm());
floatx80 b = BX_READ_FPU_REG(i->src());
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
@ -902,13 +902,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FDIVR_ST0_STj(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
{
FPU_stack_underflow(0);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(i->rm());
floatx80 a = BX_READ_FPU_REG(i->src());
floatx80 b = BX_READ_FPU_REG(0);
float_status_t status =
@ -931,13 +931,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FDIV_STi_ST0(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->dst()))
{
FPU_stack_underflow(i->rm(), pop_stack);
FPU_stack_underflow(i->dst(), pop_stack);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(i->rm());
floatx80 a = BX_READ_FPU_REG(i->dst());
floatx80 b = BX_READ_FPU_REG(0);
float_status_t status =
@ -946,7 +946,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FDIV_STi_ST0(bxInstruction_c *i)
floatx80 result = floatx80_div(a, b, status);
if (! FPU_exception(status.float_exception_flags)) {
BX_WRITE_FPU_REG(result, i->rm());
BX_WRITE_FPU_REG(result, i->dst());
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}
@ -963,14 +963,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FDIVR_STi_ST0(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->dst()))
{
FPU_stack_underflow(i->rm(), pop_stack);
FPU_stack_underflow(i->dst(), pop_stack);
BX_NEXT_INSTR(i);
}
floatx80 a = BX_READ_FPU_REG(0);
floatx80 b = BX_READ_FPU_REG(i->rm());
floatx80 b = BX_READ_FPU_REG(i->dst());
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
@ -978,7 +978,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FDIVR_STi_ST0(bxInstruction_c *i)
floatx80 result = floatx80_div(a, b, status);
if (! FPU_exception(status.float_exception_flags)) {
BX_WRITE_FPU_REG(result, i->rm());
BX_WRITE_FPU_REG(result, i->dst());
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}

32
bochs/fpu/fpu_cmov.cc
View File

@ -33,12 +33,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCMOVB_ST0_STj(bxInstruction_c *i)
BX_CPU_THIS_PTR prepareFPU(i);
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm())) {
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src())) {
FPU_stack_underflow(0);
}
else {
if (get_CF())
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->rm()), 0);
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->src()), 0);
}
BX_NEXT_INSTR(i);
@ -49,12 +49,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCMOVBE_ST0_STj(bxInstruction_c *i
BX_CPU_THIS_PTR prepareFPU(i);
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm())) {
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src())) {
FPU_stack_underflow(0);
}
else {
if (get_CF() || get_ZF())
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->rm()), 0);
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->src()), 0);
}
BX_NEXT_INSTR(i);
@ -65,12 +65,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCMOVE_ST0_STj(bxInstruction_c *i)
BX_CPU_THIS_PTR prepareFPU(i);
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm())) {
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src())) {
FPU_stack_underflow(0);
}
else {
if (get_ZF())
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->rm()), 0);
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->src()), 0);
}
BX_NEXT_INSTR(i);
@ -81,12 +81,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCMOVNB_ST0_STj(bxInstruction_c *i
BX_CPU_THIS_PTR prepareFPU(i);
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm())) {
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src())) {
FPU_stack_underflow(0);
}
else {
if (! get_CF())
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->rm()), 0);
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->src()), 0);
}
BX_NEXT_INSTR(i);
@ -97,12 +97,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCMOVNBE_ST0_STj(bxInstruction_c *
BX_CPU_THIS_PTR prepareFPU(i);
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm())) {
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src())) {
FPU_stack_underflow(0);
}
else {
if (! get_CF() && ! get_ZF())
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->rm()), 0);
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->src()), 0);
}
BX_NEXT_INSTR(i);
@ -113,12 +113,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCMOVNE_ST0_STj(bxInstruction_c *i
BX_CPU_THIS_PTR prepareFPU(i);
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm())) {
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src())) {
FPU_stack_underflow(0);
}
else {
if (! get_ZF())
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->rm()), 0);
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->src()), 0);
}
BX_NEXT_INSTR(i);
@ -129,12 +129,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCMOVNU_ST0_STj(bxInstruction_c *i
BX_CPU_THIS_PTR prepareFPU(i);
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm())) {
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src())) {
FPU_stack_underflow(0);
}
else {
if (! get_PF())
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->rm()), 0);
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->src()), 0);
}
BX_NEXT_INSTR(i);
@ -145,12 +145,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCMOVU_ST0_STj(bxInstruction_c *i)
BX_CPU_THIS_PTR prepareFPU(i);
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm())) {
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src())) {
FPU_stack_underflow(0);
}
else {
if (get_PF())
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->rm()), 0);
BX_WRITE_FPU_REG(BX_READ_FPU_REG(i->src()), 0);
}
BX_NEXT_INSTR(i);

16
bochs/fpu/fpu_compare.cc
View File

@ -86,7 +86,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOM_STi(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
{
FPU_exception(FPU_EX_Stack_Underflow);
setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
@ -102,7 +102,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOM_STi(bxInstruction_c *i)
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
int rc = floatx80_compare(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->rm()), status);
int rc = floatx80_compare(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->src()), status);
setcc(status_word_flags_fpu_compare(rc));
if (! FPU_exception(status.float_exception_flags)) {
@ -122,7 +122,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOMI_ST0_STj(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
{
FPU_exception(FPU_EX_Stack_Underflow);
setEFlagsOSZAPC(EFlagsZFMask | EFlagsPFMask | EFlagsCFMask);
@ -138,7 +138,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOMI_ST0_STj(bxInstruction_c *i)
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
int rc = floatx80_compare(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->rm()), status);
int rc = floatx80_compare(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->src()), status);
BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
if (! FPU_exception(status.float_exception_flags)) {
@ -158,7 +158,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FUCOMI_ST0_STj(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
{
FPU_exception(FPU_EX_Stack_Underflow);
setEFlagsOSZAPC(EFlagsZFMask | EFlagsPFMask | EFlagsCFMask);
@ -174,7 +174,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FUCOMI_ST0_STj(bxInstruction_c *i)
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
int rc = floatx80_compare_quiet(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->rm()), status);
int rc = floatx80_compare_quiet(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->src()), status);
BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
if (! FPU_exception(status.float_exception_flags)) {
@ -194,7 +194,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FUCOM_STi(bxInstruction_c *i)
if (i->getIaOpcode() == BX_IA_FUCOMP_STi)
pop_stack = 1;
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(i->src()))
{
FPU_exception(FPU_EX_Stack_Underflow);
setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
@ -210,7 +210,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FUCOM_STi(bxInstruction_c *i)
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
int rc = floatx80_compare_quiet(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->rm()), status);
int rc = floatx80_compare_quiet(BX_READ_FPU_REG(0), BX_READ_FPU_REG(i->src()), status);
setcc(status_word_flags_fpu_compare(rc));
if (! FPU_exception(status.float_exception_flags)) {

8
bochs/fpu/fpu_load_store.cc
View File

@ -49,7 +49,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FLD_STi(bxInstruction_c *i)
floatx80 sti_reg = floatx80_default_nan;
if (IS_TAG_EMPTY(i->rm()))
if (IS_TAG_EMPTY(i->src()))
{
FPU_exception(FPU_EX_Stack_Underflow);
@ -57,7 +57,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FLD_STi(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
else {
sti_reg = BX_READ_FPU_REG(i->rm());
sti_reg = BX_READ_FPU_REG(i->src());
}
BX_CPU_THIS_PTR the_i387.FPU_push();
@ -280,12 +280,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FST_STi(bxInstruction_c *i)
clear_C1();
if (IS_TAG_EMPTY(0)) {
FPU_stack_underflow(i->rm(), pop_stack);
FPU_stack_underflow(i->dst(), pop_stack);
}
else {
floatx80 st0_reg = BX_READ_FPU_REG(0);
BX_WRITE_FPU_REG(st0_reg, i->rm());
BX_WRITE_FPU_REG(st0_reg, i->dst());
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}

12
bochs/fpu/fpu_misc.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2009 Stanislav Shwartsman
// Copyright (c) 2003-2012 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -37,10 +37,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FXCH_STi(bxInstruction_c *i)
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
int st0_tag = BX_CPU_THIS_PTR the_i387.FPU_gettagi(0);
int sti_tag = BX_CPU_THIS_PTR the_i387.FPU_gettagi(i->rm());
int sti_tag = BX_CPU_THIS_PTR the_i387.FPU_gettagi(i->src());
floatx80 st0_reg = BX_READ_FPU_REG(0);
floatx80 sti_reg = BX_READ_FPU_REG(i->rm());
floatx80 sti_reg = BX_READ_FPU_REG(i->src());
clear_C1();
@ -62,7 +62,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FXCH_STi(bxInstruction_c *i)
}
}
BX_WRITE_FPU_REG(st0_reg, i->rm());
BX_WRITE_FPU_REG(st0_reg, i->src());
BX_WRITE_FPU_REG(sti_reg, 0);
BX_NEXT_INSTR(i);
@ -138,7 +138,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FFREE_STi(bxInstruction_c *i)
clear_C1();
BX_CPU_THIS_PTR the_i387.FPU_settagi(FPU_Tag_Empty, i->rm());
BX_CPU_THIS_PTR the_i387.FPU_settagi(FPU_Tag_Empty, i->dst());
BX_NEXT_INSTR(i);
}
@ -156,7 +156,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FFREEP_STi(bxInstruction_c *i)
clear_C1();
BX_CPU_THIS_PTR the_i387.FPU_settagi(FPU_Tag_Empty, i->rm());
BX_CPU_THIS_PTR the_i387.FPU_settagi(FPU_Tag_Empty, i->dst());
BX_CPU_THIS_PTR the_i387.FPU_pop();
BX_NEXT_INSTR(i);