cc694377b9
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore. Use generic source/destination indications like SRC1, SRC2 and DST. All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly. Immediate benefits: - Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example) - Simpler to understand fetch-decode code Future benefits: - Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned) Huge patch. Almost all source files wre modified.
172 lines
4.6 KiB
C++
172 lines
4.6 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MUL_AXEwR(bxInstruction_c *i)
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{
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Bit16u op1_16 = AX;
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Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
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Bit32u product_32 = ((Bit32u) op1_16) * ((Bit32u) op2_16);
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Bit16u product_16l = (product_32 & 0xFFFF);
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Bit16u product_16h = product_32 >> 16;
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/* now write product back to destination */
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AX = product_16l;
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DX = product_16h;
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/* set EFLAGS */
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SET_FLAGS_OSZAPC_LOGIC_16(product_16l);
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if(product_16h != 0)
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{
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ASSERT_FLAGS_OxxxxC();
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_AXEwR(bxInstruction_c *i)
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{
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Bit16s op1_16 = AX;
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Bit16s op2_16 = BX_READ_16BIT_REG(i->src());
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Bit32s product_32 = ((Bit32s) op1_16) * ((Bit32s) op2_16);
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Bit16u product_16l = (product_32 & 0xFFFF);
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Bit16u product_16h = product_32 >> 16;
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/* now write product back to destination */
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AX = product_16l;
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DX = product_16h;
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/* set eflags:
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* IMUL r/m16: condition for clearing CF & OF:
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* DX:AX = sign-extend of AX
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*/
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SET_FLAGS_OSZAPC_LOGIC_16(product_16l);
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if(product_32 != (Bit16s)product_32)
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{
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ASSERT_FLAGS_OxxxxC();
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIV_AXEwR(bxInstruction_c *i)
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{
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Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
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if (op2_16 == 0)
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exception(BX_DE_EXCEPTION, 0);
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Bit32u op1_32 = (((Bit32u) DX) << 16) | ((Bit32u) AX);
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Bit32u quotient_32 = op1_32 / op2_16;
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Bit16u remainder_16 = op1_32 % op2_16;
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Bit16u quotient_16l = quotient_32 & 0xFFFF;
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if (quotient_32 != quotient_16l)
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exception(BX_DE_EXCEPTION, 0);
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/* now write quotient back to destination */
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AX = quotient_16l;
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DX = remainder_16;
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IDIV_AXEwR(bxInstruction_c *i)
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{
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Bit32s op1_32 = ((((Bit32u) DX) << 16) | ((Bit32u) AX));
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/* check MIN_INT case */
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if (op1_32 == ((Bit32s)0x80000000))
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exception(BX_DE_EXCEPTION, 0);
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Bit16s op2_16 = BX_READ_16BIT_REG(i->src());
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if (op2_16 == 0)
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exception(BX_DE_EXCEPTION, 0);
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Bit32s quotient_32 = op1_32 / op2_16;
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Bit16s remainder_16 = op1_32 % op2_16;
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Bit16s quotient_16l = quotient_32 & 0xFFFF;
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if (quotient_32 != quotient_16l)
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exception(BX_DE_EXCEPTION, 0);
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/* now write quotient back to destination */
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AX = quotient_16l;
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DX = remainder_16;
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GwEwIwR(bxInstruction_c *i)
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{
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Bit16s op2_16 = BX_READ_16BIT_REG(i->src());
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Bit16s op3_16 = i->Iw();
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Bit32s product_32 = op2_16 * op3_16;
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Bit16u product_16 = (product_32 & 0xFFFF);
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/* now write product back to destination */
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BX_WRITE_16BIT_REG(i->dst(), product_16);
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/* set eflags:
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* IMUL r16,r/m16,imm16: condition for clearing CF & OF:
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* result exactly fits within r16
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*/
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SET_FLAGS_OSZAPC_LOGIC_16(product_16);
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if(product_32 != (Bit16s) product_32)
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{
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ASSERT_FLAGS_OxxxxC();
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IMUL_GwEwR(bxInstruction_c *i)
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{
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Bit16s op1_16 = BX_READ_16BIT_REG(i->dst());
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Bit16s op2_16 = BX_READ_16BIT_REG(i->src());
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Bit32s product_32 = op1_16 * op2_16;
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Bit16u product_16 = (product_32 & 0xFFFF);
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/* now write product back to destination */
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BX_WRITE_16BIT_REG(i->dst(), product_16);
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/* set eflags:
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* IMUL r16,r/m16: condition for clearing CF & OF:
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* result exactly fits within r16
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*/
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SET_FLAGS_OSZAPC_LOGIC_16(product_16);
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if(product_32 != (Bit16s) product_32)
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{
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ASSERT_FLAGS_OxxxxC();
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}
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BX_NEXT_INSTR(i);
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}
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