cc694377b9
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore. Use generic source/destination indications like SRC1, SRC2 and DST. All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly. Immediate benefits: - Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example) - Simpler to understand fetch-decode code Future benefits: - Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned) Huge patch. Almost all source files wre modified.
757 lines
19 KiB
C++
757 lines
19 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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BX_CPP_INLINE void BX_CPP_AttrRegparmN(1) BX_CPU_C::branch_near16(Bit16u new_IP)
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{
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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// check always, not only in protected mode
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if (new_IP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
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{
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BX_ERROR(("branch_near16: offset outside of CS limits"));
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exception(BX_GP_EXCEPTION, 0);
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}
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EIP = new_IP;
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#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS == 0
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// assert magic async_event to stop trace execution
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BX_CPU_THIS_PTR async_event |= BX_ASYNC_EVENT_STOP_TRACE;
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#endif
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RETnear16_Iw(bxInstruction_c *i)
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{
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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RSP_SPECULATIVE;
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Bit16u return_IP = pop_16();
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if (return_IP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
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{
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BX_ERROR(("RETnear16_Iw: IP > limit"));
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exception(BX_GP_EXCEPTION, 0);
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}
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EIP = return_IP;
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Bit16u imm16 = i->Iw();
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) /* 32bit stack */
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ESP += imm16;
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else
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SP += imm16;
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RSP_COMMIT;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, PREV_RIP, EIP);
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BX_NEXT_TRACE(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RETnear16(bxInstruction_c *i)
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{
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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RSP_SPECULATIVE;
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Bit16u return_IP = pop_16();
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if (return_IP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
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{
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BX_ERROR(("RETnear16: IP > limit"));
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exception(BX_GP_EXCEPTION, 0);
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}
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EIP = return_IP;
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RSP_COMMIT;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, PREV_RIP, EIP);
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BX_NEXT_TRACE(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RETfar16_Iw(bxInstruction_c *i)
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{
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Bit16u ip, cs_raw;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_ret;
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#endif
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Bit16s imm16 = (Bit16s) i->Iw();
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if (protected_mode()) {
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return_protected(i, imm16);
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goto done;
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}
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RSP_SPECULATIVE;
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ip = pop_16();
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cs_raw = pop_16();
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// CS.LIMIT can't change when in real/v8086 mode
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if (ip > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
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BX_ERROR(("RETfar16_Iw: instruction pointer not within code segment limits"));
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exception(BX_GP_EXCEPTION, 0);
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}
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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EIP = (Bit32u) ip;
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if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
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ESP += imm16;
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else
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SP += imm16;
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RSP_COMMIT;
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done:
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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BX_NEXT_TRACE(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_Jw(bxInstruction_c *i)
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{
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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RSP_SPECULATIVE;
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/* push 16 bit EA of next instruction */
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push_16(IP);
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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RSP_COMMIT;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, PREV_RIP, EIP);
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BX_NEXT_TRACE(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL16_Ap(bxInstruction_c *i)
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{
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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Bit16u disp16 = i->Iw();
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Bit16u cs_raw = i->Iw2();
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RSP_SPECULATIVE;
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if (protected_mode()) {
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call_protected(i, cs_raw, disp16);
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goto done;
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}
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push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_16(IP);
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// CS.LIMIT can't change when in real/v8086 mode
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if (disp16 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
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BX_ERROR(("CALL16_Ap: instruction pointer not within code segment limits"));
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exception(BX_GP_EXCEPTION, 0);
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}
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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EIP = (Bit32u) disp16;
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done:
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RSP_COMMIT;
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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BX_NEXT_TRACE(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EwR(bxInstruction_c *i)
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{
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Bit16u new_IP = BX_READ_16BIT_REG(i->dst());
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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RSP_SPECULATIVE;
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/* push 16 bit EA of next instruction */
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push_16(IP);
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branch_near16(new_IP);
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RSP_COMMIT;
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL_INDIRECT, PREV_RIP, EIP);
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BX_NEXT_TRACE(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL16_Ep(bxInstruction_c *i)
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{
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Bit16u cs_raw;
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Bit16u op1_16;
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invalidate_prefetch_q();
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR show_flag |= Flag_call;
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#endif
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_16 = read_virtual_word(i->seg(), eaddr);
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cs_raw = read_virtual_word(i->seg(), (eaddr+2) & i->asize_mask());
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RSP_SPECULATIVE;
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if (protected_mode()) {
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call_protected(i, cs_raw, op1_16);
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goto done;
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}
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push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
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push_16(IP);
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// CS.LIMIT can't change when in real/v8086 mode
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if (op1_16 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
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BX_ERROR(("CALL16_Ep: instruction pointer not within code segment limits"));
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exception(BX_GP_EXCEPTION, 0);
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}
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load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
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EIP = op1_16;
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done:
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RSP_COMMIT;
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BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL_INDIRECT,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
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BX_NEXT_TRACE(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_Jw(bxInstruction_c *i)
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{
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JO_Jw(bxInstruction_c *i)
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{
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if (get_OF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JNO_Jw(bxInstruction_c *i)
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{
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if (! get_OF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JB_Jw(bxInstruction_c *i)
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{
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if (get_CF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JNB_Jw(bxInstruction_c *i)
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{
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if (! get_CF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JZ_Jw(bxInstruction_c *i)
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{
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if (get_ZF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JNZ_Jw(bxInstruction_c *i)
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{
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if (! get_ZF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JBE_Jw(bxInstruction_c *i)
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{
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if (get_CF() || get_ZF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JNBE_Jw(bxInstruction_c *i)
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{
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if (! (get_CF() || get_ZF())) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JS_Jw(bxInstruction_c *i)
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{
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if (get_SF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JNS_Jw(bxInstruction_c *i)
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{
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if (! get_SF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JP_Jw(bxInstruction_c *i)
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{
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if (get_PF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JNP_Jw(bxInstruction_c *i)
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{
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if (! get_PF()) {
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Bit16u new_IP = IP + i->Iw();
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branch_near16(new_IP);
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BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
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BX_NEXT_TRACE(i);
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}
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BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
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BX_NEXT_INSTR(i); // trace can continue over non-taken branch
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JL_Jw(bxInstruction_c *i)
|
|
{
|
|
if (getB_SF() != getB_OF()) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
BX_NEXT_INSTR(i); // trace can continue over non-taken branch
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JNL_Jw(bxInstruction_c *i)
|
|
{
|
|
if (getB_SF() == getB_OF()) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
BX_NEXT_INSTR(i); // trace can continue over non-taken branch
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JLE_Jw(bxInstruction_c *i)
|
|
{
|
|
if (get_ZF() || (getB_SF() != getB_OF())) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
BX_NEXT_INSTR(i); // trace can continue over non-taken branch
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JNLE_Jw(bxInstruction_c *i)
|
|
{
|
|
if (! get_ZF() && (getB_SF() == getB_OF())) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
BX_NEXT_INSTR(i); // trace can continue over non-taken branch
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EwR(bxInstruction_c *i)
|
|
{
|
|
Bit16u new_IP = BX_READ_16BIT_REG(i->dst());
|
|
branch_near16(new_IP);
|
|
BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP_INDIRECT, PREV_RIP, new_IP);
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
/* Far indirect jump */
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP16_Ep(bxInstruction_c *i)
|
|
{
|
|
Bit16u cs_raw;
|
|
Bit16u op1_16;
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
|
|
|
op1_16 = read_virtual_word(i->seg(), eaddr);
|
|
cs_raw = read_virtual_word(i->seg(), (eaddr+2) & i->asize_mask());
|
|
|
|
// jump_protected doesn't affect RSP so it is RSP safe
|
|
if (protected_mode()) {
|
|
jump_protected(i, cs_raw, op1_16);
|
|
goto done;
|
|
}
|
|
|
|
// CS.LIMIT can't change when in real/v8086 mode
|
|
if (op1_16 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
|
|
BX_ERROR(("JMP16_Ep: instruction pointer not within code segment limits"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
|
|
EIP = op1_16;
|
|
|
|
done:
|
|
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP_INDIRECT,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::IRET16(bxInstruction_c *i)
|
|
{
|
|
invalidate_prefetch_q();
|
|
|
|
#if BX_SUPPORT_VMX
|
|
if (!BX_CPU_THIS_PTR in_vmx_guest || !VMEXIT(VMX_VM_EXEC_CTRL1_NMI_VMEXIT))
|
|
#endif
|
|
BX_CPU_THIS_PTR disable_NMI = 0;
|
|
|
|
#if BX_DEBUGGER
|
|
BX_CPU_THIS_PTR show_flag |= Flag_iret;
|
|
#endif
|
|
|
|
if (protected_mode()) {
|
|
iret_protected(i);
|
|
goto done;
|
|
}
|
|
|
|
RSP_SPECULATIVE;
|
|
|
|
if (v8086_mode()) {
|
|
// IOPL check in stack_return_from_v86()
|
|
iret16_stack_return_from_v86(i);
|
|
}
|
|
else {
|
|
Bit16u ip = pop_16();
|
|
Bit16u cs_raw = pop_16(); // #SS has higher priority
|
|
Bit16u flags = pop_16();
|
|
|
|
// CS.LIMIT can't change when in real/v8086 mode
|
|
if(ip > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
|
|
BX_ERROR(("IRET16: instruction pointer not within code segment limits"));
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
}
|
|
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
|
|
EIP = (Bit32u) ip;
|
|
write_flags(flags, /* change IOPL? */ 1, /* change IF? */ 1);
|
|
}
|
|
|
|
RSP_COMMIT;
|
|
|
|
done:
|
|
|
|
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_IRET,
|
|
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::JCXZ_Jb(bxInstruction_c *i)
|
|
{
|
|
// it is impossible to get this instruction in long mode
|
|
BX_ASSERT(i->as64L() == 0);
|
|
|
|
Bit32u temp_ECX;
|
|
|
|
if (i->as32L())
|
|
temp_ECX = ECX;
|
|
else
|
|
temp_ECX = CX;
|
|
|
|
if (temp_ECX == 0) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
}
|
|
#if BX_INSTRUMENTATION
|
|
else {
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
}
|
|
#endif
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
//
|
|
// There is some weirdness in LOOP instructions definition. If an exception
|
|
// was generated during the instruction execution (for example #GP fault
|
|
// because EIP was beyond CS segment limits) CPU state should restore the
|
|
// state prior to instruction execution.
|
|
//
|
|
// The final point that we are not allowed to decrement ECX register before
|
|
// it is known that no exceptions can happen.
|
|
//
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOOPNE16_Jb(bxInstruction_c *i)
|
|
{
|
|
// it is impossible to get this instruction in long mode
|
|
BX_ASSERT(i->as64L() == 0);
|
|
|
|
if (i->as32L()) {
|
|
Bit32u count = ECX;
|
|
|
|
count--;
|
|
if (count != 0 && (get_ZF()==0)) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
}
|
|
#if BX_INSTRUMENTATION
|
|
else {
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
}
|
|
#endif
|
|
|
|
ECX = count;
|
|
}
|
|
else {
|
|
Bit16u count = CX;
|
|
|
|
count--;
|
|
if (count != 0 && (get_ZF()==0)) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
}
|
|
#if BX_INSTRUMENTATION
|
|
else {
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
}
|
|
#endif
|
|
|
|
CX = count;
|
|
}
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOOPE16_Jb(bxInstruction_c *i)
|
|
{
|
|
// it is impossible to get this instruction in long mode
|
|
BX_ASSERT(i->as64L() == 0);
|
|
|
|
if (i->as32L()) {
|
|
Bit32u count = ECX;
|
|
|
|
count--;
|
|
if (count != 0 && get_ZF()) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
}
|
|
#if BX_INSTRUMENTATION
|
|
else {
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
}
|
|
#endif
|
|
|
|
ECX = count;
|
|
}
|
|
else {
|
|
Bit16u count = CX;
|
|
|
|
count--;
|
|
if (count != 0 && get_ZF()) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
}
|
|
#if BX_INSTRUMENTATION
|
|
else {
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
}
|
|
#endif
|
|
|
|
CX = count;
|
|
}
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOOP16_Jb(bxInstruction_c *i)
|
|
{
|
|
// it is impossible to get this instruction in long mode
|
|
BX_ASSERT(i->as64L() == 0);
|
|
|
|
if (i->as32L()) {
|
|
Bit32u count = ECX;
|
|
|
|
count--;
|
|
if (count != 0) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
}
|
|
#if BX_INSTRUMENTATION
|
|
else {
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
}
|
|
#endif
|
|
|
|
ECX = count;
|
|
}
|
|
else {
|
|
Bit16u count = CX;
|
|
|
|
count--;
|
|
if (count != 0) {
|
|
Bit16u new_IP = IP + i->Iw();
|
|
branch_near16(new_IP);
|
|
BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, PREV_RIP, new_IP);
|
|
}
|
|
#if BX_INSTRUMENTATION
|
|
else {
|
|
BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID, PREV_RIP);
|
|
}
|
|
#endif
|
|
|
|
CX = count;
|
|
}
|
|
|
|
BX_NEXT_TRACE(i);
|
|
}
|