cc694377b9
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore. Use generic source/destination indications like SRC1, SRC2 and DST. All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly. Immediate benefits: - Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example) - Simpler to understand fetch-decode code Future benefits: - Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned) Huge patch. Almost all source files wre modified.
506 lines
11 KiB
C++
506 lines
11 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2012 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EbR(bxInstruction_c *i)
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{
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unsigned count;
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unsigned bit0, bit7;
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if (i->getIaOpcode() == BX_IA_ROL_Eb)
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count = CL;
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else
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count = i->Ib();
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Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
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if ((count & 0x07) == 0) {
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if (count & 0x18) {
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bit0 = (op1_8 & 1);
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bit7 = (op1_8 >> 7);
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SET_FLAGS_OxxxxC(bit0 ^ bit7, bit0);
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}
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}
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else {
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count &= 0x7; // use only lowest 3 bits
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Bit8u result_8 = (op1_8 << count) | (op1_8 >> (8 - count));
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
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/* set eflags:
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* ROL count affects the following flags: C, O
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*/
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bit0 = (result_8 & 1);
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bit7 = (result_8 >> 7);
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SET_FLAGS_OxxxxC(bit0 ^ bit7, bit0);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EbM(bxInstruction_c *i)
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{
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unsigned count;
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unsigned bit0, bit7;
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if (i->getIaOpcode() == BX_IA_ROL_Eb)
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count = CL;
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else
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count = i->Ib();
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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Bit8u op1_8 = read_RMW_virtual_byte(i->seg(), eaddr);
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if ((count & 0x07) == 0) {
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if (count & 0x18) {
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bit0 = (op1_8 & 1);
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bit7 = (op1_8 >> 7);
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SET_FLAGS_OxxxxC(bit0 ^ bit7, bit0);
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}
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}
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else {
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count &= 0x7; // use only lowest 3 bits
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Bit8u result_8 = (op1_8 << count) | (op1_8 >> (8 - count));
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write_RMW_virtual_byte(result_8);
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/* set eflags:
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* ROL count affects the following flags: C, O
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*/
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bit0 = (result_8 & 1);
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bit7 = (result_8 >> 7);
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SET_FLAGS_OxxxxC(bit0 ^ bit7, bit0);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EbR(bxInstruction_c *i)
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{
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unsigned count;
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unsigned bit6, bit7;
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if (i->getIaOpcode() == BX_IA_ROR_Eb)
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count = CL;
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else
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count = i->Ib();
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Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
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if ((count & 0x07) == 0) {
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if (count & 0x18) {
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bit6 = (op1_8 >> 6) & 1;
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bit7 = (op1_8 >> 7) & 1;
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SET_FLAGS_OxxxxC(bit6 ^ bit7, bit7);
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}
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}
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else {
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count &= 0x7; /* use only bottom 3 bits */
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Bit8u result_8 = (op1_8 >> count) | (op1_8 << (8 - count));
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
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/* set eflags:
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* ROR count affects the following flags: C, O
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*/
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bit6 = (result_8 >> 6) & 1;
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bit7 = (result_8 >> 7) & 1;
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SET_FLAGS_OxxxxC(bit6 ^ bit7, bit7);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EbM(bxInstruction_c *i)
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{
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unsigned count;
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unsigned bit6, bit7;
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if (i->getIaOpcode() == BX_IA_ROR_Eb)
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count = CL;
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else
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count = i->Ib();
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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Bit8u op1_8 = read_RMW_virtual_byte(i->seg(), eaddr);
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if ((count & 0x07) == 0) {
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if (count & 0x18) {
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bit6 = (op1_8 >> 6) & 1;
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bit7 = (op1_8 >> 7) & 1;
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SET_FLAGS_OxxxxC(bit6 ^ bit7, bit7);
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}
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}
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else {
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count &= 0x7; /* use only bottom 3 bits */
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Bit8u result_8 = (op1_8 >> count) | (op1_8 << (8 - count));
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write_RMW_virtual_byte(result_8);
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/* set eflags:
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* ROR count affects the following flags: C, O
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*/
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bit6 = (result_8 >> 6) & 1;
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bit7 = (result_8 >> 7) & 1;
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SET_FLAGS_OxxxxC(bit6 ^ bit7, bit7);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EbR(bxInstruction_c *i)
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{
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Bit8u result_8;
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unsigned count;
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unsigned of, cf;
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if (i->getIaOpcode() == BX_IA_RCL_Eb)
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count = CL;
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else
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count = i->Ib();
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count = (count & 0x1f) % 9;
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if (! count) {
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BX_NEXT_INSTR(i);
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}
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Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
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if (count==1) {
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result_8 = (op1_8 << 1) | getB_CF();
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}
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else {
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result_8 = (op1_8 << count) | (getB_CF() << (count - 1)) |
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(op1_8 >> (9 - count));
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}
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
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cf = (op1_8 >> (8 - count)) & 0x01;
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of = cf ^ (result_8 >> 7); // of = cf ^ result7
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EbM(bxInstruction_c *i)
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{
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Bit8u result_8;
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unsigned count;
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unsigned of, cf;
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if (i->getIaOpcode() == BX_IA_RCL_Eb)
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count = CL;
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else
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count = i->Ib();
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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Bit8u op1_8 = read_RMW_virtual_byte(i->seg(), eaddr);
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count = (count & 0x1f) % 9;
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if (! count) {
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BX_NEXT_INSTR(i);
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}
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if (count==1) {
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result_8 = (op1_8 << 1) | getB_CF();
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}
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else {
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result_8 = (op1_8 << count) | (getB_CF() << (count - 1)) |
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(op1_8 >> (9 - count));
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}
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write_RMW_virtual_byte(result_8);
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cf = (op1_8 >> (8 - count)) & 0x01;
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of = cf ^ (result_8 >> 7); // of = cf ^ result7
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EbR(bxInstruction_c *i)
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{
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unsigned count;
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unsigned cf, of;
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if (i->getIaOpcode() == BX_IA_RCR_Eb)
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count = CL;
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else
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count = i->Ib();
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count = (count & 0x1f) % 9;
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if (count) {
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Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
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Bit8u result_8 = (op1_8 >> count) | (getB_CF() << (8 - count)) |
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(op1_8 << (9 - count));
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
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cf = (op1_8 >> (count - 1)) & 0x1;
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of = (((result_8 << 1) ^ result_8) >> 7) & 0x1; // of = result6 ^ result7
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EbM(bxInstruction_c *i)
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{
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unsigned count;
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unsigned cf, of;
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if (i->getIaOpcode() == BX_IA_RCR_Eb)
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count = CL;
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else
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count = i->Ib();
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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Bit8u op1_8 = read_RMW_virtual_byte(i->seg(), eaddr);
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count = (count & 0x1f) % 9;
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if (count) {
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Bit8u result_8 = (op1_8 >> count) | (getB_CF() << (8 - count)) |
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(op1_8 << (9 - count));
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write_RMW_virtual_byte(result_8);
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cf = (op1_8 >> (count - 1)) & 0x1;
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of = (((result_8 << 1) ^ result_8) >> 7) & 0x1; // of = result6 ^ result7
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EbR(bxInstruction_c *i)
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{
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Bit8u result_8;
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unsigned count;
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unsigned of = 0, cf = 0;
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if (i->getIaOpcode() == BX_IA_SHL_Eb)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (!count) {
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BX_NEXT_INSTR(i);
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}
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Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
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if (count <= 8) {
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result_8 = (op1_8 << count);
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cf = (op1_8 >> (8 - count)) & 0x1;
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of = cf ^ (result_8 >> 7);
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}
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else {
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result_8 = 0;
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}
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
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SET_FLAGS_OSZAPC_LOGIC_8(result_8);
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EbM(bxInstruction_c *i)
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{
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Bit8u result_8;
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unsigned count;
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unsigned of = 0, cf = 0;
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if (i->getIaOpcode() == BX_IA_SHL_Eb)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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Bit8u op1_8 = read_RMW_virtual_byte(i->seg(), eaddr);
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if (!count) {
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BX_NEXT_INSTR(i);
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}
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if (count <= 8) {
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result_8 = (op1_8 << count);
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cf = (op1_8 >> (8 - count)) & 0x1;
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of = cf ^ (result_8 >> 7);
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}
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else {
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result_8 = 0;
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}
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write_RMW_virtual_byte(result_8);
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SET_FLAGS_OSZAPC_LOGIC_8(result_8);
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SET_FLAGS_OxxxxC(of, cf);
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EbR(bxInstruction_c *i)
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{
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unsigned count;
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if (i->getIaOpcode() == BX_IA_SHR_Eb)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (count) {
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Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
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Bit8u result_8 = (op1_8 >> count);
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
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unsigned cf = (op1_8 >> (count - 1)) & 0x1;
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// note, that of == result7 if count == 1 and
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// of == 0 if count >= 2
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unsigned of = (((result_8 << 1) ^ result_8) >> 7) & 0x1;
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SET_FLAGS_OSZAPC_LOGIC_8(result_8);
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EbM(bxInstruction_c *i)
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{
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unsigned count;
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if (i->getIaOpcode() == BX_IA_SHR_Eb)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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Bit8u op1_8 = read_RMW_virtual_byte(i->seg(), eaddr);
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if (count) {
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Bit8u result_8 = (op1_8 >> count);
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write_RMW_virtual_byte(result_8);
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unsigned cf = (op1_8 >> (count - 1)) & 0x1;
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// note, that of == result7 if count == 1 and
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// of == 0 if count >= 2
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unsigned of = (((result_8 << 1) ^ result_8) >> 7) & 0x1;
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SET_FLAGS_OSZAPC_LOGIC_8(result_8);
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SET_FLAGS_OxxxxC(of, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EbR(bxInstruction_c *i)
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{
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unsigned count;
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if (i->getIaOpcode() == BX_IA_SAR_Eb)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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if (count) {
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Bit8u op1_8 = BX_READ_8BIT_REGx(i->dst(), i->extend8bitL());
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Bit8u result_8 = ((Bit8s) op1_8) >> count;
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BX_WRITE_8BIT_REGx(i->dst(), i->extend8bitL(), result_8);
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unsigned cf = (((Bit8s) op1_8) >> (count - 1)) & 0x1;
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SET_FLAGS_OSZAPC_LOGIC_8(result_8);
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/* signed overflow cannot happen in SAR instruction */
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SET_FLAGS_OxxxxC(0, cf);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EbM(bxInstruction_c *i)
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{
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unsigned count;
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if (i->getIaOpcode() == BX_IA_SAR_Eb)
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count = CL;
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else
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count = i->Ib();
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count &= 0x1f;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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Bit8u op1_8 = read_RMW_virtual_byte(i->seg(), eaddr);
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if (count) {
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Bit8u result_8 = ((Bit8s) op1_8) >> count;
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write_RMW_virtual_byte(result_8);
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unsigned cf = (((Bit8s) op1_8) >> (count - 1)) & 0x1;
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SET_FLAGS_OSZAPC_LOGIC_8(result_8);
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/* signed overflow cannot happen in SAR instruction */
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SET_FLAGS_OxxxxC(0, cf);
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}
|
|
|
|
BX_NEXT_INSTR(i);
|
|
}
|