cc694377b9
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore. Use generic source/destination indications like SRC1, SRC2 and DST. All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly. Immediate benefits: - Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example) - Simpler to understand fetch-decode code Future benefits: - Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned) Huge patch. Almost all source files wre modified.
750 lines
23 KiB
C++
750 lines
23 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2009-2012 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_VMX
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// BX_READ(0) form means nnn(), rm(); BX_WRITE(1) form means rm(), nnn()
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Bit32u gen_instruction_info(bxInstruction_c *i, Bit32u reason, bx_bool rw_form)
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{
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Bit32u instr_info = 0;
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switch(reason) {
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case VMX_VMEXIT_VMREAD:
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case VMX_VMEXIT_VMWRITE:
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#if BX_SUPPORT_VMX >= 2
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case VMX_VMEXIT_GDTR_IDTR_ACCESS:
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case VMX_VMEXIT_LDTR_TR_ACCESS:
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case VMX_VMEXIT_INVEPT:
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case VMX_VMEXIT_INVVPID:
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case VMX_VMEXIT_INVPCID:
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#endif
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if (rw_form == BX_READ)
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instr_info = i->dst() << 28;
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else
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instr_info = i->src() << 28;
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break;
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default:
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break;
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}
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// --------------------------------------
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// instruction information field format
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// --------------------------------------
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//
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// [.2:.0] | Memory operand scale field (encoded)
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// [.6:.3] | Reg1, undefined when memory operand
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// [.9:.7] | Memory operand address size
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// [10:10] | Memory/Register format (0 - mem, 1 - reg)
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// [14:11] | Reserved
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// [17:15] | Memory operand segment register field
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// [21:18] | Memory operand index field
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// [22:22] | Memory operand index field invalid
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// [26:23] | Memory operand base field
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// [27:27] | Memory operand base field invalid
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// [31:28] | Reg2, if exists
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//
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if (i->modC0()) {
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// reg/reg format
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instr_info |= (1 << 10);
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if (rw_form == BX_READ)
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instr_info = i->src() << 3;
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else
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instr_info = i->dst() << 3;
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}
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else {
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// memory format
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if (i->as64L())
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instr_info |= 1 << 8;
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else if (i->as32L())
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instr_info |= 1 << 7;
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instr_info |= i->seg() << 15;
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if (i->sibIndex() != BX_NIL_REGISTER)
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instr_info |= i->sibScale() | (i->sibIndex() << 18);
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else
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instr_info |= 1 << 22; // index invalid
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if (i->sibBase() != BX_NIL_REGISTER)
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instr_info |= i->sibBase() << 23;
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else
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instr_info |= 1 << 27; // base invalid
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}
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return instr_info;
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}
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void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_Instruction(bxInstruction_c *i, Bit32u reason, bx_bool rw_form)
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{
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Bit64u qualification = 0;
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Bit32u instr_info = 0;
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switch(reason) {
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case VMX_VMEXIT_VMREAD:
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case VMX_VMEXIT_VMWRITE:
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case VMX_VMEXIT_VMPTRLD:
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case VMX_VMEXIT_VMPTRST:
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case VMX_VMEXIT_VMCLEAR:
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case VMX_VMEXIT_VMXON:
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#if BX_SUPPORT_VMX >= 2
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case VMX_VMEXIT_GDTR_IDTR_ACCESS:
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case VMX_VMEXIT_LDTR_TR_ACCESS:
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case VMX_VMEXIT_INVEPT:
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case VMX_VMEXIT_INVVPID:
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#endif
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#if BX_SUPPORT_X86_64
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if (long64_mode()) {
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qualification = (Bit64u) i->displ32s();
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if (i->sibBase() == BX_64BIT_REG_RIP)
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qualification += RIP;
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}
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else
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#endif
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qualification = (Bit64u) ((Bit32u) i->displ32s());
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instr_info = gen_instruction_info(i, reason, rw_form);
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VMwrite32(VMCS_32BIT_VMEXIT_INSTRUCTION_INFO, instr_info);
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break;
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default:
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BX_PANIC(("VMexit_Instruction reason %d", reason));
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}
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VMexit(reason, qualification);
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}
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void BX_CPU_C::VMexit_PAUSE(void)
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{
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BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
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if (VMEXIT(VMX_VM_EXEC_CTRL2_PAUSE_VMEXIT)) {
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BX_DEBUG(("VMEXIT: PAUSE"));
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VMexit(VMX_VMEXIT_PAUSE, 0);
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}
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#if BX_SUPPORT_VMX >= 2
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if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_PAUSE_LOOP_VMEXIT) && CPL == 0) {
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VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
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Bit64u currtime = bx_pc_system.time_ticks();
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if ((currtime - vm->last_pause_time) > vm->pause_loop_exiting_gap) {
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vm->first_pause_time = currtime;
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}
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else {
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if ((currtime - vm->first_pause_time) > vm->pause_loop_exiting_window)
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VMexit(VMX_VMEXIT_PAUSE, 0);
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}
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vm->last_pause_time = currtime;
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}
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#endif
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}
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void BX_CPU_C::VMexit_ExtInterrupt(void)
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{
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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if (PIN_VMEXIT(VMX_VM_EXEC_CTRL1_EXTERNAL_INTERRUPT_VMEXIT)) {
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VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
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if (! (vm->vmexit_ctrls & VMX_VMEXIT_CTRL1_INTA_ON_VMEXIT)) {
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// interrupt wasn't acknowledged and still pending, interruption info is invalid
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VMwrite32(VMCS_32BIT_VMEXIT_INTERRUPTION_INFO, 0);
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VMexit(VMX_VMEXIT_EXTERNAL_INTERRUPT, 0);
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}
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}
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}
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#if BX_SUPPORT_VMX >= 2
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void BX_CPU_C::VMexit_PreemptionTimerExpired(void)
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{
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BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
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if (PIN_VMEXIT(VMX_VM_EXEC_CTRL1_VMX_PREEMPTION_TIMER_VMEXIT)) {
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BX_DEBUG(("VMEXIT: VMX Preemption Timer Expired"));
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VMexit(VMX_VMEXIT_VMX_PREEMPTION_TIMER_EXPIRED, 0);
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}
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}
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#endif
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void BX_CPU_C::VMexit_Event(unsigned type, unsigned vector, Bit16u errcode, bx_bool errcode_valid, Bit64u qualification)
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{
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
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bx_bool vmexit = 0;
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VMX_vmexit_reason reason = VMX_VMEXIT_EXCEPTION_NMI;
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switch(type) {
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case BX_EXTERNAL_INTERRUPT:
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reason = VMX_VMEXIT_EXTERNAL_INTERRUPT;
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if (PIN_VMEXIT(VMX_VM_EXEC_CTRL1_EXTERNAL_INTERRUPT_VMEXIT))
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vmexit = 1;
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break;
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case BX_NMI:
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if (PIN_VMEXIT(VMX_VM_EXEC_CTRL1_NMI_VMEXIT))
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vmexit = 1;
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break;
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case BX_PRIVILEGED_SOFTWARE_INTERRUPT:
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case BX_SOFTWARE_EXCEPTION:
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case BX_HARDWARE_EXCEPTION:
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BX_ASSERT(vector < BX_CPU_HANDLED_EXCEPTIONS);
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if (vector == BX_PF_EXCEPTION) {
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// page faults are specially treated
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bx_bool err_match = ((errcode & vm->vm_pf_mask) == vm->vm_pf_match);
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bx_bool bitmap = (vm->vm_exceptions_bitmap >> BX_PF_EXCEPTION) & 1;
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vmexit = (err_match == bitmap);
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}
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else {
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vmexit = (vm->vm_exceptions_bitmap >> vector) & 1;
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}
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break;
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case BX_SOFTWARE_INTERRUPT:
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break; // no VMEXIT on software interrupt
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default:
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BX_ERROR(("VMexit_Event: unknown event type %d", type));
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}
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// ----------------------------------------------------
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// VMExit interruption info
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// ----------------------------------------------------
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// [.7:.0] | Interrupt/Exception vector
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// [10:.8] | Interrupt/Exception type
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// [11:11] | error code pushed to the stack
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// [12:12] | NMI unblocking due to IRET
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// [30:13] | reserved
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// [31:31] | interruption info valid
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//
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if (! vmexit) {
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// record IDT vectoring information
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vm->idt_vector_error_code = errcode;
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vm->idt_vector_info = vector | (type << 8);
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if (errcode_valid)
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vm->idt_vector_info |= (1 << 11); // error code delivered
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return;
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}
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BX_DEBUG(("VMEXIT: event vector 0x%02x type %d error code=0x%04x", vector, type, errcode));
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// VMEXIT is not considered to occur during event delivery if it results
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// in a double fault exception that causes VMEXIT directly
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if (vector == BX_DF_EXCEPTION)
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BX_CPU_THIS_PTR in_event = 0; // clear in_event indication on #DF
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if (vector == BX_DB_EXCEPTION) {
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// qualifcation for debug exceptions similar to debug_trap field
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qualification = BX_CPU_THIS_PTR debug_trap & 0x0000600f;
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}
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// clear debug_trap field
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BX_CPU_THIS_PTR debug_trap = 0;
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BX_CPU_THIS_PTR inhibit_mask = 0;
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Bit32u interruption_info = vector | (type << 8);
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if (errcode_valid)
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interruption_info |= (1 << 11); // error code delivered
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interruption_info |= (1 << 31); // valid
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VMwrite32(VMCS_32BIT_VMEXIT_INTERRUPTION_INFO, interruption_info);
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VMwrite32(VMCS_32BIT_VMEXIT_INTERRUPTION_ERR_CODE, errcode);
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VMexit(reason, qualification);
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}
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void BX_CPU_C::VMexit_TripleFault(void)
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{
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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BX_ERROR(("VMEXIT: triple fault"));
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// VMEXIT is not considered to occur during event delivery if it results
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// in a triple fault exception (that causes VMEXIT directly)
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BX_CPU_THIS_PTR in_event = 0;
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VMexit(VMX_VMEXIT_TRIPLE_FAULT, 0);
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}
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_TaskSwitch(Bit16u tss_selector, unsigned source)
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{
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BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
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BX_ERROR(("VMEXIT: task switch"));
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VMexit(VMX_VMEXIT_TASK_SWITCH, tss_selector | (source << 30));
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}
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#define BX_VMX_LO_MSR_START 0x00000000
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#define BX_VMX_LO_MSR_END 0x00001FFF
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#define BX_VMX_HI_MSR_START 0xC0000000
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#define BX_VMX_HI_MSR_END 0xC0001FFF
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_MSR(unsigned op, Bit32u msr)
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{
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BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
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bx_bool vmexit = 0;
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if (! VMEXIT(VMX_VM_EXEC_CTRL2_MSR_BITMAPS)) vmexit = 1;
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else {
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VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
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Bit8u field;
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if (msr >= BX_VMX_HI_MSR_START) {
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if (msr > BX_VMX_HI_MSR_END) vmexit = 1;
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else {
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// check MSR-HI bitmaps
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bx_phy_address pAddr = vm->msr_bitmap_addr + ((msr - BX_VMX_HI_MSR_START) >> 3) + 1024 + ((op == VMX_VMEXIT_RDMSR) ? 0 : 2048);
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access_read_physical(pAddr, 1, &field);
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BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_MSR_BITMAP_ACCESS, &field);
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if (field & (1 << (msr & 7)))
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vmexit = 1;
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}
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}
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else {
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if (msr > BX_VMX_LO_MSR_END) vmexit = 1;
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else {
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// check MSR-LO bitmaps
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bx_phy_address pAddr = vm->msr_bitmap_addr + (msr >> 3) + ((op == VMX_VMEXIT_RDMSR) ? 0 : 2048);
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access_read_physical(pAddr, 1, &field);
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BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_MSR_BITMAP_ACCESS, &field);
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if (field & (1 << (msr & 7)))
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vmexit = 1;
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}
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}
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}
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if (vmexit) {
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BX_DEBUG(("VMEXIT: %sMSR 0x%08x", (op == VMX_VMEXIT_RDMSR) ? "RD" : "WR", msr));
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VMexit(op, 0);
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}
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}
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#define VMX_VMEXIT_IO_PORTIN (1 << 3)
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#define VMX_VMEXIT_IO_INSTR_STRING (1 << 4)
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#define VMX_VMEXIT_IO_INSTR_REP (1 << 5)
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#define VMX_VMEXIT_IO_INSTR_IMM (1 << 6)
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void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_IO(bxInstruction_c *i, unsigned port, unsigned len)
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{
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BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
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BX_ASSERT(port <= 0xFFFF);
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bool vmexit = 0;
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if (VMEXIT(VMX_VM_EXEC_CTRL2_IO_BITMAPS)) {
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// always VMEXIT on port "wrap around" case
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if ((port + len) > 0x10000) vmexit = 1;
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else {
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Bit8u bitmap[2];
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bx_phy_address pAddr;
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if ((port & 0x7fff) + len > 0x8000) {
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// special case - the IO access split cross both I/O bitmaps
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pAddr = BX_CPU_THIS_PTR vmcs.io_bitmap_addr[0] + 0xfff;
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access_read_physical(pAddr, 1, &bitmap[0]);
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BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[0]);
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pAddr = BX_CPU_THIS_PTR vmcs.io_bitmap_addr[1];
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access_read_physical(pAddr, 1, &bitmap[1]);
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BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[1]);
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}
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else {
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// access_read_physical cannot read 2 bytes cross 4K boundary :(
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pAddr = BX_CPU_THIS_PTR vmcs.io_bitmap_addr[(port >> 15) & 1] + ((port & 0x7fff) / 8);
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access_read_physical(pAddr, 1, &bitmap[0]);
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BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[0]);
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pAddr++;
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access_read_physical(pAddr, 1, &bitmap[1]);
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BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[1]);
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}
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Bit16u combined_bitmap = bitmap[1];
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combined_bitmap = (combined_bitmap << 8) | bitmap[0];
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unsigned mask = ((1 << len) - 1) << (port & 7);
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if (combined_bitmap & mask) vmexit = 1;
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}
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}
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else if (VMEXIT(VMX_VM_EXEC_CTRL2_IO_VMEXIT)) vmexit = 1;
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if (vmexit) {
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BX_DEBUG(("VMEXIT: I/O port 0x%04x", port));
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Bit32u qualification = 0;
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switch(i->getIaOpcode()) {
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case BX_IA_IN_ALIb:
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case BX_IA_IN_AXIb:
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case BX_IA_IN_EAXIb:
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qualification = VMX_VMEXIT_IO_PORTIN | VMX_VMEXIT_IO_INSTR_IMM;
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break;
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case BX_IA_OUT_IbAL:
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case BX_IA_OUT_IbAX:
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case BX_IA_OUT_IbEAX:
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qualification = VMX_VMEXIT_IO_INSTR_IMM;
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break;
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case BX_IA_IN_ALDX:
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case BX_IA_IN_AXDX:
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case BX_IA_IN_EAXDX:
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qualification = VMX_VMEXIT_IO_PORTIN; // no immediate
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break;
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case BX_IA_OUT_DXAL:
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case BX_IA_OUT_DXAX:
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case BX_IA_OUT_DXEAX:
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qualification = 0; // PORTOUT, no immediate
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break;
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case BX_IA_REP_INSB_YbDX:
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case BX_IA_REP_INSW_YwDX:
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case BX_IA_REP_INSD_YdDX:
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qualification = VMX_VMEXIT_IO_PORTIN | VMX_VMEXIT_IO_INSTR_STRING;
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if (i->repUsedL())
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qualification |= VMX_VMEXIT_IO_INSTR_REP;
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break;
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case BX_IA_REP_OUTSB_DXXb:
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case BX_IA_REP_OUTSW_DXXw:
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case BX_IA_REP_OUTSD_DXXd:
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qualification = VMX_VMEXIT_IO_INSTR_STRING; // PORTOUT
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if (i->repUsedL())
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qualification |= VMX_VMEXIT_IO_INSTR_REP;
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break;
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default:
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BX_PANIC(("VMexit_IO: I/O instruction %s unknown", i->getIaOpcodeName()));
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}
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|
|
if (qualification & VMX_VMEXIT_IO_INSTR_STRING) {
|
|
bx_address asize_mask = (bx_address) i->asize_mask(), laddr;
|
|
|
|
if (qualification & VMX_VMEXIT_IO_PORTIN)
|
|
laddr = get_laddr(BX_SEG_REG_ES, RDI & asize_mask);
|
|
else // PORTOUT
|
|
laddr = get_laddr(i->seg(), RSI & asize_mask);
|
|
|
|
VMwrite_natural(VMCS_GUEST_LINEAR_ADDR, laddr);
|
|
|
|
Bit32u instruction_info = i->seg() << 15;
|
|
if (i->as64L())
|
|
instruction_info |= (1 << 8);
|
|
else if (i->as32L())
|
|
instruction_info |= (1 << 7);
|
|
|
|
VMwrite32(VMCS_32BIT_VMEXIT_INSTRUCTION_INFO, instruction_info);
|
|
}
|
|
|
|
VMexit(VMX_VMEXIT_IO_INSTRUCTION, qualification | (len-1) | (port << 16));
|
|
}
|
|
}
|
|
|
|
//
|
|
// ----------------------------------------------------------------
|
|
// Exit qualification for CR access
|
|
// ----------------------------------------------------------------
|
|
// [.3:.0] | Number of CR register (CR0, CR3, CR4, CR8)
|
|
// [.5:.4] | CR access type (0 - MOV to CR, 1 - MOV from CR, 2 - CLTS, 3 - LMSW)
|
|
// [.6:.6] | LMSW operand reg/mem (cleared for CR access and CLTS)
|
|
// [.7:.7] | reserved
|
|
// [11:.8] | Source Operand Register for CR access (cleared for CLTS and LMSW)
|
|
// [15:12] | reserved
|
|
// [31:16] | LMSW source data (cleared for CR access and CLTS)
|
|
// [63:32] | reserved
|
|
//
|
|
|
|
bx_bool BX_CPU_C::VMexit_CLTS(void)
|
|
{
|
|
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
|
|
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
|
|
if (vm->vm_cr0_mask & vm->vm_cr0_read_shadow & 0x8)
|
|
{
|
|
BX_DEBUG(("VMEXIT: CLTS"));
|
|
|
|
// all rest of the fields cleared to zero
|
|
Bit64u qualification = VMX_VMEXIT_CR_ACCESS_CLTS << 4;
|
|
|
|
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
|
|
}
|
|
|
|
if ((vm->vm_cr0_mask & 0x8) != 0 && (vm->vm_cr0_read_shadow & 0x8) == 0)
|
|
return 1; /* do not clear CR0.TS */
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
Bit32u BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_LMSW(bxInstruction_c *i, Bit32u msw)
|
|
{
|
|
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
|
|
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
Bit32u mask = vm->vm_cr0_mask & 0xF; /* LMSW affects only low 4 bits */
|
|
bx_bool vmexit = 0;
|
|
|
|
if ((mask & msw & 0x1) != 0 && (vm->vm_cr0_read_shadow & 0x1) == 0)
|
|
vmexit = 1;
|
|
|
|
if ((mask & vm->vm_cr0_read_shadow & 0xE) != (mask & msw & 0xE))
|
|
vmexit = 1;
|
|
|
|
if (vmexit) {
|
|
BX_DEBUG(("VMEXIT: CR0 write by LMSW of value 0x%04x", msw));
|
|
|
|
Bit64u qualification = VMX_VMEXIT_CR_ACCESS_LMSW << 4;
|
|
qualification |= msw << 16;
|
|
if (! i->modC0()) {
|
|
qualification |= (1 << 6); // memory operand
|
|
VMwrite_natural(VMCS_GUEST_LINEAR_ADDR, get_laddr(i->seg(), RMAddr(i)));
|
|
}
|
|
|
|
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
|
|
}
|
|
|
|
// keep untouched all the bits set in CR0 mask
|
|
return (BX_CPU_THIS_PTR cr0.get32() & mask) | (msw & ~mask);
|
|
}
|
|
|
|
bx_address BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_CR0_Write(bxInstruction_c *i, bx_address val)
|
|
{
|
|
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
|
|
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
|
|
if ((vm->vm_cr0_mask & vm->vm_cr0_read_shadow) != (vm->vm_cr0_mask & val))
|
|
{
|
|
BX_DEBUG(("VMEXIT: CR0 write"));
|
|
Bit64u qualification = i->src() << 8;
|
|
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
|
|
}
|
|
|
|
// keep untouched all the bits set in CR0 mask
|
|
return (BX_CPU_THIS_PTR cr0.get32() & vm->vm_cr0_mask) | (val & ~vm->vm_cr0_mask);
|
|
}
|
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CR3_Read(bxInstruction_c *i)
|
|
{
|
|
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
|
|
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR3_READ_VMEXIT)) {
|
|
BX_DEBUG(("VMEXIT: CR3 read"));
|
|
|
|
Bit64u qualification = 3 | (VMX_VMEXIT_CR_ACCESS_CR_READ << 4) | (i->dst() << 8);
|
|
|
|
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
|
|
}
|
|
}
|
|
|
|
void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_CR3_Write(bxInstruction_c *i, bx_address val)
|
|
{
|
|
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
|
|
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR3_WRITE_VMEXIT)) {
|
|
for (unsigned n=0; n < vm->vm_cr3_target_cnt; n++) {
|
|
if (vm->vm_cr3_target_value[n] == val) return;
|
|
}
|
|
|
|
BX_DEBUG(("VMEXIT: CR3 write"));
|
|
Bit64u qualification = 3 | (i->src() << 8);
|
|
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
|
|
}
|
|
}
|
|
|
|
bx_address BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_CR4_Write(bxInstruction_c *i, bx_address val)
|
|
{
|
|
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
|
|
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
|
|
if ((vm->vm_cr4_mask & vm->vm_cr4_read_shadow) != (vm->vm_cr4_mask & val))
|
|
{
|
|
BX_DEBUG(("VMEXIT: CR4 write"));
|
|
Bit64u qualification = 4 | (i->src() << 8);
|
|
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
|
|
}
|
|
|
|
// keep untouched all the bits set in CR4 mask
|
|
return (BX_CPU_THIS_PTR cr4.get32() & vm->vm_cr4_mask) | (val & ~vm->vm_cr4_mask);
|
|
}
|
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CR8_Read(bxInstruction_c *i)
|
|
{
|
|
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
|
|
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR8_READ_VMEXIT)) {
|
|
BX_DEBUG(("VMEXIT: CR8 read"));
|
|
|
|
Bit64u qualification = 8 | (VMX_VMEXIT_CR_ACCESS_CR_READ << 4) | (i->dst() << 8);
|
|
|
|
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
|
|
}
|
|
}
|
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CR8_Write(bxInstruction_c *i)
|
|
{
|
|
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
|
|
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR8_WRITE_VMEXIT)) {
|
|
BX_DEBUG(("VMEXIT: CR8 write"));
|
|
Bit64u qualification = 8 | (i->src() << 8);
|
|
VMexit(VMX_VMEXIT_CR_ACCESS, qualification);
|
|
}
|
|
}
|
|
|
|
//
|
|
// ----------------------------------------------------------------
|
|
// Exit qualification for DR access
|
|
// ----------------------------------------------------------------
|
|
// [.3:.0] | Number of DR register
|
|
// [.4:.4] | DR access type (0 - MOV to DR, 1 - MOV from DR)
|
|
// [.7:.5] | reserved
|
|
// [11:.8] | Source Operand Register
|
|
// [63:12] | reserved
|
|
//
|
|
|
|
void BX_CPU_C::VMexit_DR_Access(unsigned read, unsigned dr, unsigned reg)
|
|
{
|
|
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
|
|
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_DRx_ACCESS_VMEXIT))
|
|
{
|
|
BX_DEBUG(("VMEXIT: DR%d %s access", dr, read ? "READ" : "WRITE"));
|
|
|
|
Bit64u qualification = dr | (reg << 8);
|
|
if (read)
|
|
qualification |= (1 << 4);
|
|
|
|
VMexit(VMX_VMEXIT_DR_ACCESS, qualification);
|
|
}
|
|
}
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
Bit32u BX_CPU_C::VMX_Read_VTPR(void)
|
|
{
|
|
bx_phy_address pAddr = BX_CPU_THIS_PTR vmcs.virtual_apic_page_addr + 0x80;
|
|
Bit32u vtpr;
|
|
access_read_physical(pAddr, 4, (Bit8u*)(&vtpr));
|
|
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 4, BX_READ, BX_VMX_VTPR_ACCESS, (Bit8u*)(&vtpr));
|
|
return vtpr;
|
|
}
|
|
|
|
void BX_CPU_C::VMX_Write_VTPR(Bit8u vtpr)
|
|
{
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
bx_phy_address pAddr = vm->virtual_apic_page_addr + 0x80;
|
|
Bit32u field32 = vtpr;
|
|
|
|
access_write_physical(pAddr, 4, (Bit8u*)(&field32));
|
|
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 4, BX_WRITE, BX_VMX_VTPR_ACCESS, (Bit8u*)(&field32));
|
|
|
|
Bit8u tpr_shadow = vtpr >> 4;
|
|
if (tpr_shadow < vm->vm_tpr_threshold) {
|
|
// commit current instruction to produce trap-like VMexit
|
|
BX_CPU_THIS_PTR prev_rip = RIP; // commit new RIP
|
|
VMexit(VMX_VMEXIT_TPR_THRESHOLD, 0);
|
|
}
|
|
}
|
|
|
|
// apic virtualization
|
|
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::is_virtual_apic_page(bx_phy_address paddr)
|
|
{
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_VIRTUALIZE_APIC_ACCESSES))
|
|
if (PPFOf(paddr) == PPFOf(vm->apic_access_page)) return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
// apic virtualization
|
|
void BX_CPU_C::VMX_Virtual_Apic_Read(bx_phy_address paddr, unsigned len, void *data)
|
|
{
|
|
BX_ASSERT(SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_VIRTUALIZE_APIC_ACCESSES));
|
|
|
|
Bit32u offset = PAGE_OFFSET(paddr);
|
|
|
|
// access is not instruction fetch because cpu::prefetch will crash them
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_TPR_SHADOW) && offset == 0x80 && len <= 4) {
|
|
// VTPR access
|
|
Bit32u vtpr = VMX_Read_VTPR();
|
|
if (len == 1)
|
|
*((Bit8u *) data) = vtpr & 0xff;
|
|
else if (len == 2)
|
|
*((Bit16u *) data) = vtpr & 0xffff;
|
|
else if (len == 4)
|
|
*((Bit32u *) data) = vtpr;
|
|
else
|
|
BX_PANIC(("PANIC: Unsupported Virtual APIC access len = 3 !"));
|
|
return;
|
|
}
|
|
|
|
Bit32u qualification = offset |
|
|
(BX_CPU_THIS_PTR in_event) ? VMX_APIC_ACCESS_DURING_EVENT_DELIVERY : VMX_APIC_READ_INSTRUCTION_EXECUTION;
|
|
VMexit(VMX_VMEXIT_APIC_ACCESS, qualification);
|
|
}
|
|
|
|
// apic virtualization
|
|
void BX_CPU_C::VMX_Virtual_Apic_Write(bx_phy_address paddr, unsigned len, void *data)
|
|
{
|
|
BX_ASSERT(SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_VIRTUALIZE_APIC_ACCESSES));
|
|
|
|
Bit32u offset = PAGE_OFFSET(paddr);
|
|
|
|
if (VMEXIT(VMX_VM_EXEC_CTRL2_TPR_SHADOW) && offset == 0x80 && len <= 4) {
|
|
// VTPR access
|
|
VMX_Write_VTPR(*((Bit8u *) data));
|
|
return;
|
|
}
|
|
|
|
Bit32u qualification = offset |
|
|
(BX_CPU_THIS_PTR in_event) ? VMX_APIC_ACCESS_DURING_EVENT_DELIVERY : VMX_APIC_WRITE_INSTRUCTION_EXECUTION;
|
|
VMexit(VMX_VMEXIT_APIC_ACCESS, qualification);
|
|
}
|
|
|
|
#endif
|
|
|
|
#if BX_SUPPORT_VMX >= 2
|
|
Bit16u BX_CPU_C::VMX_Get_Current_VPID(void)
|
|
{
|
|
if (! BX_CPU_THIS_PTR in_vmx_guest || !SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_VPID_ENABLE))
|
|
return 0;
|
|
|
|
return BX_CPU_THIS_PTR vmcs.vpid;
|
|
}
|
|
#endif
|
|
|
|
#endif // BX_SUPPORT_VMX
|