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add new instrumentation callbacks for physical memory access from CPU

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This commit is contained in:
Stanislav Shwartsman 2012-06-18 11:41:26 +00:00
parent 05fe85659a
commit 515d8b5c25
14 changed files with 92 additions and 104 deletions
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3
bochs/CHANGES
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@ -26,7 +26,8 @@ Changes after 2.5.1 release:
debugger and Bochs debugger GUI through param tree interfaces
- Implemented 'writemem' debugger command to dump virtual memory block
starting from selected linear address into a file
- Updated / Fixed instrumentation examples
- Updated definition of instrumentation callbacks, see description in
instrumentation.txt / Fixed instrumentation examples
- Configure and compile
- Moved networking, sound and USB devices to subdirectories in iodev.

4
bochs/bochs.h
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@ -229,8 +229,8 @@ void print_tree(bx_param_c *node, int level = 0);
if (bx_guard.report.io) bx_dbg_io_report(port, size, op, val)
# define BX_DBG_LIN_MEMORY_ACCESS(cpu, lin, phy, len, pl, rw, data) \
bx_dbg_lin_memory_access(cpu, lin, phy, len, pl, rw, data)
# define BX_DBG_PHY_MEMORY_ACCESS(cpu, phy, len, rw, attr, data) \
bx_dbg_phy_memory_access(cpu, phy, len, rw, attr, data)
# define BX_DBG_PHY_MEMORY_ACCESS(cpu, phy, len, rw, why, data) \
bx_dbg_phy_memory_access(cpu, phy, len, rw, why, data)
#else // #if BX_DEBUGGER
// debugger not compiled in, use empty stubs
# define BX_DBG_ASYNC_INTR 1

5
bochs/cpu/cpu.h
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@ -524,6 +524,11 @@ BOCHSAPI extern BX_CPU_C bx_cpu;
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, (laddr), (paddr), (size), (pl), (rw), (dataptr)); \
}
#define BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, size, rw, why, dataptr) { \
BX_INSTR_PHY_ACCESS(BX_CPU_ID, (paddr), (size), (rw)); \
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, (paddr), (size), (rw), (why), (dataptr)); \
}
// accessors for all eflags in bx_flags_reg_t
// The macro is used once for each flag bit
// Do not use for arithmetic flags !

39
bochs/cpu/paging.cc
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@ -706,7 +706,7 @@ bx_phy_address BX_CPU_C::translate_linear_long_mode(bx_address laddr, Bit32u &lp
}
#endif
access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
offset_mask >>= 9;
Bit64u curr_entry = entry[leaf];
@ -768,7 +768,7 @@ void BX_CPU_C::update_access_dirty_PAE(bx_phy_address *entry_addr, Bit64u *entry
if (!(entry[level] & 0x20)) {
entry[level] |= 0x20;
access_write_physical(entry_addr[level], 8, &entry[level]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[level], 8, BX_WRITE,
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[level], 8, BX_WRITE,
(BX_PTE_ACCESS + level), (Bit8u*)(&entry[level]));
}
}
@ -777,7 +777,7 @@ void BX_CPU_C::update_access_dirty_PAE(bx_phy_address *entry_addr, Bit64u *entry
if (!(entry[leaf] & 0x20) || (write && !(entry[leaf] & 0x40))) {
entry[leaf] |= (0x20 | (write<<6)); // Update A and possibly D bits
access_write_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_WRITE,
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_WRITE,
(BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
}
}
@ -821,8 +821,7 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::CheckPDPTR(bx_phy_address cr3_val)
// read and check PDPTE entries
bx_phy_address pdpe_entry_addr = (bx_phy_address) (cr3_val | (n << 3));
access_read_physical(pdpe_entry_addr, 8, &(pdptr[n]));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pdpe_entry_addr, 8, BX_READ,
(BX_PDPTR0_ACCESS + n), (Bit8u*) &(pdptr[n]));
BX_NOTIFY_PHY_MEMORY_ACCESS(pdpe_entry_addr, 8, BX_READ, (BX_PDPTR0_ACCESS + n), (Bit8u*) &(pdptr[n]));
if (pdptr[n] & 0x1) {
if (pdptr[n] & PAGING_PAE_PDPTE_RESERVED_BITS) return 0;
@ -862,8 +861,7 @@ bx_phy_address BX_CPU_C::translate_linear_load_PDPTR(bx_address laddr, unsigned
bx_phy_address pdpe_entry_addr = (bx_phy_address) (cr3_val | (index << 3));
access_read_physical(pdpe_entry_addr, 8, &pdptr);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pdpe_entry_addr, 8, BX_READ,
(BX_PDPTR0_ACCESS + index), (Bit8u*) &pdptr);
BX_NOTIFY_PHY_MEMORY_ACCESS(pdpe_entry_addr, 8, BX_READ, (BX_PDPTR0_ACCESS + index), (Bit8u*) &pdptr);
if (pdptr & 0x1) {
if (pdptr & PAGING_PAE_PDPTE_RESERVED_BITS) {
@ -918,7 +916,7 @@ bx_phy_address BX_CPU_C::translate_linear_PAE(bx_address laddr, Bit32u &lpf_mask
}
#endif
access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
Bit64u curr_entry = entry[leaf];
int fault = check_entry_PAE(bx_paging_level[leaf], curr_entry, reserved, rw, &nx_fault);
@ -1014,7 +1012,7 @@ bx_phy_address BX_CPU_C::translate_linear_legacy(bx_address laddr, Bit32u &lpf_m
}
#endif
access_read_physical(entry_addr[leaf], 4, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 4, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 4, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
Bit32u curr_entry = entry[leaf];
if (!(curr_entry & 0x1)) {
@ -1080,7 +1078,7 @@ void BX_CPU_C::update_access_dirty(bx_phy_address *entry_addr, Bit32u *entry, un
if (!(entry[BX_LEVEL_PDE] & 0x20)) {
entry[BX_LEVEL_PDE] |= 0x20;
access_write_physical(entry_addr[BX_LEVEL_PDE], 4, &entry[BX_LEVEL_PDE]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[BX_LEVEL_PDE], 4, BX_WRITE, BX_PDE_ACCESS, (Bit8u*)(&entry[BX_LEVEL_PDE]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[BX_LEVEL_PDE], 4, BX_WRITE, BX_PDE_ACCESS, (Bit8u*)(&entry[BX_LEVEL_PDE]));
}
}
@ -1088,8 +1086,7 @@ void BX_CPU_C::update_access_dirty(bx_phy_address *entry_addr, Bit32u *entry, un
if (!(entry[leaf] & 0x20) || (write && !(entry[leaf] & 0x40))) {
entry[leaf] |= (0x20 | (write<<6)); // Update A and possibly D bits
access_write_physical(entry_addr[leaf], 4, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 4, BX_WRITE,
(BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 4, BX_WRITE, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
}
}
@ -1254,7 +1251,7 @@ bx_phy_address BX_CPU_C::nested_walk_long_mode(bx_phy_address guest_paddr, unsig
for (leaf = BX_LEVEL_PML4;; --leaf) {
entry_addr[leaf] = ppf + ((guest_paddr >> (9 + 9*leaf)) & 0xff8);
access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
offset_mask >>= 9;
Bit64u curr_entry = entry[leaf];
@ -1314,8 +1311,7 @@ bx_phy_address BX_CPU_C::nested_walk_PAE(bx_phy_address guest_paddr, unsigned rw
bx_phy_address pdpe_entry_addr = (bx_phy_address) (ncr3 | (index << 3));
access_read_physical(pdpe_entry_addr, 8, &pdptr);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pdpe_entry_addr, 8, BX_READ,
(BX_PDPTR0_ACCESS + index), (Bit8u*) &pdptr);
BX_NOTIFY_PHY_MEMORY_ACCESS(pdpe_entry_addr, 8, BX_READ, (BX_PDPTR0_ACCESS + index), (Bit8u*) &pdptr);
if (! (pdptr & 0x1)) {
BX_DEBUG(("Nested PAE Walk PDPTE%d entry not present !", index));
@ -1336,7 +1332,7 @@ bx_phy_address BX_CPU_C::nested_walk_PAE(bx_phy_address guest_paddr, unsigned rw
for (leaf = BX_LEVEL_PDE;; --leaf) {
entry_addr[leaf] = ppf + ((guest_paddr >> (9 + 9*leaf)) & 0xff8);
access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
Bit64u curr_entry = entry[leaf];
int fault = check_entry_PAE(bx_paging_level[leaf], curr_entry, reserved, rw, &nx_fault);
@ -1389,7 +1385,7 @@ bx_phy_address BX_CPU_C::nested_walk_legacy(bx_phy_address guest_paddr, unsigned
for (leaf = BX_LEVEL_PDE;; --leaf) {
entry_addr[leaf] = ppf + ((guest_paddr >> (10 + 10*leaf)) & 0xffc);
access_read_physical(entry_addr[leaf], 4, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 4, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 4, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
Bit32u curr_entry = entry[leaf];
if (!(curr_entry & 0x1)) {
@ -1505,8 +1501,7 @@ bx_phy_address BX_CPU_C::translate_guest_physical(bx_phy_address guest_paddr, bx
for (leaf = BX_LEVEL_PML4;; --leaf) {
entry_addr[leaf] = ppf + ((guest_paddr >> (9 + 9*leaf)) & 0xff8);
access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_READ,
(BX_EPT_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_READ, (BX_EPT_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
offset_mask >>= 9;
Bit64u curr_entry = entry[leaf];
@ -1602,8 +1597,7 @@ void BX_CPU_C::update_ept_access_dirty(bx_phy_address *entry_addr, Bit64u *entry
if (!(entry[level] & 0x100)) {
entry[level] |= 0x100;
access_write_physical(entry_addr[level], 8, &entry[level]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[level], 8, BX_WRITE,
(BX_EPT_PTE_ACCESS + level), (Bit8u*)(&entry[level]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[level], 8, BX_WRITE, (BX_EPT_PTE_ACCESS + level), (Bit8u*)(&entry[level]));
}
}
@ -1611,8 +1605,7 @@ void BX_CPU_C::update_ept_access_dirty(bx_phy_address *entry_addr, Bit64u *entry
if (!(entry[leaf] & 0x100) || (write && !(entry[leaf] & 0x200))) {
entry[leaf] |= (0x100 | (write<<9)); // Update A and possibly D bits
access_write_physical(entry_addr[leaf], 8, &entry[leaf]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, entry_addr[leaf], 8, BX_WRITE,
(BX_EPT_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_WRITE, (BX_EPT_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
}
}

4
bochs/cpu/smm.cc
View File

@ -94,7 +94,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RSM(bxInstruction_c *i)
for(n=0;n<SMM_SAVE_STATE_MAP_SIZE;n++) {
base -= 4;
access_read_physical(base, 4, &saved_state[n]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, base, 4, BX_READ, BX_SMRAM_ACCESS, (Bit8u*)(&saved_state[n]));
BX_NOTIFY_PHY_MEMORY_ACCESS(base, 4, BX_READ, BX_SMRAM_ACCESS, (Bit8u*)(&saved_state[n]));
}
BX_CPU_THIS_PTR in_smm = 0;
@ -159,7 +159,7 @@ void BX_CPU_C::enter_system_management_mode(void)
for(n=0;n<SMM_SAVE_STATE_MAP_SIZE;n++) {
base -= 4;
access_write_physical(base, 4, &saved_state[n]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, base, 4, BX_WRITE, BX_SMRAM_ACCESS, (Bit8u*)(&saved_state[n]));
BX_NOTIFY_PHY_MEMORY_ACCESS(base, 4, BX_WRITE, BX_SMRAM_ACCESS, (Bit8u*)(&saved_state[n]));
}
BX_CPU_THIS_PTR setEFlags(0x2); // Bit1 is always set

22
bochs/cpu/svm.cc
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@ -57,7 +57,7 @@ BX_CPP_INLINE Bit8u BX_CPU_C::vmcb_read8(unsigned offset)
access_read_physical(pAddr, 1, (Bit8u*)(&val_8));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&val_8));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&val_8));
return val_8;
}
@ -74,7 +74,7 @@ BX_CPP_INLINE Bit16u BX_CPU_C::vmcb_read16(unsigned offset)
access_read_physical(pAddr, 2, (Bit8u*)(&val_16));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&val_16));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 2, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&val_16));
return val_16;
}
@ -91,7 +91,7 @@ BX_CPP_INLINE Bit32u BX_CPU_C::vmcb_read32(unsigned offset)
access_read_physical(pAddr, 4, (Bit8u*)(&val_32));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&val_32));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 4, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&val_32));
return val_32;
}
@ -108,7 +108,7 @@ BX_CPP_INLINE Bit64u BX_CPU_C::vmcb_read64(unsigned offset)
access_read_physical(pAddr, 8, (Bit8u*)(&val_64));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&val_64));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 8, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&val_64));
return val_64;
}
@ -125,7 +125,7 @@ BX_CPP_INLINE void BX_CPU_C::vmcb_write8(unsigned offset, Bit8u val_8)
access_write_physical(pAddr, 1, (Bit8u*)(&val_8));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_8));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_8));
}
BX_CPP_INLINE void BX_CPU_C::vmcb_write16(unsigned offset, Bit16u val_16)
@ -141,7 +141,7 @@ BX_CPP_INLINE void BX_CPU_C::vmcb_write16(unsigned offset, Bit16u val_16)
access_write_physical(pAddr, 2, (Bit8u*)(&val_16));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_16));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 2, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_16));
}
BX_CPP_INLINE void BX_CPU_C::vmcb_write32(unsigned offset, Bit32u val_32)
@ -157,7 +157,7 @@ BX_CPP_INLINE void BX_CPU_C::vmcb_write32(unsigned offset, Bit32u val_32)
access_write_physical(pAddr, 4, (Bit8u*)(&val_32));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_32));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 4, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_32));
}
BX_CPP_INLINE void BX_CPU_C::vmcb_write64(unsigned offset, Bit64u val_64)
@ -173,7 +173,7 @@ BX_CPP_INLINE void BX_CPU_C::vmcb_write64(unsigned offset, Bit64u val_64)
access_write_physical(pAddr, 8, (Bit8u*)(&val_64));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_64));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 8, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_64));
}
BX_CPP_INLINE void BX_CPU_C::svm_segment_read(bx_segment_reg_t *seg, unsigned offset)
@ -765,11 +765,11 @@ void BX_CPU_C::SvmInterceptIO(bxInstruction_c *i, unsigned port, unsigned len)
// access_read_physical cannot read 2 bytes cross 4K boundary :(
pAddr = BX_CPU_THIS_PTR vmcb.ctrls.iopm_base + (port / 8);
access_read_physical(pAddr, 1, &bitmap[0]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[0]);
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[0]);
pAddr++;
access_read_physical(pAddr, 1, &bitmap[1]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[1]);
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[1]);
Bit16u combined_bitmap = bitmap[1];
combined_bitmap = (combined_bitmap << 8) | bitmap[0];
@ -859,7 +859,7 @@ void BX_CPU_C::SvmInterceptMSR(unsigned op, Bit32u msr)
Bit8u msr_bitmap;
access_read_physical(msr_bitmap_addr + (msr_offset / 8), 1, (Bit8u*)(&msr_bitmap));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, msr_bitmap_addr + (msr_offset / 8), 1, BX_READ, BX_MSR_BITMAP_ACCESS, &msr_bitmap);
BX_NOTIFY_PHY_MEMORY_ACCESS(msr_bitmap_addr + (msr_offset / 8), 1, BX_READ, BX_MSR_BITMAP_ACCESS, &msr_bitmap);
vmexit = (msr_bitmap >> (msr_offset & 7)) & 0x1;
}

16
bochs/cpu/vmexit.cc
View File

@ -327,7 +327,7 @@ void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_MSR(bxInstruction_c *i, unsigned op
// check MSR-HI bitmaps
bx_phy_address pAddr = vm->msr_bitmap_addr + ((msr - BX_VMX_HI_MSR_START) >> 3) + 1024 + ((op == VMX_VMEXIT_RDMSR) ? 0 : 2048);
access_read_physical(pAddr, 1, &field);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, BX_MSR_BITMAP_ACCESS, &field);
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_MSR_BITMAP_ACCESS, &field);
if (field & (1 << (msr & 7)))
vmexit = 1;
}
@ -338,7 +338,7 @@ void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_MSR(bxInstruction_c *i, unsigned op
// check MSR-LO bitmaps
bx_phy_address pAddr = vm->msr_bitmap_addr + (msr >> 3) + ((op == VMX_VMEXIT_RDMSR) ? 0 : 2048);
access_read_physical(pAddr, 1, &field);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, BX_MSR_BITMAP_ACCESS, &field);
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_MSR_BITMAP_ACCESS, &field);
if (field & (1 << (msr & 7)))
vmexit = 1;
}
@ -374,21 +374,21 @@ void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_IO(bxInstruction_c *i, unsigned por
// special case - the IO access split cross both I/O bitmaps
pAddr = BX_CPU_THIS_PTR vmcs.io_bitmap_addr[0] + 0xfff;
access_read_physical(pAddr, 1, &bitmap[0]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[0]);
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[0]);
pAddr = BX_CPU_THIS_PTR vmcs.io_bitmap_addr[1];
access_read_physical(pAddr, 1, &bitmap[1]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[1]);
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[1]);
}
else {
// access_read_physical cannot read 2 bytes cross 4K boundary :(
pAddr = BX_CPU_THIS_PTR vmcs.io_bitmap_addr[(port >> 15) & 1] + ((port & 0x7fff) / 8);
access_read_physical(pAddr, 1, &bitmap[0]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[0]);
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[0]);
pAddr++;
access_read_physical(pAddr, 1, &bitmap[1]);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[1]);
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, BX_READ, BX_IO_BITMAP_ACCESS, &bitmap[1]);
}
Bit16u combined_bitmap = bitmap[1];
@ -663,7 +663,7 @@ Bit32u BX_CPU_C::VMX_Read_VTPR(void)
bx_phy_address pAddr = BX_CPU_THIS_PTR vmcs.virtual_apic_page_addr + 0x80;
Bit32u vtpr;
access_read_physical(pAddr, 4, (Bit8u*)(&vtpr));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_READ, BX_VMX_VTPR_ACCESS, (Bit8u*)(&vtpr));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 4, BX_READ, BX_VMX_VTPR_ACCESS, (Bit8u*)(&vtpr));
return vtpr;
}
@ -674,7 +674,7 @@ void BX_CPU_C::VMX_Write_VTPR(Bit8u vtpr)
Bit32u field32 = vtpr;
access_write_physical(pAddr, 4, (Bit8u*)(&field32));
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_WRITE, BX_VMX_VTPR_ACCESS, (Bit8u*)(&field32));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 4, BX_WRITE, BX_VMX_VTPR_ACCESS, (Bit8u*)(&field32));
Bit8u tpr_shadow = vtpr >> 4;
if (tpr_shadow < vm->vm_tpr_threshold) {

32
bochs/cpu/vmx.cc
View File

@ -71,7 +71,7 @@ Bit16u BX_CPP_AttrRegparmN(1) BX_CPU_C::VMread16(unsigned encoding)
access_read_physical(pAddr, 2, (Bit8u*)(&field));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&field));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 2, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&field));
return field;
}
@ -95,7 +95,7 @@ void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMwrite16(unsigned encoding, Bit16u val_16
access_write_physical(pAddr, 2, (Bit8u*)(&val_16));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_16));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 2, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_16));
}
Bit32u BX_CPP_AttrRegparmN(1) BX_CPU_C::VMread32(unsigned encoding)
@ -115,7 +115,7 @@ Bit32u BX_CPP_AttrRegparmN(1) BX_CPU_C::VMread32(unsigned encoding)
access_read_physical(pAddr, 4, (Bit8u*)(&field));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&field));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 4, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&field));
return field;
}
@ -137,7 +137,7 @@ void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMwrite32(unsigned encoding, Bit32u val_32
access_write_physical(pAddr, 4, (Bit8u*)(&val_32));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_32));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 4, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_32));
}
Bit64u BX_CPP_AttrRegparmN(1) BX_CPU_C::VMread64(unsigned encoding)
@ -159,7 +159,7 @@ Bit64u BX_CPP_AttrRegparmN(1) BX_CPU_C::VMread64(unsigned encoding)
access_read_physical(pAddr, 8, (Bit8u*)(&field));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&field));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 8, BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&field));
return field;
}
@ -183,7 +183,7 @@ void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMwrite64(unsigned encoding, Bit64u val_64
access_write_physical(pAddr, 8, (Bit8u*)(&val_64));
}
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_64));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 8, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&val_64));
}
#if BX_SUPPORT_X86_64
@ -238,7 +238,7 @@ void BX_CPU_C::VMabort(VMX_vmabort_code error_code)
Bit32u abort = error_code;
bx_phy_address pAddr = BX_CPU_THIS_PTR vmcsptr + VMCS_VMX_ABORT_FIELD_ADDR;
access_write_physical(pAddr, 4, &abort);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&abort));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 4, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&abort));
#if BX_SUPPORT_VMX >= 2
// Deactivate VMX preemtion timer
@ -252,7 +252,7 @@ unsigned BX_CPU_C::VMXReadRevisionID(bx_phy_address pAddr)
{
Bit32u revision;
access_read_physical(pAddr + VMCS_REVISION_ID_FIELD_ADDR, 4, &revision);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr + VMCS_REVISION_ID_FIELD_ADDR, 4,
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr + VMCS_REVISION_ID_FIELD_ADDR, 4,
BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&revision));
return revision;
@ -1711,9 +1711,9 @@ Bit32u BX_CPU_C::LoadMSRs(Bit32u msr_cnt, bx_phy_address pAddr)
for (Bit32u msr = 1; msr <= msr_cnt; msr++) {
access_read_physical(pAddr, 8, &msr_lo);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_READ, BX_VMX_LOAD_MSR_ACCESS, (Bit8u*)(&msr_lo));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 8, BX_READ, BX_VMX_LOAD_MSR_ACCESS, (Bit8u*)(&msr_lo));
access_read_physical(pAddr + 8, 8, &msr_hi);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr + 8, 8, BX_READ, BX_VMX_LOAD_MSR_ACCESS, (Bit8u*)(&msr_hi));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr + 8, 8, BX_READ, BX_VMX_LOAD_MSR_ACCESS, (Bit8u*)(&msr_hi));
if (GET32H(msr_lo))
return msr;
@ -1745,7 +1745,7 @@ Bit32u BX_CPU_C::StoreMSRs(Bit32u msr_cnt, bx_phy_address pAddr)
for (Bit32u msr = 1; msr <= msr_cnt; msr++) {
access_read_physical(pAddr, 8, &msr_lo);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 8, BX_READ, BX_VMX_STORE_MSR_ACCESS, (Bit8u*)(&msr_lo));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 8, BX_READ, BX_VMX_STORE_MSR_ACCESS, (Bit8u*)(&msr_lo));
if (GET32H(msr_lo))
return msr;
@ -1761,7 +1761,7 @@ Bit32u BX_CPU_C::StoreMSRs(Bit32u msr_cnt, bx_phy_address pAddr)
return msr;
access_write_physical(pAddr + 8, 8, &msr_hi);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr + 8, 8, BX_WRITE, BX_VMX_STORE_MSR_ACCESS, (Bit8u*)(&msr_hi));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr + 8, 8, BX_WRITE, BX_VMX_STORE_MSR_ACCESS, (Bit8u*)(&msr_hi));
pAddr += 16; // to next MSR
}
@ -2309,7 +2309,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMCALL(bxInstruction_c *i)
Bit32u launch_state;
access_read_physical(BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4, &launch_state);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4,
BX_NOTIFY_PHY_MEMORY_ACCESS(BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4,
BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&launch_state));
if (launch_state != VMCS_STATE_CLEAR) {
@ -2386,7 +2386,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMLAUNCH(bxInstruction_c *i)
Bit32u launch_state;
access_read_physical(BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4, &launch_state);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4,
BX_NOTIFY_PHY_MEMORY_ACCESS(BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4,
BX_READ, BX_VMCS_ACCESS, (Bit8u*)(&launch_state));
if (vmlaunch) {
@ -2451,7 +2451,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMLAUNCH(bxInstruction_c *i)
launch_state = VMCS_STATE_LAUNCHED;
bx_phy_address pAddr = BX_CPU_THIS_PTR vmcsptr + VMCS_LAUNCH_STATE_FIELD_ADDR;
access_write_physical(pAddr, 4, &launch_state);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 4, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&launch_state));
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 4, BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&launch_state));
}
/*
@ -2832,7 +2832,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMCLEAR(bxInstruction_c *i)
// clear VMCS launch state
Bit32u launch_state = VMCS_STATE_CLEAR;
access_write_physical(pAddr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4, &launch_state);
BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4,
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr + VMCS_LAUNCH_STATE_FIELD_ADDR, 4,
BX_WRITE, BX_VMCS_ACCESS, (Bit8u*)(&launch_state));
if (pAddr == BX_CPU_THIS_PTR vmcsptr) {

11
bochs/instrument/example0/instrument.h
View File

@ -94,9 +94,7 @@ void bx_instr_lin_access(unsigned cpu, bx_address lin, bx_phy_address phy, unsig
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw) \
bx_instr_lin_access(cpu_id, lin, phy, len, rw)
/* called from memory object */
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw)
/* feedback from device units */
#define BX_INSTR_INP(addr, len)
@ -148,12 +146,11 @@ void bx_instr_lin_access(unsigned cpu, bx_address lin, bx_phy_address phy, unsig
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
/* memory access */
/* linear memory access */
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
/* called from memory object */
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
/* physical memory access */
#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw)
/* feedback from device units */
#define BX_INSTR_INP(addr, len)

11
bochs/instrument/example1/instrument.h
View File

@ -145,9 +145,7 @@ extern bxInstrumentation *icpu;
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw) \
icpu[cpu_id].bx_instr_lin_access(lin, phy, len, rw)
/* called from memory object */
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw)
/* feedback from device units */
#define BX_INSTR_INP(addr, len)
@ -199,12 +197,11 @@ extern bxInstrumentation *icpu;
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
/* memory access */
/* linear memory access */
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
/* called from memory object */
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
/* physical memory access */
#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw)
/* feedback from device units */
#define BX_INSTR_INP(addr, len)

14
bochs/instrument/example2/instrument.h
View File

@ -81,12 +81,11 @@ void bx_instr_before_execution(unsigned cpu, bxInstruction_c *i);
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
/* memory access */
/* linear memory access */
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
/* called from memory object */
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
/* physical memory access */
#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw)
/* feedback from device units */
#define BX_INSTR_INP(addr, len)
@ -139,12 +138,11 @@ void bx_instr_before_execution(unsigned cpu, bxInstruction_c *i);
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
/* memory access */
/* linear memory access */
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
/* called from memory object */
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
/* physical memory access */
#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw)
/* feedback from device units */
#define BX_INSTR_INP(addr, len)

13
bochs/instrument/instrumentation.txt
View File

@ -210,7 +210,7 @@ The callback is called each time, when Bochs simulator executes a linear
memory access. Note that no page split accesses will be generated because
Bochs splits page split accesses to two different memory accesses during its
execution flow. The callback also will not be generated in case of direct
physical memory access like in SMM, VMM or SVM modes.
physical memory access like page walks, SMM, VMM or SVM operations.
Possible access types are: BX_READ, BX_WRITE and BX_RW.
@ -218,10 +218,15 @@ Currently the callback is not supported when repeat-speedups optimization is
enabled.
void bx_instr_phy_read(unsigned cpu, bx_address addr, unsigned len);
void bx_instr_phy_write(unsigned cpu, bx_address addr, unsigned len);
void bx_instr_phy_access(unsigned cpu, bx_address lin, bx_address phy, unsigned len, unsigned rw);
These callback functions are the feedback from external memory system.
The callback is called each time, when Bochs simulator executes a physical
memory access. Physical accesses include memory accesses generated by the
CPU during page walks, SMM, VMM or SVM operations. Note that no page split
accesses will be generated because Bochs splits page split accesses to two
different memory accesses during its execution flow.
Possible access types are: BX_READ, BX_WRITE and BX_RW.
void bx_instr_inp(Bit16u addr, unsigned len);

18
bochs/instrument/stubs/instrument.h
View File

@ -65,9 +65,7 @@ void bx_instr_inp2(Bit16u addr, unsigned len, unsigned val);
void bx_instr_outp(Bit16u addr, unsigned len, unsigned val);
void bx_instr_lin_access(unsigned cpu, bx_address lin, bx_address phy, unsigned len, unsigned rw);
void bx_instr_phy_write(unsigned cpu, bx_address addr, unsigned len);
void bx_instr_phy_read(unsigned cpu, bx_address addr, unsigned len);
void bx_instr_phy_access(unsigned cpu, bx_address phy, unsigned len, unsigned rw);
void bx_instr_wrmsr(unsigned cpu, unsigned addr, Bit64u value);
@ -117,12 +115,11 @@ void bx_instr_wrmsr(unsigned cpu, unsigned addr, Bit64u value);
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i) bx_instr_after_execution(cpu_id, i)
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i) bx_instr_repeat_iteration(cpu_id, i)
/* memory access */
/* linear memory access */
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw) bx_instr_lin_access(cpu_id, lin, phy, len, rw)
/* called from memory object */
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len) bx_instr_phy_write(cpu_id, addr, len)
#define BX_INSTR_PHY_READ(cpu_id, addr, len) bx_instr_phy_read(cpu_id, addr, len)
/* physical memory access */
#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw) bx_instr_phy_access(cpu_id, phy, len, rw)
/* feedback from device units */
#define BX_INSTR_INP(addr, len) bx_instr_inp(addr, len)
@ -174,12 +171,11 @@ void bx_instr_wrmsr(unsigned cpu, unsigned addr, Bit64u value);
#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
/* memory access */
/* linear memory access */
#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
/* called from memory object */
#define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
#define BX_INSTR_PHY_READ(cpu_id, addr, len)
/* physical memory access */
#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw)
/* feedback from device units */
#define BX_INSTR_INP(addr, len)

4
bochs/memory/memory.cc
View File

@ -61,8 +61,6 @@ void BX_MEM_C::writePhysicalPage(BX_CPU_C *cpu, bx_phy_address addr, unsigned le
bx_devices.pluginIODebug->mem_write(cpu, a20addr, len, data);
#endif
BX_INSTR_PHY_WRITE(cpu->which_cpu(), a20addr, len);
if ((a20addr >= 0x000a0000 && a20addr < 0x000c0000) && BX_MEM_THIS smram_available)
{
// SMRAM memory space
@ -206,8 +204,6 @@ void BX_MEM_C::readPhysicalPage(BX_CPU_C *cpu, bx_phy_address addr, unsigned len
bx_devices.pluginIODebug->mem_read(cpu, a20addr, len, data);
#endif
BX_INSTR_PHY_READ(cpu->which_cpu(), a20addr, len);
if ((a20addr >= 0x000a0000 && a20addr < 0x000c0000) && BX_MEM_THIS smram_available)
{
// SMRAM memory space