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fixes for SVN. also turion64_tyler supports RDTSCP - include it in CPUID

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This commit is contained in:
Stanislav Shwartsman 2012-01-01 17:54:41 +00:00
parent ca09763e89
commit 810aa1b67c
4 changed files with 20 additions and 10 deletions
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2
bochs/cpu/cpudb/athlon64_clawhammer.cc
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@ -251,7 +251,7 @@ void athlon64_clawhammer_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
leaf->ecx = 0;
// EDX:
// Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD
// Many of the bits in EDX are the same as FN 0x00000001 for AMD
// * [0:0] FPU on chip
// * [1:1] VME: Virtual-8086 Mode enhancements
// * [2:2] DE: Debug Extensions (I/O breakpoints)

2
bochs/cpu/cpudb/athlon64_venice.cc
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@ -301,7 +301,7 @@ void athlon64_venice_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
leaf->ecx = BX_CPUID_EXT2_LAHF_SAHF;
// EDX:
// Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD
// Many of the bits in EDX are the same as FN 0x00000001 for AMD
// * [0:0] FPU on chip
// * [1:1] VME: Virtual-8086 Mode enhancements
// * [2:2] DE: Debug Extensions (I/O breakpoints)

8
bochs/cpu/cpudb/turion64_tyler.cc
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@ -104,7 +104,10 @@ Bit64u turion64_tyler_t::get_isa_extensions_bitmask(void) const
BX_ISA_SSE3 |
BX_ISA_CMPXCHG16B |
BX_ISA_LM_LAHF_SAHF |
BX_ISA_SVM;
#if BX_SUPPORT_SVM
BX_ISA_SVM |
#endif
BX_ISA_RDTSCP;
}
Bit32u turion64_tyler_t::get_cpu_extensions_bitmask(void) const
@ -339,7 +342,7 @@ void turion64_tyler_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
BX_CPUID_EXT2_PREFETCHW;
// EDX:
// Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD
// Many of the bits in EDX are the same as FN 0x00000001 for AMD
// * [0:0] FPU on chip
// * [1:1] VME: Virtual-8086 Mode enhancements
// * [2:2] DE: Debug Extensions (I/O breakpoints)
@ -394,6 +397,7 @@ void turion64_tyler_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
BX_CPUID_STD_MMX |
BX_CPUID_STD_FXSAVE_FXRSTOR |
BX_CPUID_STD2_FFXSR |
BX_CPUID_STD2_RDTSCP |
BX_CPUID_STD2_LONG_MODE |
BX_CPUID_STD2_3DNOW_EXT |
BX_CPUID_STD2_3DNOW;

18
bochs/cpu/svm.cc
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@ -185,7 +185,7 @@ BX_CPP_INLINE void BX_CPU_C::svm_segment_read(bx_segment_reg_t *seg, unsigned of
bx_bool valid = (attr >> 7) & 1;
set_segment_ar_data(seg, valid, selector, base, limit,
(attr & 0xff) | ((attr & 0xf00) << 8));
(attr & 0xff) | ((attr & 0xf00) << 4));
}
BX_CPP_INLINE void BX_CPU_C::svm_segment_write(bx_segment_reg_t *seg, unsigned offset)
@ -197,7 +197,7 @@ BX_CPP_INLINE void BX_CPU_C::svm_segment_write(bx_segment_reg_t *seg, unsigned o
(get_descriptor_h(&seg->cache) & 0x00f0ff00) : 0;
vmcb_write16(offset, selector);
vmcb_write16(offset + 2, ((attr >> 8) & 0xff) | ((attr >> 20) & 0xf));
vmcb_write16(offset + 2, ((attr >> 8) & 0xff) | ((attr >> 12) & 0xf00));
vmcb_write32(offset + 4, limit);
vmcb_write64(offset + 8, base);
}
@ -359,6 +359,10 @@ bx_bool BX_CPU_C::SvmEnterLoadCheckControls(SVM_CONTROLS *ctrls)
ctrls->v_intr_prio = vintr_control & 0xf;
ctrls->v_ignore_tpr = (vintr_control >> 4) & 0x1;
if (vmcb_read8(SVM_CONTROL_NESTED_PAGING_ENABLE)) {
BX_PANIC(("VMRUN: Nested Paging support is not implemented yet !"));
}
return 1;
}
@ -426,7 +430,9 @@ bx_bool BX_CPU_C::SvmEnterLoadCheckGuestState(void)
svm_segment_read(&guest.sregs[n], SVM_GUEST_ES_SELECTOR + n * 0x10);
}
//
// FIXME: patch segment attributes
//
if (guest.sregs[BX_SEG_REG_CS].cache.u.segment.d_b && guest.sregs[BX_SEG_REG_CS].cache.u.segment.l) {
BX_ERROR(("VMRUN: VMCB CS.D_B/L mismatch"));
@ -458,8 +464,8 @@ bx_bool BX_CPU_C::SvmEnterLoadCheckGuestState(void)
guest.gdtr.base = CanonicalizeAddress(vmcb_read64(SVM_GUEST_GDTR_BASE));
guest.gdtr.limit = vmcb_read16(SVM_GUEST_GDTR_LIMIT);
guest.idtr.base = CanonicalizeAddress(vmcb_read64(SVM_GUEST_GDTR_BASE));
guest.idtr.limit = vmcb_read16(SVM_GUEST_GDTR_LIMIT);
guest.idtr.base = CanonicalizeAddress(vmcb_read64(SVM_GUEST_IDTR_BASE));
guest.idtr.limit = vmcb_read16(SVM_GUEST_IDTR_LIMIT);
guest.inhibit_interrupts = vmcb_read8(SVM_CONTROL_INTERRUPT_SHADOW) & 0x1;
@ -948,7 +954,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMLOAD(bxInstruction_c *i)
BX_CPU_THIS_PTR vmcbptr = pAddr;
BX_CPU_THIS_PTR vmcbhostptr = BX_CPU_THIS_PTR getHostMemAddr(pAddr, BX_WRITE);
BX_INFO(("VMLOAD VMCB ptr: 0x" FMT_ADDRX64, BX_CPU_THIS_PTR vmcbptr));
BX_DEBUG(("VMLOAD VMCB ptr: 0x" FMT_ADDRX64, BX_CPU_THIS_PTR vmcbptr));
bx_segment_reg_t fs, gs, guest_tr, guest_ldtr;
@ -999,7 +1005,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMSAVE(bxInstruction_c *i)
BX_CPU_THIS_PTR vmcbptr = pAddr;
BX_CPU_THIS_PTR vmcbhostptr = BX_CPU_THIS_PTR getHostMemAddr(pAddr, BX_WRITE);
BX_INFO(("VMSAVE VMCB ptr: 0x" FMT_ADDRX64, BX_CPU_THIS_PTR vmcbptr));
BX_DEBUG(("VMSAVE VMCB ptr: 0x" FMT_ADDRX64, BX_CPU_THIS_PTR vmcbptr));
svm_segment_write(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], SVM_GUEST_FS_SELECTOR);
svm_segment_write(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], SVM_GUEST_GS_SELECTOR);