reorg avx opcodes in ia_opcodes.h. place v128 and v256 opcodes together. todo: find way to merge them sometimes
This commit is contained in:
Stanislav Shwartsman
parent
a6b85d9443
commit
6ddfe5fc3b
@ -1536,7 +1536,7 @@ bx_define_opcode(BX_IA_INVPCID, &BX_CPU_C::INVPCID, &BX_CPU_C::BxError, BX_ISA_I
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#endif
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#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
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// AVX
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// AVX1/AVX2
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bx_define_opcode(BX_IA_VZEROUPPER, NULL, &BX_CPU_C::VZEROUPPER, BX_ISA_AVX, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VZEROALL, NULL, &BX_CPU_C::VZEROALL, BX_ISA_AVX, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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@ -1544,33 +1544,32 @@ bx_define_opcode(BX_IA_VLDMXCSR, &BX_CPU_C::LDMXCSR, &BX_CPU_C::BxError, BX_ISA_
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bx_define_opcode(BX_IA_VSTMXCSR, &BX_CPU_C::STMXCSR, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVAPS_VpsWps, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVAPS_WpsVps, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVAPD_WpdVpd, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVUPS_WpsVps, &BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVUPD_VpdWpd, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVUPD_WpdVpd, &BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVDQA_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVDQA_WdqVdq, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVDQU_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVDQU_WdqVdq, &BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVAPS_VpsWps, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVAPS_WpsVps, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVAPS_WpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVAPD_WpdVpd, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVAPD_WpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVUPS_WpsVps, &BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVUPS_WpsVps, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVUPD_VpdWpd, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVUPD_VpdWpd, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVUPD_WpdVpd, &BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVUPD_WpdVpd, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVDQA_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVDQA_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVDQA_WdqVdq, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVDQA_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVDQU_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVDQU_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVDQU_WdqVdq, &BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVDQU_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVSD_VsdHpdWsd, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_MEM_NO_VVV, BX_SRC_NONE, BX_PREPARE_AVX)
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@ -1585,19 +1584,22 @@ bx_define_opcode(BX_IA_V128_VMOVLPD_MqVsd, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::
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bx_define_opcode(BX_IA_V128_VMOVHPD_MqVsd, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVLPD_VpdHpdMq, &BX_CPU_C::VMOVLPD_VpdHpdMq, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVHPD_VpdHpdMq, &BX_CPU_C::VMOVHPD_VpdHpdMq, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VLDDQU_VdqMdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVNTPS_MpsVps, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVNTPD_MpdVpd, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVNTDQ_MdqVdq, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVNTPS_MpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVNTPD_MpdVpd, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVNTPD_MpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VMOVNTDQ_MdqVdq, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VMOVNTDQ_MdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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@ -1616,9 +1618,14 @@ bx_define_opcode(BX_IA_VORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS
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bx_define_opcode(BX_IA_VORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VXORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VXORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V128_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VHADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VHADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_VHSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
@ -1677,107 +1684,211 @@ bx_define_opcode(BX_IA_VCMPSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCMPS
|
||||
// SSE alias
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPSRLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSRLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSRLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRLQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSRAW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRAW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSLLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSLLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSLLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSLLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSLLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSLLQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPSRLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLW_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRLW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSRAW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAW_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRAW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSLLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLW_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSLLW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSRLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLD_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRLD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSRAD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRAD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSLLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLD_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSLLD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSRLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRLQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSLLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSLLQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSRLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLDQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLDQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSLLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLDQ_UdqIb, BX_ISA_AVX, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSLLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLDQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_VMOVMSKPS_GdVRps, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPS_GdVRps, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VMOVMSKPD_GdVRpd, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPD_GdVRpd, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VUNPCKLPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VUNPCKLPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VUNPCKHPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPUNPCKLBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKLBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKLBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKLBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPUNPCKLWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKLWD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKLWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKLWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPUNPCKHBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKHBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKHBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKHBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPUNPCKHWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKHWD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKHWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKHWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPCMPEQB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPEQB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPCMPEQW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPEQW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPCMPEQD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPEQD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPCMPEQQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPEQQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPCMPGTB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPGTB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPCMPGTW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPGTW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPCMPGTD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPGTD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPCMPGTQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPGTQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPSUBSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPADDSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPADDSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSUBUSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBUSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBUSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBUSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSUBUSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBUSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBUSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBUSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPADDUSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDUSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDUSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDUSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPADDUSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDUSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDUSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDUSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPAVGB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPAVGB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPAVGB_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPAVGB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPAVGW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPAVGW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPAVGW_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPAVGW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPANDN_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPANDN_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPAND_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPAND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPOR_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPXOR_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPXOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPMULHRSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHRSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULHRSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHRSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMULLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULLW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMULHW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHUW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMULLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULLW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMULHW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULHW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHUW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VMASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVDQU_VdqUdq, BX_ISA_AVX, BX_SRC_NONE, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSUBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPADDB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPADDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPADDD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPSHUFB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSHUFB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPHADDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHADDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPHADDD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHADDD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPHSUBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHSUBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPHSUBD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPHADDSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHADDSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPHSUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHSUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPMADDWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADDWD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMADDWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMADDUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADDUBSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMADDUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPSIGNB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGNB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSIGNB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGNB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSIGNW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGNW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSIGNW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGNW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPSIGND_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGND_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSIGND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGND_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_VTESTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPS_VpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VTESTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPD_VpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VPTEST_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPTEST_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VBROADCASTSS_VpsMss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_VdqWd, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VBROADCASTSD_VpdMsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWq, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VBROADCASTF128_VdqMdq, &BX_CPU_C::VBROADCASTF128_VdqMdq, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPABSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSB_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPABSB_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSB_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPABSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSW_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPABSW_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSW_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPABSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSD_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPABSD_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSD_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPACKSSWB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKSSWB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPACKSSWB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKSSWB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPACKUSWB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKUSWB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPACKUSWB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKUSWB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPACKUSDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKUSDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPACKUSDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKUSDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPACKSSDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKSSDW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPACKSSDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKSSDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_VMASKMOVPS_VpsHpsMps, &BX_CPU_C::VMASKMOVPS_VpsHpsMps, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VMASKMOVPS_MpsHpsVps, &BX_CPU_C::VMASKMOVPS_MpsHpsVps, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::BxError, BX_ISA_AVX, BX_SRC_RM, BX_SRC_VVV, BX_SRC_NNN, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_VPMOVSXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXBW_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VPMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXBD_VdqWdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VPMOVSXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVSXBQ_VdqWwR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
@ -1790,36 +1901,61 @@ bx_define_opcode(BX_IA_VPMOVZXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVZXBQ_
|
||||
bx_define_opcode(BX_IA_VPMOVZXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXWD_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VPMOVZXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXWQ_VdqWdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VPMOVZXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXDQ_VdqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPMINSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMINSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMINUB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINUB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMINUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMAXSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMAXSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMAXUB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUB_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXUB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMAXUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUW_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPHMINPOSUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_VPERMILPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsHpsWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VPERMILPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdHpdWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VPERMILPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VPERMILPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VBLENDPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VBLENDPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPBLENDW_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPBLENDW_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPBLENDW_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDW_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPALIGNR_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPALIGNR_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPERM2F128_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VINSERTF128_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VEXTRACTF128_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_VBLENDVPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPS_VpsHpsWpsIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VBLENDVPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPD_VpdHpdWpdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VMPSADBW_VdqHdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMPSADBW_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPCMPESTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
@ -1836,6 +1972,7 @@ bx_define_opcode(BX_IA_V128_VPCLMULQDQ_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CP
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VMOVD_VdqEd, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVD_VdqEdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VMOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_V128_VPINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqHdqEbIbM, &BX_CPU_C::PINSRB_VdqHdqEbIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::PINSRW_VdqHdqEwIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPINSRD_VdqEdIb, &BX_CPU_C::PINSRD_VdqHdqEdIbM, &BX_CPU_C::PINSRD_VdqHdqEdIbR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
@ -1845,6 +1982,7 @@ bx_define_opcode(BX_IA_V128_VPEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, &BX_C
|
||||
bx_define_opcode(BX_IA_V128_VPEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_CPU_C::PEXTRW_EwdVdqIbR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VPEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRQ_EqVdqIbM, &BX_CPU_C::PEXTRQ_EqVdqIbR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_VCVTPS2PD_VpdWps, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VCVTPS2PD_VpdWpsR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VCVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPD2DQ_VqWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VCVTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2DQ_VqWpdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
@ -1867,6 +2005,7 @@ bx_define_opcode(BX_IA_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2
|
||||
bx_define_opcode(BX_IA_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
|
||||
bx_define_opcode(BX_IA_VMOVQ_WqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VMOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V128_VMOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
@ -1874,113 +2013,6 @@ bx_define_opcode(BX_IA_V128_VMOVQ_EqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOV
|
||||
|
||||
bx_define_opcode(BX_IA_VCVTPH2PS_VpsWps, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_ISA_AVX_F16C, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, BX_ISA_AVX_F16C, BX_SRC_RM, BX_SRC_NNN, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
// AVX
|
||||
|
||||
// AVX2
|
||||
bx_define_opcode(BX_IA_V256_VPCMPEQB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPEQW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPEQD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPEQQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPGTB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPGTW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPGTD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPCMPGTQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINUB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXUB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSIGNB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGNB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSIGNW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGNW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSIGND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGND_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPANDN_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPAND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPXOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPABSB_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSB_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPABSW_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSW_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPABSD_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSD_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBUSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBUSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSUBUSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBUSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDUSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDUSB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPADDUSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDUSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPAVGB_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPAVGB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPAVGW_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPAVGW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHADDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHADDD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHSUBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHADDSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPHSUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPACKSSWB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKSSWB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPACKUSWB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKUSWB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPACKUSDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKUSDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPACKSSDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKSSDW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKLBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKLBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKLWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKLWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKHBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKHBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKHWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKHWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULHW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHUW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMULHRSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHRSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMADDUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDUBSW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMADDWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDWD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMPSADBW_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPBLENDW_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDW_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_VIB, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSHUFB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFB_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
|
||||
bx_define_opcode(BX_IA_V256_VPSRLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSRLQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSRAW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSLLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLW_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSLLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSLLQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLQ_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSRLW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSRAW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSLLW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLW_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSRLD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSRAD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSLLD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLD_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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bx_define_opcode(BX_IA_V256_VPSRLQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
bx_define_opcode(BX_IA_V256_VPSLLQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
bx_define_opcode(BX_IA_V256_VPSRLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLDQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
bx_define_opcode(BX_IA_V256_VPSLLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLDQ_UdqIb, BX_ISA_AVX2, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
bx_define_opcode(BX_IA_V256_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPALIGNR_VdqHdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
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bx_define_opcode(BX_IA_VPMOVSXBW256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXBW256_VdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
bx_define_opcode(BX_IA_VPMOVSXBD256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXBD256_VdqWqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
@ -2034,8 +2066,7 @@ bx_define_opcode(BX_IA_V256_VPERMD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C:
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bx_define_opcode(BX_IA_V256_VPERMPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
bx_define_opcode(BX_IA_V256_VPERMPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMQ_VdqWdqIbR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
bx_define_opcode(BX_IA_VPSRAVD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAVD_VdqHdqWdqR, BX_ISA_AVX2, BX_SRC_NNN, BX_SRC_VVV, BX_SRC_VEC_RM, BX_SRC_NONE, BX_PREPARE_AVX)
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||||
// AVX2
|
||||
|
||||
// AVX1/AVX2
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||||
|
||||
// AVX2 FMA - VexW aliased
|
||||
bx_define_opcode(BX_IA_VFMADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX_FMA, BX_SRC_NNN, BX_SRC_NNN, BX_SRC_VEC_RM, BX_SRC_VVV, BX_PREPARE_AVX)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user