intel disclosed more cpuid bits
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@ -300,26 +300,28 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
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// [0:0] FS/GS BASE access instructions
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// [2:1] reserved
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// [3:3] BMI1: Advanced Bit Manipulation Extensions
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// [4:4] reserved
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// [4:4] HLE: Hardware Lock Elision
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// [5:5] AVX2
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// [6:6] reserved
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// [7:7] SMEP: Supervisor Mode Execution Protection
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// [8:8] BMI2: Advanced Bit Manipulation Extensions
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// [9:9] Support for Enhanced REP MOVSB/STOSB
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// [10:10] Support for INVPCID instruction
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// [11:11] RTM: Restricted Transactional Memory
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// [31:10] reserved
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#define BX_CPUID_EXT3_FSGSBASE (1 << 0)
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#define BX_CPUID_EXT3_RESERVED1 (1 << 1)
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#define BX_CPUID_EXT3_RESERVED2 (1 << 2)
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#define BX_CPUID_EXT3_BMI1 (1 << 3)
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#define BX_CPUID_EXT3_RESERVED4 (1 << 4)
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#define BX_CPUID_EXT3_HLE (1 << 4)
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#define BX_CPUID_EXT3_AVX2 (1 << 5)
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#define BX_CPUID_EXT3_RESERVED6 (1 << 6)
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#define BX_CPUID_EXT3_SMEP (1 << 7)
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#define BX_CPUID_EXT3_BMI2 (1 << 8)
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#define BX_CPUID_EXT3_ENCHANCED_REP_STRINGS (1 << 9)
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#define BX_CPUID_EXT3_INVPCID (1 << 10)
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#define BX_CPUID_EXT3_RTM (1 << 11)
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// ...
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