intel disclosed more cpuid bits

This commit is contained in:
Stanislav Shwartsman 2012-02-08 19:54:22 +00:00
parent 47f2137edf
commit b497077b70

View File

@ -300,26 +300,28 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [0:0] FS/GS BASE access instructions
// [2:1] reserved
// [3:3] BMI1: Advanced Bit Manipulation Extensions
// [4:4] reserved
// [4:4] HLE: Hardware Lock Elision
// [5:5] AVX2
// [6:6] reserved
// [7:7] SMEP: Supervisor Mode Execution Protection
// [8:8] BMI2: Advanced Bit Manipulation Extensions
// [9:9] Support for Enhanced REP MOVSB/STOSB
// [10:10] Support for INVPCID instruction
// [11:11] RTM: Restricted Transactional Memory
// [31:10] reserved
#define BX_CPUID_EXT3_FSGSBASE (1 << 0)
#define BX_CPUID_EXT3_RESERVED1 (1 << 1)
#define BX_CPUID_EXT3_RESERVED2 (1 << 2)
#define BX_CPUID_EXT3_BMI1 (1 << 3)
#define BX_CPUID_EXT3_RESERVED4 (1 << 4)
#define BX_CPUID_EXT3_HLE (1 << 4)
#define BX_CPUID_EXT3_AVX2 (1 << 5)
#define BX_CPUID_EXT3_RESERVED6 (1 << 6)
#define BX_CPUID_EXT3_SMEP (1 << 7)
#define BX_CPUID_EXT3_BMI2 (1 << 8)
#define BX_CPUID_EXT3_ENCHANCED_REP_STRINGS (1 << 9)
#define BX_CPUID_EXT3_INVPCID (1 << 10)
#define BX_CPUID_EXT3_RTM (1 << 11)
// ...