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few fixes in new disasm module

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This commit is contained in:
Stanislav Shwartsman 2013-09-30 20:16:52 +00:00
parent fd383435f0
commit 147d788022
3 changed files with 65 additions and 37 deletions
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71
bochs/cpu/disasm.cc
View File

@ -82,21 +82,37 @@ static const char *intel_segment_name[8] = {
char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regname[])
{
unsigned ops = 0;
if (i->sibBase() != BX_NIL_REGISTER) {
disbufptr = dis_sprintf(disbufptr, "%s", regname[i->sibBase()]);
ops++;
}
if (i->sibIndex() != BX_NIL_REGISTER) {
if (ops > 0) {
disbufptr = dis_putc(disbufptr, '+');
if (i->sibBase() == BX_NIL_REGISTER)
{
if (i->sibIndex() == BX_NIL_REGISTER)
{
if (! i->os32L()) {
if (i->displ16s() != 0) {
disbufptr = dis_sprintf(disbufptr, "0x%04x", (Bit32u) (Bit16u) i->displ16s());
}
}
else {
if (i->displ32s() != 0) {
disbufptr = dis_sprintf(disbufptr, "0x%08x", (Bit32u) i->displ32s());
}
}
return disbufptr;
}
disbufptr = dis_sprintf(disbufptr, "%s", regname[i->sibIndex()]);
if (i->sibScale() > 1)
disbufptr = dis_sprintf(disbufptr, "[%s", regname[i->sibIndex()]);
if (i->sibScale())
disbufptr = dis_sprintf(disbufptr, "*%d", 1 << i->sibScale());
}
else {
disbufptr = dis_sprintf(disbufptr, "[%s", regname[i->sibBase()]);
if (i->sibIndex() != BX_NIL_REGISTER)
{
disbufptr = dis_sprintf(disbufptr, "+%s", regname[i->sibIndex()]);
if (i->sibScale())
disbufptr = dis_sprintf(disbufptr, "*%d", 1 << i->sibScale());
}
}
if (! i->os32L()) {
if (i->displ16s() != 0) {
@ -104,19 +120,19 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regn
}
}
else {
if (i->displ16s() != 0) {
disbufptr = dis_sprintf(disbufptr, "%+d", (Bit32s) i->displ32s());
if (i->displ32s() != 0) {
disbufptr = dis_sprintf(disbufptr, "%+d", i->displ32s());
}
}
disbufptr = dis_putc(disbufptr, ']');
return disbufptr;
}
char *resolve_memref(char *disbufptr, const bxInstruction_c *i)
{
// [base + index*scale + disp]
disbufptr = dis_sprintf(disbufptr, "%s:[", intel_segment_name[i->seg()]);
// seg:[base + index*scale + disp]
disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
if (i->os64L()) {
disbufptr = resolve_memref(disbufptr, i, intel_general_64bit_regname);
}
@ -126,7 +142,6 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i)
else {
disbufptr = resolve_memref(disbufptr, i, intel_general_16bit_regname);
}
disbufptr = dis_putc(disbufptr, ']');
return disbufptr;
}
@ -239,6 +254,12 @@ void disasm(char *disbufptr, const bxInstruction_c *i)
case BX_IMMQ:
disbufptr = dis_sprintf(disbufptr, "0x" FMT_LL "x", i->Iq());
break;
case BX_IMMB2:
disbufptr = dis_sprintf(disbufptr, "0x%02x", i->Ib2());
break;
case BX_IMMW2:
disbufptr = dis_sprintf(disbufptr, "0x%04x", i->Iw2());
break;
case BX_IMM_BrOff16:
disbufptr = dis_sprintf(disbufptr, ".%+d", i->Iw());
break;
@ -246,25 +267,27 @@ void disasm(char *disbufptr, const bxInstruction_c *i)
disbufptr = dis_sprintf(disbufptr, ".%+d", i->Id());
break;
case BX_RSIREF:
disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
if (i->as64L()) {
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_64bit_regname[BX_64BIT_REG_RSI]);
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_64bit_regname[BX_64BIT_REG_RSI]);
}
else {
if (i->as32L())
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_32bit_regname[BX_32BIT_REG_ESI]);
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_32bit_regname[BX_32BIT_REG_ESI]);
else
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_16bit_regname[BX_16BIT_REG_SI]);
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_16bit_regname[BX_16BIT_REG_SI]);
}
break;
case BX_RDIREF:
disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
if (i->as64L()) {
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_64bit_regname[BX_64BIT_REG_RDI]);
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_64bit_regname[BX_64BIT_REG_RDI]);
}
else {
if (i->as32L())
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_32bit_regname[BX_32BIT_REG_EDI]);
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_32bit_regname[BX_32BIT_REG_EDI]);
else
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_16bit_regname[BX_16BIT_REG_DI]);
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_16bit_regname[BX_16BIT_REG_DI]);
}
break;
default:

13
bochs/cpu/fetchdecode.h
View File

@ -104,10 +104,12 @@ enum {
BX_IMMW = 0x11,
BX_IMMD = 0x12,
BX_IMMQ = 0x13,
BX_IMM_BrOff16 = 0x14,
BX_IMM_BrOff32 = 0x15,
BX_RSIREF = 0x16,
BX_RDIREF = 0x17
BX_IMMB2 = 0x14,
BX_IMMW2 = 0x15,
BX_IMM_BrOff16 = 0x16,
BX_IMM_BrOff32 = 0x17,
BX_RSIREF = 0x18,
BX_RDIREF = 0x19
};
#define BX_FORM_SRC(type, src) (((type) << 3) | (src))
@ -139,6 +141,9 @@ const Bit8u OP_Iw = BX_FORM_SRC(BX_IMMW, BX_SRC_NONE);
const Bit8u OP_Id = BX_FORM_SRC(BX_IMMD, BX_SRC_NONE);
const Bit8u OP_Iq = BX_FORM_SRC(BX_IMMQ, BX_SRC_NONE);
const Bit8u OP_Ib2 = BX_FORM_SRC(BX_IMMB2, BX_SRC_NONE);
const Bit8u OP_Iw2 = BX_FORM_SRC(BX_IMMW2, BX_SRC_NONE);
const Bit8u OP_Jw = BX_FORM_SRC(BX_IMM_BrOff16, BX_SRC_NONE);
const Bit8u OP_Jd = BX_FORM_SRC(BX_IMM_BrOff32, BX_SRC_NONE);
const Bit8u OP_Jq = BX_FORM_SRC(BX_IMM_BrOff32, BX_SRC_NONE); /* always same as OP_Jd ? */

18
bochs/cpu/ia_opcodes.h
View File

@ -271,8 +271,8 @@ bx_define_opcode(BX_IA_CALL_Ed, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CALL_EdR, 0, OP_E
bx_define_opcode(BX_IA_CALL_Ew, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::CALL_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Jd, NULL, &BX_CPU_C::CALL_Jd, 0, OP_Jd, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Jw, NULL, &BX_CPU_C::CALL_Jw, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op16_Ap, NULL, &BX_CPU_C::CALL16_Ap, 0, OP_Iw, OP_Iw, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op32_Ap, NULL, &BX_CPU_C::CALL32_Ap, 0, OP_Id, OP_Iw, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op16_Ap, NULL, &BX_CPU_C::CALL16_Ap, 0, OP_Iw, OP_Iw2, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op32_Ap, NULL, &BX_CPU_C::CALL32_Ap, 0, OP_Id, OP_Iw2, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op16_Ep, &BX_CPU_C::CALL16_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op32_Ep, &BX_CPU_C::CALL32_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
@ -288,8 +288,8 @@ bx_define_opcode(BX_IA_CWD, NULL, &BX_CPU_C::CWD, 0, OP_NONE, OP_NONE, OP_NONE,
bx_define_opcode(BX_IA_CWDE, NULL, &BX_CPU_C::CWDE, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_HLT, NULL, &BX_CPU_C::HLT, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_ENTER_Op16_IwIb, NULL, &BX_CPU_C::ENTER16_IwIb, 0, OP_Iw, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_ENTER_Op32_IwIb, NULL, &BX_CPU_C::ENTER32_IwIb, 0, OP_Iw, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_ENTER_Op16_IwIb, NULL, &BX_CPU_C::ENTER16_IwIb, 0, OP_Iw, OP_Ib2, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_ENTER_Op32_IwIb, NULL, &BX_CPU_C::ENTER32_IwIb, 0, OP_Iw, OP_Ib2, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_LEAVE_Op16, NULL, &BX_CPU_C::LEAVE16, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_LEAVE_Op32, NULL, &BX_CPU_C::LEAVE32, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
@ -324,8 +324,8 @@ bx_define_opcode(BX_IA_JMP_Ew, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::JMP_EwR, 0, OP_Ew,
bx_define_opcode(BX_IA_JMP_Jw, NULL, &BX_CPU_C::JMP_Jw, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Jd, NULL, &BX_CPU_C::JMP_Jd, 0, OP_Jd, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op16_Ap, NULL, &BX_CPU_C::JMP_Ap, 0, OP_Iw, OP_Iw, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op32_Ap, NULL, &BX_CPU_C::JMP_Ap, 0, OP_Id, OP_Iw, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op16_Ap, NULL, &BX_CPU_C::JMP_Ap, 0, OP_Iw, OP_Iw2, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op32_Ap, NULL, &BX_CPU_C::JMP_Ap, 0, OP_Id, OP_Iw2, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op16_Ep, &BX_CPU_C::JMP16_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op32_Ep, &BX_CPU_C::JMP32_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
@ -1412,7 +1412,7 @@ bx_define_opcode(BX_IA_JNL_Jq, NULL, &BX_CPU_C::JNL_Jq, 0, OP_Jq, OP_NONE, OP_NO
bx_define_opcode(BX_IA_JLE_Jq, NULL, &BX_CPU_C::JLE_Jq, 0, OP_Jq, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_JNLE_Jq, NULL, &BX_CPU_C::JNLE_Jq, 0, OP_Jq, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_ENTER_Op64_IwIb, NULL, &BX_CPU_C::ENTER64_IwIb, 0, OP_Iw, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_ENTER_Op64_IwIb, NULL, &BX_CPU_C::ENTER64_IwIb, 0, OP_Iw, OP_Ib2, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_LEAVE_Op64, NULL, &BX_CPU_C::LEAVE64, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_IRET_Op64, NULL, &BX_CPU_C::IRET64, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
@ -2409,9 +2409,9 @@ bx_define_opcode(BX_IA_LZCNT_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::LZCNT_GqEqR, B
// SSE4A
bx_define_opcode(BX_IA_MOVNTSS_MssVss, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::BxError, BX_ISA_SSE4A, OP_Wss, OP_Vss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVNTSD_MsdVsd, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::BxError, BX_ISA_SSE4A, OP_Wsd, OP_Vsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_EXTRQ_UdqIbIb, &BX_CPU_C::BxError, &BX_CPU_C::EXTRQ_UdqIbIb, BX_ISA_SSE4A, OP_Wdq, OP_Ib, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_EXTRQ_UdqIbIb, &BX_CPU_C::BxError, &BX_CPU_C::EXTRQ_UdqIbIb, BX_ISA_SSE4A, OP_Wdq, OP_Ib, OP_Ib2, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_EXTRQ_VdqUq, &BX_CPU_C::BxError, &BX_CPU_C::EXTRQ_VdqUq, BX_ISA_SSE4A, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_INSERTQ_VdqUqIbIb, &BX_CPU_C::BxError, &BX_CPU_C::INSERTQ_VdqUqIbIb, BX_ISA_SSE4A, OP_Vdq, OP_Wq, OP_Ib, OP_Ib, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_INSERTQ_VdqUqIbIb, &BX_CPU_C::BxError, &BX_CPU_C::INSERTQ_VdqUqIbIb, BX_ISA_SSE4A, OP_Vdq, OP_Wq, OP_Ib, OP_Ib2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_INSERTQ_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::INSERTQ_VdqUdq, BX_ISA_SSE4A, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
// SSE4A