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fixed evex override mscsr controls

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This commit is contained in:
Stanislav Shwartsman 2013-09-19 21:38:25 +00:00
parent 0441f82b02
commit 3803ac7fbe
5 changed files with 85 additions and 157 deletions
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96
bochs/cpu/avx512_pfp.cc
View File

@ -42,9 +42,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPS_MASK_VpsHpsWpsR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4) {
xmm_addps_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -69,9 +67,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPD_MASK_VpdHpdWpdR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2) {
xmm_addpd_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -98,8 +94,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSS_MASK_VssHpsWssR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm32u(0) = float32_add(op1.xmm32u(0), op2, status);
@ -127,8 +122,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSD_MASK_VsdHpdWsdR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm64u(0) = float64_add(op1.xmm64u(0), op2, status);
@ -154,9 +148,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPS_MASK_VpsHpsWpsR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4) {
xmm_subps_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -181,9 +173,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPD_MASK_VpdHpdWpdR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2) {
xmm_subpd_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -210,8 +200,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSS_MASK_VssHpsWssR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm32u(0) = float32_sub(op1.xmm32u(0), op2, status);
@ -239,8 +228,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSD_MASK_VsdHpdWsdR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm64u(0) = float64_sub(op1.xmm64u(0), op2, status);
@ -266,9 +254,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPS_MASK_VpsHpsWpsR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4) {
xmm_mulps_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -293,9 +279,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPD_MASK_VpdHpdWpdR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2) {
xmm_mulpd_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -322,8 +306,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSS_MASK_VssHpsWssR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm32u(0) = float32_mul(op1.xmm32u(0), op2, status);
@ -351,8 +334,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSD_MASK_VsdHpdWsdR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm64u(0) = float64_mul(op1.xmm64u(0), op2, status);
@ -378,9 +360,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPS_MASK_VpsHpsWpsR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4) {
xmm_divps_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -405,9 +385,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPD_MASK_VpdHpdWpdR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2) {
xmm_divpd_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -434,8 +412,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSS_MASK_VssHpsWssR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm32u(0) = float32_div(op1.xmm32u(0), op2, status);
@ -463,8 +440,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSD_MASK_VsdHpdWsdR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm64u(0) = float64_div(op1.xmm64u(0), op2, status);
@ -490,9 +466,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPS_MASK_VpsHpsWpsR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4) {
xmm_minps_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -517,9 +491,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPD_MASK_VpdHpdWpdR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2) {
xmm_minpd_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -543,14 +515,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSS_MASK_VssHpsWssR(bxInstructi
if (mask & 0x1) {
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2());
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm32u(0) = float32_min(op1.xmm32u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
}
else {
@ -572,14 +540,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSD_MASK_VsdHpdWsdR(bxInstructi
if (mask & 0x1) {
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2());
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm64u(0) = float64_min(op1.xmm64u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
}
else {
@ -602,9 +566,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPS_MASK_VpsHpsWpsR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4) {
xmm_maxps_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -629,9 +591,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPD_MASK_VpdHpdWpdR(bxInstructi
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2) {
xmm_maxpd_mask(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);
@ -655,14 +615,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSS_MASK_VssHpsWssR(bxInstructi
if (mask & 0x1) {
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->src2());
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm32u(0) = float32_max(op1.xmm32u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
}
else {
@ -684,14 +640,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSD_MASK_VsdHpdWsdR(bxInstructi
if (mask & 0x1) {
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->src2());
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
op1.xmm64u(0) = float64_max(op1.xmm64u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
}
else {

90
bochs/cpu/avx_pfp.cc
View File

@ -327,8 +327,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -351,8 +350,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -375,8 +373,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSS_VssHpsWssR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm32u(0) = float32_add(op1.xmm32u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -394,8 +391,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSD_VsdHpdWsdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm64u(0) = float64_add(op1.xmm64u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -413,8 +409,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -437,8 +432,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -461,8 +455,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSS_VssHpsWssR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm32u(0) = float32_mul(op1.xmm32u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -480,8 +473,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSD_VsdHpdWsdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm64u(0) = float64_mul(op1.xmm64u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -634,8 +626,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -658,8 +649,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -682,8 +672,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSS_VssHpsWssR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm32u(0) = float32_sub(op1.xmm32u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -701,8 +690,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSD_VsdHpdWsdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm64u(0) = float64_sub(op1.xmm64u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -720,8 +708,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -744,8 +731,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -768,8 +754,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSS_VssHpsWssR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm32u(0) = float32_min(op1.xmm32u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -788,8 +773,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSD_VsdHpdWsdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm64u(0) = float64_min(op1.xmm64u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -808,8 +792,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -832,8 +815,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -856,8 +838,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSS_VssHpsWssR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm32u(0) = float32_div(op1.xmm32u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -875,8 +856,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSD_VsdHpdWsdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm64u(0) = float64_div(op1.xmm64u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -894,8 +874,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -918,8 +897,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -942,8 +920,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSS_VssHpsWssR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm32u(0) = float32_max(op1.xmm32u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -962,8 +939,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSD_VsdHpdWsdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, BX_VL512);
#endif
op1.xmm64u(0) = float64_max(op1.xmm64u(0), op2, status);
check_exceptionsSSE(status.float_exception_flags);
@ -982,8 +958,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -1006,8 +981,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -1030,8 +1004,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -1054,8 +1027,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -1163,8 +1135,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPD_VpdHpdWpdR(bxInstruction
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {
@ -1187,8 +1158,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPS_VpsHpsWpsR(bxInstruction
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
#if BX_SUPPORT_EVEX
if (len == BX_VL512 && i->modC0() && i->getEvexb())
status.float_rounding_mode = i->getRC();
evex_softfloat_status_word_override(status, i, len);
#endif
for (unsigned n=0; n < len; n++) {

2
bochs/cpu/fpu/softfloat.h
View File

@ -91,6 +91,8 @@ enum float_exception_flag_t {
float_flag_inexact = 0x20
};
const unsigned float_all_exceptions_mask = 0x3f;
#ifdef FLOATX80
#define RAISE_SW_C1 0x0200
#endif

38
bochs/cpu/simd_int.h
View File

@ -505,26 +505,26 @@ BX_CPP_INLINE void xmm_blendvpd(BxPackedXmmRegister *op1, const BxPackedXmmRegis
BX_CPP_INLINE void xmm_andps(BxPackedXmmRegister *op1, const BxPackedXmmRegister *op2)
{
op1->xmm64u(0) &= op2->xmm64u(0);
op1->xmm64u(1) &= op2->xmm64u(1);
for (unsigned n=0; n < 2; n++)
op1->xmm64u(n) &= op2->xmm64u(n);
}
BX_CPP_INLINE void xmm_andnps(BxPackedXmmRegister *op1, const BxPackedXmmRegister *op2)
{
op1->xmm64u(0) = ~(op1->xmm64u(0)) & op2->xmm64u(0);
op1->xmm64u(1) = ~(op1->xmm64u(1)) & op2->xmm64u(1);
for (unsigned n=0; n < 2; n++)
op1->xmm64u(n) = ~(op1->xmm64u(n)) & op2->xmm64u(n);
}
BX_CPP_INLINE void xmm_orps(BxPackedXmmRegister *op1, const BxPackedXmmRegister *op2)
{
op1->xmm64u(0) |= op2->xmm64u(0);
op1->xmm64u(1) |= op2->xmm64u(1);
for (unsigned n=0; n < 2; n++)
op1->xmm64u(n) |= op2->xmm64u(n);
}
BX_CPP_INLINE void xmm_xorps(BxPackedXmmRegister *op1, const BxPackedXmmRegister *op2)
{
op1->xmm64u(0) ^= op2->xmm64u(0);
op1->xmm64u(1) ^= op2->xmm64u(1);
for (unsigned n=0; n < 2; n++)
op1->xmm64u(n) ^= op2->xmm64u(n);
}
// arithmetic (add/sub)
@ -883,25 +883,13 @@ BX_CPP_INLINE void simd_pbroadcastq(BxPackedZmmRegister *op, Bit64u val_64, unsi
BX_CPP_INLINE void xmm_psadbw(BxPackedXmmRegister *op1, const BxPackedXmmRegister *op2)
{
Bit16u temp1 = 0, temp2 = 0;
unsigned temp1 = 0, temp2 = 0, n;
temp1 += abs(op1->xmmubyte(0x0) - op2->xmmubyte(0x0));
temp1 += abs(op1->xmmubyte(0x1) - op2->xmmubyte(0x1));
temp1 += abs(op1->xmmubyte(0x2) - op2->xmmubyte(0x2));
temp1 += abs(op1->xmmubyte(0x3) - op2->xmmubyte(0x3));
temp1 += abs(op1->xmmubyte(0x4) - op2->xmmubyte(0x4));
temp1 += abs(op1->xmmubyte(0x5) - op2->xmmubyte(0x5));
temp1 += abs(op1->xmmubyte(0x6) - op2->xmmubyte(0x6));
temp1 += abs(op1->xmmubyte(0x7) - op2->xmmubyte(0x7));
for (n=0; n < 8; n++)
temp1 += abs(op1->xmmubyte(n) - op2->xmmubyte(n));
temp2 += abs(op1->xmmubyte(0x8) - op2->xmmubyte(0x8));
temp2 += abs(op1->xmmubyte(0x9) - op2->xmmubyte(0x9));
temp2 += abs(op1->xmmubyte(0xA) - op2->xmmubyte(0xA));
temp2 += abs(op1->xmmubyte(0xB) - op2->xmmubyte(0xB));
temp2 += abs(op1->xmmubyte(0xC) - op2->xmmubyte(0xC));
temp2 += abs(op1->xmmubyte(0xD) - op2->xmmubyte(0xD));
temp2 += abs(op1->xmmubyte(0xE) - op2->xmmubyte(0xE));
temp2 += abs(op1->xmmubyte(0xF) - op2->xmmubyte(0xF));
for (; n < 16; n++)
temp2 += abs(op1->xmmubyte(n) - op2->xmmubyte(n));
op1->xmm64u(0) = Bit64u(temp1);
op1->xmm64u(1) = Bit64u(temp2);

16
bochs/cpu/xmm.h
View File

@ -374,6 +374,18 @@ typedef BxPackedYmmRegister BxPackedAvxRegister;
#endif
#if BX_SUPPORT_EVEX
// implement SAE and EVEX encoded rounding control
BX_CPP_INLINE void evex_softfloat_status_word_override(float_status_t &status, bxInstruction_c *i, unsigned vl)
{
/* must be VL512 otherwise EVEX.LL encodes vector length */
if (vl == BX_VL512 && i->modC0() && i->getEvexb()) {
status.float_rounding_mode = i->getRC();
status.float_exception_masks = float_all_exceptions_mask;
}
}
#endif
/* MXCSR REGISTER */
/* 31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16
@ -466,6 +478,10 @@ struct BOCHSAPI bx_mxcsr_t
mxcsr |= (status & MXCSR_EXCEPTIONS);
}
void mask_all_exceptions() {
mxcsr |= (MXCSR_MASKED_EXCEPTIONS);
}
};
#if defined(NEED_CPU_REG_SHORTCUTS)