improved debug prints in MOV to/from CR
SVM bugfix remove redundant TLB flush call from SVM and VMX code
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56cce60be8
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@ -543,7 +543,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR2(bxInstruction_c *i)
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{
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// CPL is always 0 in real mode
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if (/* !real_mode() && */ CPL!=0) {
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BX_ERROR(("MOV_RdCd: CPL!=0 not in real mode"));
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BX_ERROR(("MOV_RdCR2: CPL!=0 not in real mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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@ -562,7 +562,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR3(bxInstruction_c *i)
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{
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// CPL is always 0 in real mode
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if (/* !real_mode() && */ CPL!=0) {
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BX_ERROR(("MOV_RdCd: CPL!=0 not in real mode"));
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BX_ERROR(("MOV_RdCR3: CPL!=0 not in real mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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@ -589,7 +589,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR4(bxInstruction_c *i)
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#if BX_CPU_LEVEL >= 5
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// CPL is always 0 in real mode
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if (/* !real_mode() && */ CPL!=0) {
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BX_ERROR(("MOV_RdCd: CPL!=0 not in real mode"));
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BX_ERROR(("MOV_RdCR4: CPL!=0 not in real mode"));
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exception(BX_GP_EXCEPTION, 0);
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}
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@ -703,7 +703,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR4Rq(bxInstruction_c *i)
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if (BX_CPU_THIS_PTR in_vmx_guest)
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val_64 = VMexit_CR4_Write(i, val_64);
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#endif
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BX_DEBUG(("MOV_CqRq: write to CR4 of %08x:%08x", GET32H(val_64), GET32L(val_64)));
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if (! SetCR4(val_64))
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exception(BX_GP_EXCEPTION, 0);
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@ -715,7 +714,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR4Rq(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR0(bxInstruction_c *i)
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{
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if (CPL!=0) {
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BX_ERROR(("MOV_RqCq: #GP(0) if CPL is not 0"));
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BX_ERROR(("MOV_RqCR0: #GP(0) if CPL is not 0"));
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exception(BX_GP_EXCEPTION, 0);
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}
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@ -415,6 +415,10 @@ bx_bool BX_CPU_C::SvmEnterLoadCheckGuestState(void)
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return 0;
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}
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// always assign EFER.LMA := EFER.LME & CR0.PG
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if (guest.cr0.get_PG() & guest.efer.get_LME())
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guest.efer.set_LMA(1);
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guest.cr2 = vmcb_read64(SVM_GUEST_CR2);
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guest.cr3 = vmcb_read64(SVM_GUEST_CR3);
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@ -526,8 +530,6 @@ bx_bool BX_CPU_C::SvmEnterLoadCheckGuestState(void)
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BX_CPU_THIS_PTR dr6.set32(guest.dr6);
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BX_CPU_THIS_PTR dr7.set32(guest.dr7 | 0x400);
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TLB_flush(); // CR0/CR4 updated
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for (n=0;n < 4; n++) {
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BX_CPU_THIS_PTR sregs[n] = guest.sregs[n];
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}
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@ -1535,10 +1535,6 @@ Bit32u BX_CPU_C::VMenterLoadCheckGuestState(Bit64u *qualification)
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BX_CPU_THIS_PTR cr4.set32((Bit32u) guest.cr4);
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BX_CPU_THIS_PTR cr3 = guest.cr3;
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// flush TLB is always needed to invalidate possible
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// APIC ACCESS PAGE caching by host
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TLB_flush();
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#if BX_SUPPORT_VMX >= 2
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if (vm->vmexec_ctrls3 & VMX_VM_EXEC_CTRL3_EPT_ENABLE) {
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// load PDPTR only in PAE legacy mode
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@ -1926,8 +1922,6 @@ void BX_CPU_C::VMexitLoadHostState(void)
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BX_CPU_THIS_PTR cr4.set32((Bit32u) host_state->cr4);
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BX_CPU_THIS_PTR cr3 = host_state->cr3;
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TLB_flush(); // CR0/CR4 updated
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if (! x86_64_host && BX_CPU_THIS_PTR cr4.get_PAE()) {
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if (! CheckPDPTR(host_state->cr3)) {
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BX_ERROR(("VMABORT: host PDPTRs are corrupted !"));
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