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fixes for disasm

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This commit is contained in:
Stanislav Shwartsman 2013-10-02 19:23:34 +00:00
parent 8c60799e72
commit 85b0402668
9 changed files with 99 additions and 69 deletions
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12
bochs/cpu/cpu.h
View File

@ -3742,9 +3742,9 @@ public: // for now...
BX_SMF bx_bool handleWaitForEvent(void);
BX_SMF void InterruptAcknowledge(void);
BX_SMF int fetchDecode32(const Bit8u *fetchPtr, bxInstruction_c *i, unsigned remainingInPage) BX_CPP_AttrRegparmN(3);
BX_SMF int fetchDecode32(const Bit8u *fetchPtr, Bit32u fetchModeMask, bxInstruction_c *i, unsigned remainingInPage) BX_CPP_AttrRegparmN(3);
#if BX_SUPPORT_X86_64
BX_SMF int fetchDecode64(const Bit8u *fetchPtr, bxInstruction_c *i, unsigned remainingInPage) BX_CPP_AttrRegparmN(3);
BX_SMF int fetchDecode64(const Bit8u *fetchPtr, Bit32u fetchModeMask, bxInstruction_c *i, unsigned remainingInPage) BX_CPP_AttrRegparmN(3);
#endif
BX_SMF void boundaryFetch(const Bit8u *fetchPtr, unsigned remainingInPage, bxInstruction_c *);
BX_SMF bxICacheEntry_c *serveICacheMiss(bxICacheEntry_c *entry, Bit32u eipBiased, bx_phy_address pAddr);
@ -4680,6 +4680,14 @@ BX_CPP_INLINE void BX_CPU_C::prepareXSAVE(void)
// bit 2 - SSE_OK
// bit 3 - AVX_OK
// bit 4 - EVEX_OK
//
#define BX_FETCH_MODE_IS32_MASK (1 << 0)
#define BX_FETCH_MODE_IS64_MASK (1 << 1)
#define BX_FETCH_MODE_SSE_MASK (1 << 2)
#define BX_FETCH_MODE_AVX_MASK (1 << 3)
#define BX_FETCH_MODE_EVEX_MASK (1 << 4)
//
// updateFetchModeMask - has to be called everytime
// CS.L / CS.D_B / CR0.PE, CR0.TS or CR0.EM / CR4.OSFXSR / CR4.OSXSAVE changes

43
bochs/cpu/disasm.cc
View File

@ -88,9 +88,11 @@ static const char *rounding_mode[4] = {
char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regname[])
{
if (i->sibBase() == BX_NIL_REGISTER)
unsigned sib_base = i->sibBase(), sib_index = i->sibIndex(), sib_scale = i->sibScale();
if (sib_base == BX_NIL_REGISTER)
{
if (i->sibIndex() == BX_NIL_REGISTER)
if (sib_index == BX_NIL_REGISTER)
{
if (! i->os32L()) {
if (i->displ16s() != 0) {
@ -106,16 +108,16 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regn
}
disbufptr = dis_sprintf(disbufptr, "[%s", regname[i->sibIndex()]);
if (i->sibScale())
if (sib_scale)
disbufptr = dis_sprintf(disbufptr, "*%d", 1 << i->sibScale());
}
else {
disbufptr = dis_sprintf(disbufptr, "[%s", regname[i->sibBase()]);
if (i->sibIndex() != BX_NIL_REGISTER)
if (sib_index != BX_NIL_REGISTER)
{
disbufptr = dis_sprintf(disbufptr, "+%s", regname[i->sibIndex()]);
if (i->sibScale())
if (sib_scale)
disbufptr = dis_sprintf(disbufptr, "*%d", 1 << i->sibScale());
}
}
@ -139,10 +141,10 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i)
{
// seg:[base + index*scale + disp]
disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
if (i->os64L()) {
if (i->as64L()) {
disbufptr = resolve_memref(disbufptr, i, intel_general_64bit_regname);
}
else if (i->os32L()) {
else if (i->as32L()) {
disbufptr = resolve_memref(disbufptr, i, intel_general_32bit_regname);
}
else {
@ -153,10 +155,12 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i)
char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_address rip)
{
#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS
if (i->getIaOpcode() == BX_INSERTED_OPCODE) {
disbufptr = dis_sprintf(disbufptr, "(bochs inserted internal opcode)");
return disbufptr;
}
#endif
if (i->execute1 == BX_CPU_C::BxError) {
disbufptr = dis_sprintf(disbufptr, "(invalid)");
@ -178,14 +182,14 @@ char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_a
if (! strncmp(opname, "REP_", 4)) {
opname += 4;
}
// Step 1: print prefixes
if (i->repUsedL()) {
if (i->repUsedValue() == 2)
disbufptr = dis_sprintf(disbufptr, "repne ");
else
disbufptr = dis_sprintf(disbufptr, "rep ");
// Step 1: print prefixes
if (i->repUsedL()) {
if (i->repUsedValue() == 2)
disbufptr = dis_sprintf(disbufptr, "repne ");
else
disbufptr = dis_sprintf(disbufptr, "rep ");
}
}
// Step 2: print opcode name
@ -286,14 +290,11 @@ char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_a
disbufptr = dis_sprintf(disbufptr, "0x%08x", i->Id());
break;
case BX_IMMQ:
disbufptr = dis_sprintf(disbufptr, "0x" FMT_LL "x", i->Iq());
disbufptr = dis_sprintf(disbufptr, "0x" FMT_ADDRX64, i->Iq());
break;
case BX_IMMB2:
disbufptr = dis_sprintf(disbufptr, "0x%02x", i->Ib2());
break;
case BX_IMMW2:
disbufptr = dis_sprintf(disbufptr, "0x%04x", i->Iw2());
break;
case BX_IMM_BrOff16:
{
Bit16u target = (rip + i->ilen() + (Bit16s) i->Iw()) & 0xffff;
@ -336,6 +337,12 @@ char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_a
case BX_USEDX:
disbufptr = dis_sprintf(disbufptr, "dx");
break;
case BX_DIRECT_PTR:
if (i->os32L())
disbufptr = dis_sprintf(disbufptr, "0x%04x:%08x", i->Iw2(), i->Id());
else
disbufptr = dis_sprintf(disbufptr, "0x%04x:%04x", i->Iw2(), i->Iw());
break;
case BX_DIRECT_MEMREF32:
disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
if (! i->as32L())

25
bochs/cpu/fetchdecode.cc
View File

@ -331,7 +331,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 97 /w */ { 0, BX_IA_XCHG_RXAX },
/* 98 /w */ { 0, BX_IA_CBW },
/* 99 /w */ { 0, BX_IA_CWD },
/* 9A /w */ { BxImmediate_Iw | BxImmediate_Iw2, BX_IA_CALL_Op16_Ap },
/* 9A /w */ { BxImmediate_Iw | BxImmediate_Iw2, BX_IA_CALLFAR_Op16_Ap },
/* 9B /w */ { 0, BX_IA_FWAIT },
/* 9C /w */ { 0, BX_IA_PUSHF_Fw },
/* 9D /w */ { 0, BX_IA_POPF_Fw },
@ -422,7 +422,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* E7 /w */ { BxImmediate_Ib, BX_IA_OUT_IbAX },
/* E8 /w */ { BxImmediate_BrOff16, BX_IA_CALL_Jw },
/* E9 /w */ { BxImmediate_BrOff16, BX_IA_JMP_Jw },
/* EA /w */ { BxImmediate_Iw | BxImmediate_Iw2, BX_IA_JMP_Op16_Ap },
/* EA /w */ { BxImmediate_Iw | BxImmediate_Iw2, BX_IA_JMPFAR_Ap },
/* EB /w */ { BxImmediate_BrOff8, BX_IA_JMP_Jw },
/* EC /w */ { 0, BX_IA_IN_ALDX },
/* ED /w */ { 0, BX_IA_IN_AXDX },
@ -876,7 +876,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 97 /d */ { 0, BX_IA_XCHG_ERXEAX },
/* 98 /d */ { 0, BX_IA_CWDE },
/* 99 /d */ { 0, BX_IA_CDQ },
/* 9A /d */ { BxImmediate_Id | BxImmediate_Iw2, BX_IA_CALL_Op32_Ap },
/* 9A /d */ { BxImmediate_Id | BxImmediate_Iw2, BX_IA_CALLFAR_Op32_Ap },
/* 9B /d */ { 0, BX_IA_FWAIT },
/* 9C /d */ { 0, BX_IA_PUSHF_Fd },
/* 9D /d */ { 0, BX_IA_POPF_Fd },
@ -967,7 +967,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* E7 /d */ { BxImmediate_Ib, BX_IA_OUT_IbEAX },
/* E8 /d */ { BxImmediate_BrOff32, BX_IA_CALL_Jd },
/* E9 /d */ { BxImmediate_BrOff32, BX_IA_JMP_Jd },
/* EA /d */ { BxImmediate_Id | BxImmediate_Iw2, BX_IA_JMP_Op32_Ap },
/* EA /d */ { BxImmediate_Id | BxImmediate_Iw2, BX_IA_JMPFAR_Ap },
/* EB /d */ { BxImmediate_BrOff8, BX_IA_JMP_Jd },
/* EC /d */ { 0, BX_IA_IN_ALDX },
/* ED /d */ { 0, BX_IA_IN_EAXDX },
@ -1268,7 +1268,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
};
int BX_CPP_AttrRegparmN(3)
BX_CPU_C::fetchDecode32(const Bit8u *iptr, bxInstruction_c *i, unsigned remainingInPage)
BX_CPU_C::fetchDecode32(const Bit8u *iptr, Bit32u fetchModeMask, bxInstruction_c *i, unsigned remainingInPage)
{
if (remainingInPage > 15) remainingInPage = 15;
@ -1289,8 +1289,7 @@ BX_CPU_C::fetchDecode32(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
bx_bool vex_w = 0, vex_l = 0, use_vvv = 0;
#endif
os_32 = is_32 =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b;
os_32 = is_32 = fetchModeMask & BX_FETCH_MODE_IS32_MASK;
i->ResolveModrm = 0;
i->init(/*os32*/ is_32, /*as32*/ is_32,
@ -1992,19 +1991,27 @@ decode_done:
#if BX_CPU_LEVEL >= 6
Bit32u op_flags = BxOpcodesTable[ia_opcode].opflags;
if (! BX_CPU_THIS_PTR sse_ok) {
if (! (fetchModeMask & BX_FETCH_MODE_SSE_MASK)) {
if (op_flags & BX_PREPARE_SSE) {
if (i->execute1 != &BX_CPU_C::BxError) i->execute1 = &BX_CPU_C::BxNoSSE;
return(1);
}
}
#if BX_SUPPORT_AVX
if (! BX_CPU_THIS_PTR avx_ok) {
if (! (fetchModeMask & BX_FETCH_MODE_AVX_MASK)) {
if (op_flags & BX_PREPARE_AVX) {
if (i->execute1 != &BX_CPU_C::BxError) i->execute1 = &BX_CPU_C::BxNoAVX;
return(1);
}
}
#if BX_SUPPORT_EVEX
if (! (fetchModeMask & BX_FETCH_MODE_EVEX_MASK)) {
if (op_flags & BX_PREPARE_EVEX) {
if (i->execute1 != &BX_CPU_C::BxError) i->execute1 = &BX_CPU_C::BxNoEVEX;
return(1);
}
}
#endif
#endif
#endif

37
bochs/cpu/fetchdecode.h
View File

@ -105,13 +105,13 @@ enum {
BX_IMMD = 0x12,
BX_IMMQ = 0x13,
BX_IMMB2 = 0x14,
BX_IMMW2 = 0x15,
BX_IMM_BrOff16 = 0x16,
BX_IMM_BrOff32 = 0x17,
BX_RSIREF = 0x18,
BX_RDIREF = 0x19,
BX_USECL = 0x1A,
BX_USEDX = 0x1B,
BX_IMM_BrOff16 = 0x15,
BX_IMM_BrOff32 = 0x16,
BX_RSIREF = 0x17,
BX_RDIREF = 0x18,
BX_USECL = 0x19,
BX_USEDX = 0x1A,
BX_DIRECT_PTR = 0x1B,
BX_DIRECT_MEMREF32 = 0x1C,
BX_DIRECT_MEMREF64 = 0x1D,
};
@ -146,7 +146,6 @@ const Bit8u OP_Id = BX_FORM_SRC(BX_IMMD, BX_SRC_NONE);
const Bit8u OP_Iq = BX_FORM_SRC(BX_IMMQ, BX_SRC_NONE);
const Bit8u OP_Ib2 = BX_FORM_SRC(BX_IMMB2, BX_SRC_NONE);
const Bit8u OP_Iw2 = BX_FORM_SRC(BX_IMMW2, BX_SRC_NONE);
const Bit8u OP_Jw = BX_FORM_SRC(BX_IMM_BrOff16, BX_SRC_NONE);
const Bit8u OP_Jd = BX_FORM_SRC(BX_IMM_BrOff32, BX_SRC_NONE);
@ -208,6 +207,8 @@ const Bit8u OP_Sw = BX_FORM_SRC(BX_SEGREG, BX_SRC_NNN);
const Bit8u OP_Od = BX_FORM_SRC(BX_DIRECT_MEMREF32, BX_SRC_NONE);
const Bit8u OP_Oq = BX_FORM_SRC(BX_DIRECT_MEMREF64, BX_SRC_NONE);
const Bit8u OP_Ap = BX_FORM_SRC(BX_DIRECT_PTR, BX_SRC_NONE);
const Bit8u OP_KGw = BX_FORM_SRC(BX_KMASK_REG, BX_SRC_NNN);
const Bit8u OP_KEw = BX_FORM_SRC(BX_KMASK_REG, BX_SRC_RM);
const Bit8u OP_KHw = BX_FORM_SRC(BX_KMASK_REG, BX_SRC_VVV);
@ -515,9 +516,9 @@ static const BxOpcodeInfo_t BxOpcodeInfoG5w[8] = {
/* 0 */ { BxLockable, BX_IA_INC_Ew },
/* 1 */ { BxLockable, BX_IA_DEC_Ew },
/* 2 */ { 0, BX_IA_CALL_Ew },
/* 3 */ { 0, BX_IA_CALL_Op16_Ep },
/* 3 */ { 0, BX_IA_CALLFAR_Op16_Ep },
/* 4 */ { 0, BX_IA_JMP_Ew },
/* 5 */ { 0, BX_IA_JMP_Op16_Ep },
/* 5 */ { 0, BX_IA_JMPFAR_Op16_Ep },
/* 6 */ { 0, BX_IA_PUSH_Ew },
/* 7 */ { 0, BX_IA_ERROR }
};
@ -527,9 +528,9 @@ static const BxOpcodeInfo_t BxOpcodeInfoG5d[8] = {
/* 0 */ { BxLockable, BX_IA_INC_Ed },
/* 1 */ { BxLockable, BX_IA_DEC_Ed },
/* 2 */ { 0, BX_IA_CALL_Ed },
/* 3 */ { 0, BX_IA_CALL_Op32_Ep },
/* 3 */ { 0, BX_IA_CALLFAR_Op32_Ep },
/* 4 */ { 0, BX_IA_JMP_Ed },
/* 5 */ { 0, BX_IA_JMP_Op32_Ep },
/* 5 */ { 0, BX_IA_JMPFAR_Op32_Ep },
/* 6 */ { 0, BX_IA_PUSH_Ed },
/* 7 */ { 0, BX_IA_ERROR }
};
@ -539,9 +540,9 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G5w[8] = {
/* 0 */ { BxLockable, BX_IA_INC_Ew },
/* 1 */ { BxLockable, BX_IA_DEC_Ew },
/* 2 */ { 0, BX_IA_CALL_Eq },
/* 3 */ { 0, BX_IA_CALL_Op16_Ep },
/* 3 */ { 0, BX_IA_CALLFAR_Op16_Ep },
/* 4 */ { 0, BX_IA_JMP_Eq },
/* 5 */ { 0, BX_IA_JMP_Op16_Ep },
/* 5 */ { 0, BX_IA_JMPFAR_Op16_Ep },
/* 6 */ { 0, BX_IA_PUSH_Ew },
/* 7 */ { 0, BX_IA_ERROR }
};
@ -550,9 +551,9 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G5d[8] = {
/* 0 */ { BxLockable, BX_IA_INC_Ed },
/* 1 */ { BxLockable, BX_IA_DEC_Ed },
/* 2 */ { 0, BX_IA_CALL_Eq },
/* 3 */ { 0, BX_IA_CALL_Op32_Ep },
/* 3 */ { 0, BX_IA_CALLFAR_Op32_Ep },
/* 4 */ { 0, BX_IA_JMP_Eq },
/* 5 */ { 0, BX_IA_JMP_Op32_Ep },
/* 5 */ { 0, BX_IA_JMPFAR_Op32_Ep },
/* 6 */ { 0, BX_IA_PUSH_Eq },
/* 7 */ { 0, BX_IA_ERROR }
};
@ -561,9 +562,9 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G5q[8] = {
/* 0 */ { BxLockable, BX_IA_INC_Eq },
/* 1 */ { BxLockable, BX_IA_DEC_Eq },
/* 2 */ { 0, BX_IA_CALL_Eq },
/* 3 */ { 0, BX_IA_CALL_Op64_Ep }, // TODO: 64-bit offset for Intel
/* 3 */ { 0, BX_IA_CALLFAR_Op64_Ep }, // TODO: 64-bit offset for Intel
/* 4 */ { 0, BX_IA_JMP_Eq },
/* 5 */ { 0, BX_IA_JMP_Op64_Ep }, // TODO: 64-bit offset for Intel
/* 5 */ { 0, BX_IA_JMPFAR_Op64_Ep }, // TODO: 64-bit offset for Intel
/* 6 */ { 0, BX_IA_PUSH_Eq },
/* 7 */ { 0, BX_IA_ERROR }
};

14
bochs/cpu/fetchdecode64.cc
View File

@ -1685,7 +1685,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
};
int BX_CPP_AttrRegparmN(3)
BX_CPU_C::fetchDecode64(const Bit8u *iptr, bxInstruction_c *i, unsigned remainingInPage)
BX_CPU_C::fetchDecode64(const Bit8u *iptr, Bit32u fetchModeMask, bxInstruction_c *i, unsigned remainingInPage)
{
if (remainingInPage > 15) remainingInPage = 15;
@ -2439,19 +2439,27 @@ decode_done:
BX_ASSERT(i->execute1);
Bit32u op_flags = BxOpcodesTable[ia_opcode].opflags;
if (! BX_CPU_THIS_PTR sse_ok) {
if (! (fetchModeMask & BX_FETCH_MODE_SSE_MASK)) {
if (op_flags & BX_PREPARE_SSE) {
if (i->execute1 != &BX_CPU_C::BxError) i->execute1 = &BX_CPU_C::BxNoSSE;
return(1);
}
}
#if BX_SUPPORT_AVX
if (! BX_CPU_THIS_PTR avx_ok) {
if (! (fetchModeMask & BX_FETCH_MODE_AVX_MASK)) {
if (op_flags & BX_PREPARE_AVX) {
if (i->execute1 != &BX_CPU_C::BxError) i->execute1 = &BX_CPU_C::BxNoAVX;
return(1);
}
}
#if BX_SUPPORT_EVEX
if (! (fetchModeMask & BX_FETCH_MODE_EVEX_MASK)) {
if (op_flags & BX_PREPARE_EVEX) {
if (i->execute1 != &BX_CPU_C::BxError) i->execute1 = &BX_CPU_C::BxNoEVEX;
return(1);
}
}
#endif
#endif
if ((op_flags & BX_TRACE_END) != 0 || i->execute1 == &BX_CPU_C::BxError)

19
bochs/cpu/ia_opcodes.h
View File

@ -271,10 +271,10 @@ bx_define_opcode(BX_IA_CALL_Ed, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CALL_EdR, 0, OP_E
bx_define_opcode(BX_IA_CALL_Ew, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::CALL_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Jd, NULL, &BX_CPU_C::CALL_Jd, 0, OP_Jd, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Jw, NULL, &BX_CPU_C::CALL_Jw, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op16_Ap, NULL, &BX_CPU_C::CALL16_Ap, 0, OP_Iw, OP_Iw2, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op32_Ap, NULL, &BX_CPU_C::CALL32_Ap, 0, OP_Id, OP_Iw2, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op16_Ep, &BX_CPU_C::CALL16_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op32_Ep, &BX_CPU_C::CALL32_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALLFAR_Op16_Ap, NULL, &BX_CPU_C::CALL16_Ap, 0, OP_Ap, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALLFAR_Op32_Ap, NULL, &BX_CPU_C::CALL32_Ap, 0, OP_Ap, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALLFAR_Op16_Ep, &BX_CPU_C::CALL16_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALLFAR_Op32_Ep, &BX_CPU_C::CALL32_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CBW, NULL, &BX_CPU_C::CBW, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_CDQ, NULL, &BX_CPU_C::CDQ, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
@ -324,11 +324,10 @@ bx_define_opcode(BX_IA_JMP_Ew, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::JMP_EwR, 0, OP_Ew,
bx_define_opcode(BX_IA_JMP_Jw, NULL, &BX_CPU_C::JMP_Jw, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Jd, NULL, &BX_CPU_C::JMP_Jd, 0, OP_Jd, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op16_Ap, NULL, &BX_CPU_C::JMP_Ap, 0, OP_Iw, OP_Iw2, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op32_Ap, NULL, &BX_CPU_C::JMP_Ap, 0, OP_Id, OP_Iw2, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMPFAR_Ap, NULL, &BX_CPU_C::JMP_Ap, 0, OP_Ap, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op16_Ep, &BX_CPU_C::JMP16_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op32_Ep, &BX_CPU_C::JMP32_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMPFAR_Op16_Ep, &BX_CPU_C::JMP16_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMPFAR_Op32_Ep, &BX_CPU_C::JMP32_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JCXZ_Jb, NULL, &BX_CPU_C::JCXZ_Jb, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JECXZ_Jb, NULL, &BX_CPU_C::JECXZ_Jb, 0, OP_Jd, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
@ -1470,9 +1469,9 @@ bx_define_opcode(BX_IA_INC_Eq, &BX_CPU_C::INC_EqM, &BX_CPU_C::INC_EqR, 0, OP_Eq,
bx_define_opcode(BX_IA_DEC_Eq, &BX_CPU_C::DEC_EqM, &BX_CPU_C::DEC_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_CALL_Eq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::CALL_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALL_Op64_Ep, &BX_CPU_C::CALL64_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_CALLFAR_Op64_Ep, &BX_CPU_C::CALL64_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Eq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::JMP_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op64_Ep, &BX_CPU_C::JMP64_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMPFAR_Op64_Ep, &BX_CPU_C::JMP64_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_PUSHF_Fq, NULL, &BX_CPU_C::PUSHF_Fq, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_POPF_Fq, NULL, &BX_CPU_C::POPF_Fq, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)

8
bochs/cpu/icache.cc
View File

@ -97,10 +97,10 @@ bxICacheEntry_c* BX_CPU_C::serveICacheMiss(bxICacheEntry_c *entry, Bit32u eipBia
{
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
ret = fetchDecode64(fetchPtr, i, remainingInPage);
ret = fetchDecode64(fetchPtr, BX_CPU_THIS_PTR fetchModeMask, i, remainingInPage);
else
#endif
ret = fetchDecode32(fetchPtr, i, remainingInPage);
ret = fetchDecode32(fetchPtr, BX_CPU_THIS_PTR fetchModeMask, i, remainingInPage);
if (ret < 0) {
// Fetching instruction on segment/page boundary
@ -249,10 +249,10 @@ void BX_CPU_C::boundaryFetch(const Bit8u *fetchPtr, unsigned remainingInPage, bx
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
ret = fetchDecode64(fetchBuffer, i, remainingInPage+fetchBufferLimit);
ret = fetchDecode64(fetchBuffer, BX_CPU_THIS_PTR fetchModeMask, i, remainingInPage+fetchBufferLimit);
else
#endif
ret = fetchDecode32(fetchBuffer, i, remainingInPage+fetchBufferLimit);
ret = fetchDecode32(fetchBuffer, BX_CPU_THIS_PTR fetchModeMask, i, remainingInPage+fetchBufferLimit);
if (ret < 0) {
BX_INFO(("boundaryFetch #GP(0): failed to complete instruction decoding"));

4
bochs/disasm/dis_groups.cc
View File

@ -33,14 +33,14 @@ void disassembler::Apw(const x86_insn *insn)
{
Bit16u imm16 = fetch_word();
Bit16u cs_selector = fetch_word();
dis_sprintf("%04x:%04x", (unsigned) cs_selector, (unsigned) imm16);
dis_sprintf("0x%04x:%04x", (unsigned) cs_selector, (unsigned) imm16);
}
void disassembler::Apd(const x86_insn *insn)
{
Bit32u imm32 = fetch_dword();
Bit16u cs_selector = fetch_word();
dis_sprintf("%04x:%08x", (unsigned) cs_selector, (unsigned) imm32);
dis_sprintf("0x%04x:%08x", (unsigned) cs_selector, (unsigned) imm32);
}
// 8-bit general purpose registers

6
bochs/disasm/opcodes.inc
View File

@ -116,10 +116,10 @@ Ia_blendps_Vps_Wps_Ib = { "blendps", "blendps", Vps, Wps, Ib, XX, IA_SSE4_1 },
Ia_blendvpd_Vpd_Wpd = { "blendvpd", "blendvpd", Vpd, Wpd, XX, XX, IA_SSE4_1 },
Ia_blendvps_Vps_Wps = { "blendvps", "blendvps", Vps, Wps, XX, XX, IA_SSE4_1 },
Ia_blsfill_By_Ey = { "blsfill", "blsfill", Gy, By, Ey, XX, IA_TBM },
Ia_blsi_By_Ey = { "blsi", "blsi", By, Gy, XX, XX, IA_BMI1 },
Ia_blsi_By_Ey = { "blsi", "blsi", By, Ey, XX, XX, IA_BMI1 },
Ia_blsic_By_Ey = { "blsic", "blsic", Gy, By, Ey, XX, IA_TBM },
Ia_blsmsk_By_Ey = { "blsmsk", "blsmsk", By, Gy, XX, XX, IA_BMI1 },
Ia_blsr_By_Ey = { "blsr", "blsr", By, Gy, XX, XX, IA_BMI1 },
Ia_blsmsk_By_Ey = { "blsmsk", "blsmsk", By, Ey, XX, XX, IA_BMI1 },
Ia_blsr_By_Ey = { "blsr", "blsr", By, Ey, XX, XX, IA_BMI1 },
Ia_boundl_Gd_Ma = { "bound", "boundl", Gd, Ma, XX, XX, 0 },
Ia_boundw_Gw_Ma = { "bound", "boundw", Gw, Ma, XX, XX, 0 },
Ia_bsfl_Gd_Ed = { "bsf", "bsfl", Gd, Ed, XX, XX, 0 },