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Bochs/bochs/cpu
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Stanislav Shwartsman ff79cbd596 Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm) 
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.

Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
2013-09-24 05:21:00 +00:00
..
cpudb
various fixes
2013-08-29 19:43:15 +00:00
fpu
fixed evex override mscsr controls
2013-09-19 21:38:25 +00:00
3dnow.cc
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access32.cc
first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel
2013-07-26 12:50:56 +00:00
access64.cc
fixed typo in last commit
2013-08-04 19:47:19 +00:00
access.cc
VMX: CMPXHG instructions should always write to the memory destination, even if the value unchanged - it affects VMEXIT conditions for the full apic virtualization
2013-08-04 19:37:04 +00:00
aes.cc
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apic.cc
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apic.h
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arith8.cc
CMPXHG should always write to memory dest - affects APIC virtualization VMEXIT conditions
2013-07-24 21:06:24 +00:00
arith16.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
arith32.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
arith64.cc
VMX: CMPXHG instructions should always write to the memory destination, even if the value unchanged - it affects VMEXIT conditions for the full apic virtualization
2013-08-04 19:37:04 +00:00
avx2.cc
infrastructure change for several AVX handlers to support any VL and only 128/256
2013-09-21 20:40:57 +00:00
avx512_mask16.cc
rename avx512_mask.cc
2013-09-08 20:15:52 +00:00
avx512_pfp.cc
infrastructure change for several AVX handlers to support any VL and only 128/256
2013-09-21 20:40:57 +00:00
avx_fma.cc
infrastructure change for several AVX handlers to support any VL and only 128/256
2013-09-21 20:40:57 +00:00
avx_pfp.cc
infrastructure change for several AVX handlers to support any VL and only 128/256
2013-09-21 20:40:57 +00:00
avx.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
bcd.cc
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bit16.cc
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bit32.cc
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bit64.cc
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bit.cc
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bmi32.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
bmi64.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
call_far.cc
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cpu.cc
update (c) for few files
2013-09-05 18:40:14 +00:00
cpu.h
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
cpuid.h
First step of AVX512 support implementation (simplest)
2013-09-08 19:19:16 +00:00
crc32.cc
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crregs.cc
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crregs.h
various fixes
2013-08-29 19:43:15 +00:00
ctrl_xfer16.cc
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ctrl_xfer32.cc
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ctrl_xfer64.cc
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ctrl_xfer_pro.cc
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data_xfer8.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
data_xfer16.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
data_xfer32.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
data_xfer64.cc
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debugstuff.cc
one more step in the way towards avx-512 which have more vector registers
2013-08-24 12:12:10 +00:00
descriptor.h
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event.cc
update (c) for few files
2013-09-05 18:40:14 +00:00
exception.cc
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fetchdecode64.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
fetchdecode_avx.h
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
fetchdecode_evex.h
added evex decode tables - next step to populate them :)
2013-09-15 20:48:39 +00:00
fetchdecode_sse.h
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
fetchdecode_x87.h
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fetchdecode_xop.h
added evex decode tables - next step to populate them :)
2013-09-15 20:48:39 +00:00
fetchdecode.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
fetchdecode.h
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
flag_ctrl_pro.cc
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flag_ctrl.cc
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fpu_emu.cc
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gather.cc
first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel
2013-07-26 12:50:56 +00:00
generic_cpuid.cc
merge AVX and SSE .bochsrc options to single SIMD option which will configure SSE and AVX together
2013-09-16 19:50:36 +00:00
generic_cpuid.h
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i387.h
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ia_opcodes.h
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
icache.cc
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icache.h
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init.cc
enable avx-512 in init.cc
2013-09-08 19:35:37 +00:00
instr.h
implement first EVEX instructions - VADDPS/PD/SS/SD
2013-09-19 18:31:30 +00:00
io.cc
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iret.cc
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jmp_far.cc
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lazy_flags.h
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load.cc
implement first EVEX instructions - VADDPS/PD/SS/SD
2013-09-19 18:31:30 +00:00
logical8.cc
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logical16.cc
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logical32.cc
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logical64.cc
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Makefile.in
fixed typo in makefile
2013-09-21 10:52:18 +00:00
mmx.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
msr.cc
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mult8.cc
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mult16.cc
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mult32.cc
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mult64.cc
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paging.cc
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proc_ctrl.cc
fixes and small optimizations for avx and xop decoding
2013-09-05 18:29:50 +00:00
protect_ctrl.cc
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rdrand.cc
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resolver.cc
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ret_far.cc
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segment_ctrl_pro.cc
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segment_ctrl.cc
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sha.cc
properly added sha.cc to the tree
2013-07-24 18:56:37 +00:00
shift8.cc
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shift16.cc
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shift32.cc
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shift64.cc
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simd_compare.h
name convention change - search and replace
2013-09-17 17:34:20 +00:00
simd_int.h
fixed evex override mscsr controls
2013-09-19 21:38:25 +00:00
simd_pfp.h
added masked operations to simd_pfp.h, optimize simd_int.h, rewrite dpps instr using new masked op from simd_pfp.h
2013-09-17 20:49:26 +00:00
smm.cc
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smm.h
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soft_int.cc
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sse_move.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
sse_pfp.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
sse_rcp.cc
…
sse_string.cc
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sse.cc
name convention change - search and replace
2013-09-17 17:34:20 +00:00
stack16.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
stack32.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
stack64.cc
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
2013-09-24 05:21:00 +00:00
stack.cc
properly added sha.cc to the tree
2013-07-24 18:56:37 +00:00
stack.h
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string.cc
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svm.cc
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svm.h
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tasking.cc
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tbm32.cc
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tbm64.cc
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todo
added masked operations to simd_pfp.h, optimize simd_int.h, rewrite dpps instr using new masked op from simd_pfp.h
2013-09-17 20:49:26 +00:00
vapic.cc
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vm8086.cc
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vmcs.cc
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vmexit.cc
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vmfunc.cc
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vmx.cc
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vmx.h
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xmm.h
infrastructure change for several AVX handlers to support any VL and only 128/256
2013-09-21 20:40:57 +00:00
xop.cc
name convention change - search and replace
2013-09-17 17:34:20 +00:00
xsave.cc
update (c) for few files
2013-09-05 18:37:10 +00:00