updates to internal disasm
This commit is contained in:
Stanislav Shwartsman
parent
147d788022
commit
e592f81209
@ -79,12 +79,11 @@
|
||||
# define BX_GENERAL_REGISTERS 8
|
||||
#endif
|
||||
|
||||
#define BX_TMP_REGISTER (BX_GENERAL_REGISTERS)
|
||||
|
||||
#define BX_16BIT_REG_IP (BX_GENERAL_REGISTERS+1)
|
||||
#define BX_32BIT_REG_EIP (BX_GENERAL_REGISTERS+1)
|
||||
#define BX_64BIT_REG_RIP (BX_GENERAL_REGISTERS+1)
|
||||
#define BX_16BIT_REG_IP (BX_GENERAL_REGISTERS)
|
||||
#define BX_32BIT_REG_EIP (BX_GENERAL_REGISTERS)
|
||||
#define BX_64BIT_REG_RIP (BX_GENERAL_REGISTERS)
|
||||
|
||||
#define BX_TMP_REGISTER (BX_GENERAL_REGISTERS+1)
|
||||
#define BX_NIL_REGISTER (BX_GENERAL_REGISTERS+2)
|
||||
|
||||
#if defined(NEED_CPU_REG_SHORTCUTS)
|
||||
@ -955,8 +954,8 @@ public: // for now...
|
||||
// rdi: destination index
|
||||
// esp: stack pointer
|
||||
// r8..r15 x86-64 extended registers
|
||||
// tmp: temp register
|
||||
// rip: instruction pointer
|
||||
// tmp: temp register
|
||||
// nil: null register
|
||||
bx_gen_reg_t gen_reg[BX_GENERAL_REGISTERS+3];
|
||||
|
||||
|
||||
@ -57,14 +57,14 @@ static const char *intel_general_16bit_regname[16] = {
|
||||
"r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
|
||||
};
|
||||
|
||||
static const char *intel_general_32bit_regname[16] = {
|
||||
static const char *intel_general_32bit_regname[17] = {
|
||||
"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
|
||||
"r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
|
||||
"r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", "eip"
|
||||
};
|
||||
|
||||
static const char *intel_general_64bit_regname[16] = {
|
||||
static const char *intel_general_64bit_regname[17] = {
|
||||
"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
|
||||
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
|
||||
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "rip"
|
||||
};
|
||||
|
||||
static const char *intel_general_8bit_regname_rex[16] = {
|
||||
@ -80,6 +80,12 @@ static const char *intel_segment_name[8] = {
|
||||
"es", "cs", "ss", "ds", "fs", "gs", "??", "??"
|
||||
};
|
||||
|
||||
#if BX_SUPPORT_EVEX
|
||||
static const char *rounding_mode[4] = {
|
||||
"round_nearest_even", "round_down", "round_up", "round_to_zero"
|
||||
};
|
||||
#endif
|
||||
|
||||
char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regname[])
|
||||
{
|
||||
if (i->sibBase() == BX_NIL_REGISTER)
|
||||
@ -145,23 +151,44 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i)
|
||||
return disbufptr;
|
||||
}
|
||||
|
||||
void disasm(char *disbufptr, const bxInstruction_c *i)
|
||||
char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address base)
|
||||
{
|
||||
if (i->getIaOpcode() == BX_INSERTED_OPCODE) {
|
||||
disbufptr = dis_sprintf(disbufptr, "(bochs inserted internal opcode)");
|
||||
return disbufptr;
|
||||
}
|
||||
|
||||
if (i->execute1 == BX_CPU_C::BxError) {
|
||||
dis_sprintf(disbufptr, "(invalid)");
|
||||
return;
|
||||
disbufptr = dis_sprintf(disbufptr, "(invalid)");
|
||||
return disbufptr;
|
||||
}
|
||||
|
||||
const char *opname = i->getIaOpcodeName() + 6; // skip the "BX_IA_"
|
||||
//bx_bool is_vex_xop = BX_FALSE;
|
||||
unsigned n;
|
||||
#if BX_SUPPORT_EVEX
|
||||
bx_bool is_vector = BX_FALSE;
|
||||
#endif
|
||||
|
||||
if (! strncmp(opname, "V128_", 4) || ! strncmp(opname, "V256_", 4) || ! strncmp(opname, "V512_", 4)) {
|
||||
opname += 4;
|
||||
// is_vex_xop = BX_TRUE;
|
||||
if (! strncmp(opname, "V128_", 5) || ! strncmp(opname, "V256_", 5) || ! strncmp(opname, "V512_", 5)) {
|
||||
opname += 5;
|
||||
#if BX_SUPPORT_EVEX
|
||||
is_vector = BX_TRUE;
|
||||
#endif
|
||||
}
|
||||
|
||||
// Step 1: print opcode name
|
||||
if (! strncmp(opname, "REP_", 4)) {
|
||||
opname += 4;
|
||||
}
|
||||
|
||||
// Step 1: print prefixes
|
||||
if (i->repUsedL()) {
|
||||
if (i->repUsedValue() == 2)
|
||||
disbufptr = dis_sprintf(disbufptr, "repne ");
|
||||
else
|
||||
disbufptr = dis_sprintf(disbufptr, "rep ");
|
||||
}
|
||||
|
||||
// Step 2: print opcode name
|
||||
unsigned opname_len = strlen(opname);
|
||||
for (n=0;n < opname_len; n++) {
|
||||
if (opname[n] == '_') break;
|
||||
@ -170,12 +197,13 @@ void disasm(char *disbufptr, const bxInstruction_c *i)
|
||||
|
||||
disbufptr = dis_putc(disbufptr, ' ');
|
||||
|
||||
// Step 2: print sources
|
||||
// Step 3: print sources
|
||||
Bit16u ia_opcode = i->getIaOpcode();
|
||||
unsigned srcs_used = 0;
|
||||
for (n = 0; n <= 3; n++) {
|
||||
unsigned src = (unsigned) BxOpcodesTable[ia_opcode].src[n];
|
||||
if (! src) continue;
|
||||
unsigned src_type = src >> 3;
|
||||
if (! src_type && src != BX_SRC_RM) continue;
|
||||
if (srcs_used++ > 0)
|
||||
disbufptr = dis_sprintf(disbufptr, ", ");
|
||||
|
||||
@ -184,8 +212,6 @@ void disasm(char *disbufptr, const bxInstruction_c *i)
|
||||
}
|
||||
else {
|
||||
unsigned srcreg = i->getSrcReg(n);
|
||||
unsigned src_type = src >> 3;
|
||||
|
||||
if (src_type < 0x10) {
|
||||
switch(src_type) {
|
||||
case BX_GPR8:
|
||||
@ -215,8 +241,15 @@ void disasm(char *disbufptr, const bxInstruction_c *i)
|
||||
break;
|
||||
case BX_VMM_REG:
|
||||
#if BX_SUPPORT_AVX
|
||||
if (i->getVL() > BX_NO_VL)
|
||||
if (i->getVL() > BX_NO_VL) {
|
||||
disbufptr = dis_sprintf(disbufptr, "%cmm%d", 'x' + i->getVL() - 1, srcreg);
|
||||
#if BX_SUPPORT_EVEX
|
||||
if (n == 0 && i->opmask()) {
|
||||
disbufptr = dis_sprintf(disbufptr, "{k%d}%s", i->opmask(),
|
||||
i->isZeroMasking() ? "{z}" : "");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else
|
||||
#endif
|
||||
disbufptr = dis_sprintf(disbufptr, "xmm%d", srcreg);
|
||||
@ -236,7 +269,8 @@ void disasm(char *disbufptr, const bxInstruction_c *i)
|
||||
disbufptr = dis_sprintf(disbufptr, "dr%d", srcreg);
|
||||
break;
|
||||
default:
|
||||
disbufptr = dis_sprintf(disbufptr, "(unknown source type %d)", src_type);
|
||||
if (src_type != BX_NO_REG)
|
||||
disbufptr = dis_sprintf(disbufptr, "(unknown source type %d)", src_type);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -261,10 +295,10 @@ void disasm(char *disbufptr, const bxInstruction_c *i)
|
||||
disbufptr = dis_sprintf(disbufptr, "0x%04x", i->Iw2());
|
||||
break;
|
||||
case BX_IMM_BrOff16:
|
||||
disbufptr = dis_sprintf(disbufptr, ".%+d", i->Iw());
|
||||
disbufptr = dis_sprintf(disbufptr, ".%+d (0x%08x)", i->Iw(), base + i->ilen() + (Bit16s) i->Iw());
|
||||
break;
|
||||
case BX_IMM_BrOff32:
|
||||
disbufptr = dis_sprintf(disbufptr, ".%+d", i->Id());
|
||||
disbufptr = dis_sprintf(disbufptr, ".%+d (0x" FMT_ADDRX ")", i->Id(), base + i->ilen() + (Bit32s) i->Id());
|
||||
break;
|
||||
case BX_RSIREF:
|
||||
disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
|
||||
@ -290,6 +324,22 @@ void disasm(char *disbufptr, const bxInstruction_c *i)
|
||||
disbufptr = dis_sprintf(disbufptr, "[%s]", intel_general_16bit_regname[BX_16BIT_REG_DI]);
|
||||
}
|
||||
break;
|
||||
case BX_USECL:
|
||||
disbufptr = dis_sprintf(disbufptr, "cl");
|
||||
break;
|
||||
case BX_USEDX:
|
||||
disbufptr = dis_sprintf(disbufptr, "dx");
|
||||
break;
|
||||
case BX_DIRECT_MEMREF32:
|
||||
disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
|
||||
if (! i->as32L())
|
||||
disbufptr = dis_sprintf(disbufptr, "0x%04x", i->Id());
|
||||
else
|
||||
disbufptr = dis_sprintf(disbufptr, "0x%08x", i->Id());
|
||||
break;
|
||||
case BX_DIRECT_MEMREF64:
|
||||
disbufptr = dis_sprintf(disbufptr, "%s:0x" FMT_ADDRX, intel_segment_name[i->seg()], i->Iq());
|
||||
break;
|
||||
default:
|
||||
disbufptr = dis_sprintf(disbufptr, "(unknown source type %d)", src_type);
|
||||
break;
|
||||
@ -297,4 +347,15 @@ void disasm(char *disbufptr, const bxInstruction_c *i)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_EVEX
|
||||
if (is_vector && i->getEvexb()) {
|
||||
if (! i->modC0())
|
||||
disbufptr = dis_sprintf(disbufptr, "{broadcast TBD}");
|
||||
else
|
||||
disbufptr = dis_sprintf(disbufptr, "{sae/%s}", rounding_mode[i->getRC()]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return disbufptr;
|
||||
}
|
||||
|
||||
@ -109,7 +109,11 @@ enum {
|
||||
BX_IMM_BrOff16 = 0x16,
|
||||
BX_IMM_BrOff32 = 0x17,
|
||||
BX_RSIREF = 0x18,
|
||||
BX_RDIREF = 0x19
|
||||
BX_RDIREF = 0x19,
|
||||
BX_USECL = 0x1A,
|
||||
BX_USEDX = 0x1B,
|
||||
BX_DIRECT_MEMREF32 = 0x1C,
|
||||
BX_DIRECT_MEMREF64 = 0x1D,
|
||||
};
|
||||
|
||||
#define BX_FORM_SRC(type, src) (((type) << 3) | (src))
|
||||
@ -133,8 +137,8 @@ const Bit8u OP_AXReg = BX_FORM_SRC(BX_GPR16, BX_SRC_EAX);
|
||||
const Bit8u OP_EAXReg = BX_FORM_SRC(BX_GPR32, BX_SRC_EAX);
|
||||
const Bit8u OP_RAXReg = BX_FORM_SRC(BX_GPR64, BX_SRC_EAX);
|
||||
|
||||
const Bit8u OP_CLReg = BX_SRC_NONE;
|
||||
const Bit8u OP_DXReg = BX_SRC_NONE;
|
||||
const Bit8u OP_CLReg = BX_FORM_SRC(BX_USECL, BX_SRC_NONE);
|
||||
const Bit8u OP_DXReg = BX_FORM_SRC(BX_USEDX, BX_SRC_NONE);
|
||||
|
||||
const Bit8u OP_Ib = BX_FORM_SRC(BX_IMMB, BX_SRC_NONE);
|
||||
const Bit8u OP_Iw = BX_FORM_SRC(BX_IMMW, BX_SRC_NONE);
|
||||
@ -154,6 +158,7 @@ const Bit8u OP_Mw = BX_SRC_RM;
|
||||
const Bit8u OP_Md = BX_SRC_RM;
|
||||
const Bit8u OP_Mq = BX_SRC_RM;
|
||||
const Bit8u OP_Mp = BX_SRC_RM;
|
||||
const Bit8u OP_Mt = BX_FORM_SRC(BX_FPU_REG, BX_SRC_RM);
|
||||
|
||||
const Bit8u OP_Mdq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
|
||||
@ -200,8 +205,8 @@ const Bit8u OP_Dq = BX_FORM_SRC(BX_DREG, BX_SRC_NNN);
|
||||
|
||||
const Bit8u OP_Sw = BX_FORM_SRC(BX_SEGREG, BX_SRC_NNN);
|
||||
|
||||
const Bit8u OP_Od = BX_SRC_NONE;
|
||||
const Bit8u OP_Oq = BX_SRC_NONE;
|
||||
const Bit8u OP_Od = BX_FORM_SRC(BX_DIRECT_MEMREF32, BX_SRC_NONE);
|
||||
const Bit8u OP_Oq = BX_FORM_SRC(BX_DIRECT_MEMREF64, BX_SRC_NONE);
|
||||
|
||||
const Bit8u OP_KGw = BX_FORM_SRC(BX_KMASK_REG, BX_SRC_NNN);
|
||||
const Bit8u OP_KEw = BX_FORM_SRC(BX_KMASK_REG, BX_SRC_RM);
|
||||
|
||||
@ -395,14 +395,14 @@ bx_define_opcode(BX_IA_LEA_GdM, &BX_CPU_C::LEA_GdM, &BX_CPU_C::BxError, 0, OP_Gd
|
||||
bx_define_opcode(BX_IA_LEA_GwM, &BX_CPU_C::LEA_GwM, &BX_CPU_C::BxError, 0, OP_Gw, OP_M, OP_NONE, OP_NONE, 0)
|
||||
|
||||
// IDT/GDT/LDTR/TR access - keep NNN for VMX
|
||||
bx_define_opcode(BX_IA_SIDT_Ms, &BX_CPU_C::SIDT_Ms, &BX_CPU_C::BxError, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_LIDT_Ms, &BX_CPU_C::LIDT_Ms, &BX_CPU_C::BxError, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_SGDT_Ms, &BX_CPU_C::SGDT_Ms, &BX_CPU_C::BxError, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_LGDT_Ms, &BX_CPU_C::LGDT_Ms, &BX_CPU_C::BxError, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_SLDT_Ew, &BX_CPU_C::SLDT_Ew, &BX_CPU_C::SLDT_Ew, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_LLDT_Ew, &BX_CPU_C::LLDT_Ew, &BX_CPU_C::LLDT_Ew, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_STR_Ew, &BX_CPU_C::STR_Ew, &BX_CPU_C::STR_Ew, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_LTR_Ew, &BX_CPU_C::LTR_Ew, &BX_CPU_C::LTR_Ew, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_SIDT_Ms, &BX_CPU_C::SIDT_Ms, &BX_CPU_C::BxError, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_LIDT_Ms, &BX_CPU_C::LIDT_Ms, &BX_CPU_C::BxError, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_SGDT_Ms, &BX_CPU_C::SGDT_Ms, &BX_CPU_C::BxError, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_LGDT_Ms, &BX_CPU_C::LGDT_Ms, &BX_CPU_C::BxError, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_SLDT_Ew, &BX_CPU_C::SLDT_Ew, &BX_CPU_C::SLDT_Ew, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_LLDT_Ew, &BX_CPU_C::LLDT_Ew, &BX_CPU_C::LLDT_Ew, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_STR_Ew, &BX_CPU_C::STR_Ew, &BX_CPU_C::STR_Ew, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_LTR_Ew, &BX_CPU_C::LTR_Ew, &BX_CPU_C::LTR_Ew, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0)
|
||||
// IDT/GDT/LDTR/TR access - keep NNN for VMX
|
||||
|
||||
bx_define_opcode(BX_IA_SMSW_Ew, &BX_CPU_C::SMSW_EwM, &BX_CPU_C::SMSW_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
@ -636,29 +636,29 @@ bx_define_opcode(BX_IA_MWAIT, &BX_CPU_C::BxError, &BX_CPU_C::MWAIT, BX_ISA_MONIT
|
||||
bx_define_opcode(BX_IA_FWAIT, NULL, &BX_CPU_C::FWAIT, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
#if BX_SUPPORT_FPU
|
||||
bx_define_opcode(BX_IA_FLD_STi, NULL, &BX_CPU_C::FLD_STi, BX_ISA_X87, OP_NONE, OP_STi, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FLD_SINGLE_REAL, &BX_CPU_C::FLD_SINGLE_REAL, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FLD_DOUBLE_REAL, &BX_CPU_C::FLD_DOUBLE_REAL, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FLD_EXTENDED_REAL, &BX_CPU_C::FLD_EXTENDED_REAL, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FILD_WORD_INTEGER, &BX_CPU_C::FILD_WORD_INTEGER, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FILD_DWORD_INTEGER, &BX_CPU_C::FILD_DWORD_INTEGER, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FILD_QWORD_INTEGER, &BX_CPU_C::FILD_QWORD_INTEGER, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FLD_SINGLE_REAL, &BX_CPU_C::FLD_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FLD_DOUBLE_REAL, &BX_CPU_C::FLD_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FLD_EXTENDED_REAL, &BX_CPU_C::FLD_EXTENDED_REAL, NULL, BX_ISA_X87, OP_Mt, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FILD_WORD_INTEGER, &BX_CPU_C::FILD_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FILD_DWORD_INTEGER, &BX_CPU_C::FILD_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FILD_QWORD_INTEGER, &BX_CPU_C::FILD_QWORD_INTEGER, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FBLD_PACKED_BCD, &BX_CPU_C::FBLD_PACKED_BCD, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FST_STi, NULL, &BX_CPU_C::FST_STi, BX_ISA_X87, OP_STi, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSTP_STi, NULL, &BX_CPU_C::FST_STi, BX_ISA_X87, OP_STi, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FST_SINGLE_REAL, &BX_CPU_C::FST_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FSTP_SINGLE_REAL, &BX_CPU_C::FST_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FST_DOUBLE_REAL, &BX_CPU_C::FST_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FSTP_DOUBLE_REAL, &BX_CPU_C::FST_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FSTP_EXTENDED_REAL, &BX_CPU_C::FSTP_EXTENDED_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FST_SINGLE_REAL, &BX_CPU_C::FST_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSTP_SINGLE_REAL, &BX_CPU_C::FST_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FST_DOUBLE_REAL, &BX_CPU_C::FST_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSTP_DOUBLE_REAL, &BX_CPU_C::FST_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSTP_EXTENDED_REAL, &BX_CPU_C::FSTP_EXTENDED_REAL, NULL, BX_ISA_X87, OP_Mt, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FIST_WORD_INTEGER, &BX_CPU_C::FIST_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FISTP_WORD_INTEGER, &BX_CPU_C::FIST_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FIST_DWORD_INTEGER, &BX_CPU_C::FIST_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FISTP_DWORD_INTEGER, &BX_CPU_C::FIST_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FISTP_QWORD_INTEGER, &BX_CPU_C::FISTP_QWORD_INTEGER, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FBSTP_PACKED_BCD, &BX_CPU_C::FBSTP_PACKED_BCD, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FISTTP16, &BX_CPU_C::FISTTP16, NULL, BX_ISA_SSE3, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FISTTP32, &BX_CPU_C::FISTTP32, NULL, BX_ISA_SSE3, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FISTTP64, &BX_CPU_C::FISTTP64, NULL, BX_ISA_SSE3, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FISTTP16, &BX_CPU_C::FISTTP16, NULL, BX_ISA_SSE3, OP_Ew, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FISTTP32, &BX_CPU_C::FISTTP32, NULL, BX_ISA_SSE3, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FISTTP64, &BX_CPU_C::FISTTP64, NULL, BX_ISA_SSE3, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FNINIT, NULL, &BX_CPU_C::FNINIT, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FNCLEX, NULL, &BX_CPU_C::FNCLEX, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FRSTOR, &BX_CPU_C::FRSTOR, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
@ -666,8 +666,8 @@ bx_define_opcode(BX_IA_FNSAVE, &BX_CPU_C::FNSAVE, NULL, BX_ISA_X87, OP_M, OP_NON
|
||||
bx_define_opcode(BX_IA_FLDENV, &BX_CPU_C::FLDENV, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FNSTENV, &BX_CPU_C::FNSTENV, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FLDCW, &BX_CPU_C::FLDCW, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FNSTCW, &BX_CPU_C::FNSTCW, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FNSTSW, &BX_CPU_C::FNSTSW, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FNSTCW, &BX_CPU_C::FNSTCW, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FNSTSW, &BX_CPU_C::FNSTSW, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FNSTSW_AX, NULL, &BX_CPU_C::FNSTSW_AX, BX_ISA_X87, OP_AXReg, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FLD1, NULL, &BX_CPU_C::FLD1, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FLDL2T, NULL, &BX_CPU_C::FLDL2T, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
@ -678,24 +678,24 @@ bx_define_opcode(BX_IA_FLDLN2, NULL, &BX_CPU_C::FLDLN2, BX_ISA_X87, OP_NONE, OP_
|
||||
bx_define_opcode(BX_IA_FLDZ, NULL, &BX_CPU_C::FLDZ, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FADD_ST0_STj, NULL, &BX_CPU_C::FADD_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FADD_STi_ST0, NULL, &BX_CPU_C::FADD_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FADD_SINGLE_REAL, &BX_CPU_C::FADD_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FADD_DOUBLE_REAL, &BX_CPU_C::FADD_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FADD_SINGLE_REAL, &BX_CPU_C::FADD_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FADD_DOUBLE_REAL, &BX_CPU_C::FADD_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FIADD_WORD_INTEGER, &BX_CPU_C::FIADD_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FIADD_DWORD_INTEGER, &BX_CPU_C::FIADD_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FMUL_ST0_STj, NULL, &BX_CPU_C::FMUL_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FMUL_STi_ST0, NULL, &BX_CPU_C::FMUL_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FMUL_SINGLE_REAL, &BX_CPU_C::FMUL_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FMUL_DOUBLE_REAL, &BX_CPU_C::FMUL_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FMUL_SINGLE_REAL, &BX_CPU_C::FMUL_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FMUL_DOUBLE_REAL, &BX_CPU_C::FMUL_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FIMUL_WORD_INTEGER , &BX_CPU_C::FIMUL_WORD_INTEGER , NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FIMUL_DWORD_INTEGER, &BX_CPU_C::FIMUL_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSUB_ST0_STj, NULL, &BX_CPU_C::FSUB_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSUBR_ST0_STj, NULL, &BX_CPU_C::FSUBR_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSUB_STi_ST0, NULL, &BX_CPU_C::FSUB_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSUBR_STi_ST0, NULL, &BX_CPU_C::FSUBR_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSUB_SINGLE_REAL, &BX_CPU_C::FSUB_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FSUBR_SINGLE_REAL, &BX_CPU_C::FSUBR_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FSUB_DOUBLE_REAL, &BX_CPU_C::FSUB_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FSUBR_DOUBLE_REAL, &BX_CPU_C::FSUBR_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FSUB_SINGLE_REAL, &BX_CPU_C::FSUB_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSUBR_SINGLE_REAL, &BX_CPU_C::FSUBR_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSUB_DOUBLE_REAL, &BX_CPU_C::FSUB_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FSUBR_DOUBLE_REAL, &BX_CPU_C::FSUBR_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FISUB_WORD_INTEGER, &BX_CPU_C::FISUB_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FISUBR_WORD_INTEGER, &BX_CPU_C::FISUBR_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FISUB_DWORD_INTEGER, &BX_CPU_C::FISUB_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
@ -704,10 +704,10 @@ bx_define_opcode(BX_IA_FDIV_ST0_STj, NULL, &BX_CPU_C::FDIV_ST0_STj, BX_ISA_X87,
|
||||
bx_define_opcode(BX_IA_FDIVR_ST0_STj, NULL, &BX_CPU_C::FDIVR_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FDIV_STi_ST0, NULL, &BX_CPU_C::FDIV_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FDIVR_STi_ST0, NULL, &BX_CPU_C::FDIVR_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FDIV_SINGLE_REAL, &BX_CPU_C::FDIV_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FDIVR_SINGLE_REAL, &BX_CPU_C::FDIVR_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FDIV_DOUBLE_REAL, &BX_CPU_C::FDIV_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FDIVR_DOUBLE_REAL, &BX_CPU_C::FDIVR_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FDIV_SINGLE_REAL, &BX_CPU_C::FDIV_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FDIVR_SINGLE_REAL, &BX_CPU_C::FDIVR_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FDIV_DOUBLE_REAL, &BX_CPU_C::FDIV_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FDIVR_DOUBLE_REAL, &BX_CPU_C::FDIVR_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FIDIV_WORD_INTEGER, &BX_CPU_C::FIDIV_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FIDIVR_WORD_INTEGER, &BX_CPU_C::FIDIVR_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FIDIV_DWORD_INTEGER, &BX_CPU_C::FIDIV_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
@ -720,10 +720,10 @@ bx_define_opcode(BX_IA_FCOMI_ST0_STj, NULL, &BX_CPU_C::FCOMI_ST0_STj, BX_ISA_P6,
|
||||
bx_define_opcode(BX_IA_FCOMIP_ST0_STj, NULL, &BX_CPU_C::FCOMI_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FUCOMI_ST0_STj, NULL, &BX_CPU_C::FUCOMI_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FUCOMIP_ST0_STj, NULL, &BX_CPU_C::FUCOMI_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FCOM_SINGLE_REAL, &BX_CPU_C::FCOM_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FCOMP_SINGLE_REAL, &BX_CPU_C::FCOM_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FCOM_DOUBLE_REAL, &BX_CPU_C::FCOM_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FCOMP_DOUBLE_REAL, &BX_CPU_C::FCOM_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_FCOM_SINGLE_REAL, &BX_CPU_C::FCOM_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FCOMP_SINGLE_REAL, &BX_CPU_C::FCOM_SINGLE_REAL, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FCOM_DOUBLE_REAL, &BX_CPU_C::FCOM_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FCOMP_DOUBLE_REAL, &BX_CPU_C::FCOM_DOUBLE_REAL, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FICOM_WORD_INTEGER, &BX_CPU_C::FICOM_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FICOMP_WORD_INTEGER, &BX_CPU_C::FICOM_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_FICOM_DWORD_INTEGER, &BX_CPU_C::FICOM_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
@ -1512,10 +1512,10 @@ bx_define_opcode(BX_IA_PUSH_Op64_GS, NULL, &BX_CPU_C::PUSH64_Sw, 0, OP_NONE, OP_
|
||||
bx_define_opcode(BX_IA_POP_Op64_GS, NULL, &BX_CPU_C::POP64_Sw, 0, OP_Sw, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
|
||||
// IDT/GDT/LDTR/TR access - keep NNN for VMX
|
||||
bx_define_opcode(BX_IA_SGDT_Op64_Ms, &BX_CPU_C::SGDT64_Ms, &BX_CPU_C::BxError, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_SIDT_Op64_Ms, &BX_CPU_C::SIDT64_Ms, &BX_CPU_C::BxError, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_LGDT_Op64_Ms, &BX_CPU_C::LGDT64_Ms, &BX_CPU_C::BxError, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_LIDT_Op64_Ms, &BX_CPU_C::LIDT64_Ms, &BX_CPU_C::BxError, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_SGDT_Op64_Ms, &BX_CPU_C::SGDT64_Ms, &BX_CPU_C::BxError, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_SIDT_Op64_Ms, &BX_CPU_C::SIDT64_Ms, &BX_CPU_C::BxError, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_LGDT_Op64_Ms, &BX_CPU_C::LGDT64_Ms, &BX_CPU_C::BxError, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_LIDT_Op64_Ms, &BX_CPU_C::LIDT64_Ms, &BX_CPU_C::BxError, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0)
|
||||
// IDT/GDT/LDTR/TR access - keep NNN for VMX
|
||||
|
||||
bx_define_opcode(BX_IA_MOV_RRXIq, NULL, &BX_CPU_C::MOV_RRXIq, 0, OP_Eq, OP_Iq, OP_NONE, OP_NONE, 0)
|
||||
|
||||
@ -121,7 +121,7 @@ public:
|
||||
// 3...0 ilen (0..15)
|
||||
Bit8u ilen;
|
||||
|
||||
// 7...6 repUsed (0=none, 2=0xF2, 3=0xF3)
|
||||
// 7...6 lockUsed, repUsed (0=none, 1=0xF0, 2=0xF2, 3=0xF3)
|
||||
// 5...5 extend8bit
|
||||
// 4...4 mod==c0 (modrm)
|
||||
// 3...3 os64
|
||||
|
||||
Loading…
Reference in New Issue
Block a user