added more svm intercepts
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0de2516d05
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c32eaa5d05
@ -635,6 +635,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR2Rq(bxInstruction_c *i)
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exception(BX_GP_EXCEPTION, 0);
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}
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if(SVM_CR_WRITE_INTERCEPTED(2)) Svm_Vmexit(SVM_VMEXIT_CR2_WRITE);
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}
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#endif
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BX_CPU_THIS_PTR cr2 = BX_READ_64BIT_REG(i->rm());
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BX_NEXT_INSTR(i);
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@ -733,6 +739,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR2(bxInstruction_c *i)
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exception(BX_GP_EXCEPTION, 0);
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}
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if(SVM_CR_READ_INTERCEPTED(2)) Svm_Vmexit(SVM_VMEXIT_CR2_READ);
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}
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#endif
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BX_WRITE_64BIT_REG(i->rm(), BX_CPU_THIS_PTR cr2);
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BX_NEXT_INSTR(i);
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@ -750,6 +762,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR3(bxInstruction_c *i)
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exception(BX_GP_EXCEPTION, 0);
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}
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if(SVM_CR_READ_INTERCEPTED(3)) Svm_Vmexit(SVM_VMEXIT_CR3_READ);
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}
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#endif
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#if BX_SUPPORT_VMX
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if (BX_CPU_THIS_PTR in_vmx_guest)
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VMexit_CR3_Read(i);
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@ -1180,6 +1198,12 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR4(bx_address val)
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{
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if (! check_CR4(val)) return 0;
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if(SVM_CR_WRITE_INTERCEPTED(4)) Svm_Vmexit(SVM_VMEXIT_CR4_WRITE);
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}
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#endif
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#if BX_CPU_LEVEL >= 6
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// Modification of PGE,PAE,PSE,PCIDE,SMEP flushes TLB cache according to docs.
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if ((val & BX_CR4_FLUSH_TLB_MASK) != (BX_CPU_THIS_PTR cr4.val32 & BX_CR4_FLUSH_TLB_MASK)) {
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@ -1229,6 +1253,12 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR3(bx_address val)
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}
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#endif
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if(SVM_CR_WRITE_INTERCEPTED(3)) Svm_Vmexit(SVM_VMEXIT_CR3_WRITE);
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}
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#endif
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BX_CPU_THIS_PTR cr3 = val;
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// flush TLB even if value does not change
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@ -1344,6 +1374,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CLTS(bxInstruction_c *i)
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}
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#endif
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if(SVM_CR_WRITE_INTERCEPTED(0)) Svm_Vmexit(SVM_VMEXIT_CR0_WRITE);
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}
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#endif
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BX_CPU_THIS_PTR cr0.set_TS(0);
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#if BX_CPU_LEVEL >= 6
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@ -225,6 +225,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WBINVD(bxInstruction_c *i)
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VMexit_WBINVD(i);
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#endif
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(1, SVM_INTERCEPT1_WBINVD)) Svm_Vmexit(SVM_VMEXIT_WBINVD);
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}
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#endif
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invalidate_prefetch_q();
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BX_DEBUG(("WBINVD: Flush internal caches !"));
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@ -613,6 +613,9 @@ void BX_CPU_C::SvmInterceptException(unsigned type, unsigned vector, Bit16u errc
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#define SVM_VMEXIT_IO_INSTR_LEN8 (1 << 4)
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#define SVM_VMEXIT_IO_INSTR_LEN16 (1 << 5)
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#define SVM_VMEXIT_IO_INSTR_LEN32 (1 << 6)
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#define SVM_VMEXIT_IO_INSTR_ASIZE16 (1 << 7)
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#define SVM_VMEXIT_IO_INSTR_ASIZE32 (1 << 8)
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#define SVM_VMEXIT_IO_INSTR_ASIZE64 (1 << 9)
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void BX_CPU_C::SvmInterceptIO(bxInstruction_c *i, unsigned port, unsigned len)
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{
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@ -329,6 +329,11 @@ typedef struct bx_VMCB_CACHE
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#define SVM_INTERCEPT1_SKINIT (1 << 6)
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#define SVM_INTERCEPT1_RDTSCP (1 << 7)
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#define SVM_INTERCEPT1_ICEBP (1 << 8)
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#define SVM_INTERCEPT1_WBINVD (1 << 9)
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#define SVM_INTERCEPT1_MONITOR (1 << 10)
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#define SVM_INTERCEPT1_MWAIT (1 << 11)
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#define SVM_INTERCEPT1_MWAIT_ARMED (1 << 12)
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#define SVM_INTERCEPT1_XSETBV (1 << 13)
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#define SVM_INTERCEPT(vector, intercept_bit) \
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(BX_CPU_THIS_PTR vmcb.ctrls.intercept_vector[vector] & (intercept_bit))
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@ -407,6 +407,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XSETBV(bxInstruction_c *i)
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}
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#endif
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#if BX_SUPPORT_SVM
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if (BX_CPU_THIS_PTR in_svm_guest) {
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if (SVM_INTERCEPT(1, SVM_INTERCEPT1_XSETBV)) Svm_Vmexit(SVM_VMEXIT_XSETBV);
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}
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#endif
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// CPL is always 3 in vm8086 mode
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if (/* v8086_mode() || */ CPL != 0) {
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BX_ERROR(("XSETBV: The current priveledge level is not 0"));
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