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2893 Commits

Author SHA1 Message Date
Stanislav Shwartsman
a604818ecf fixed another valgrind issue 2012-06-05 11:40:59 +00:00
Stanislav Shwartsman
efcca3e9d4 fixup VCVTPH2PS instruction implementation to match published Intel SDM 2012-06-05 11:36:50 +00:00
Stanislav Shwartsman
37e193d49c clean one more valgrind issue 2012-06-04 19:21:23 +00:00
Stanislav Shwartsman
5192d09655 fixed some more valgrind issues 2012-06-04 18:46:07 +00:00
Stanislav Shwartsman
7bae496840 fixed valgrind issues in apic initialization and generic cpuid reported in SF bug report 2012-06-04 14:27:34 +00:00
Stanislav Shwartsman
bd6330d480 small optimization for debugger 2012-06-03 18:46:20 +00:00
Stanislav Shwartsman
2ee3386c37 cpu bugfixes 2012-05-31 14:25:49 +00:00
Stanislav Shwartsman
f528290652 fixed bug EPT Access Dirty support 2012-05-27 19:17:13 +00:00
Stanislav Shwartsman
8e7f582bc3 correct init.cc fix - copy/paste issue 2012-05-20 19:02:29 +00:00
Stanislav Shwartsman
3f32517201 small fix for save/restore 2012-05-20 18:58:57 +00:00
Stanislav Shwartsman
f9540f1c24 - Improved CPU status restore after restoring from Bochs saved image 
- Changed many BX_ERROR messages about VMX VMEXIT takesn to BX_DEBUG
 2012-05-19 20:36:40 +00:00
Stanislav Shwartsman
2644ef5f63 another had_vex/had_xop fix 2012-05-19 19:46:10 +00:00
Stanislav Shwartsman
59eb1318d5 small fix 2012-05-19 19:38:57 +00:00
Stanislav Shwartsman
ffc5e4bf2d optimize x2apic reg write 2012-05-12 19:07:18 +00:00
Stanislav Shwartsman
08d4655886 X2APIC: incorrect write to self IPI X2APIC register (with reserved bits set) should not trigger the self IPI 2012-05-12 12:49:05 +00:00
Stanislav Shwartsman
03162d86f5 LAPIC: fixed timer interrupts after reloading of LAPIC Timer Divide Configuration register 2012-05-12 11:52:29 +00:00
Stanislav Shwartsman
9ea0987396 fixed send_ipi case in x2apic 2012-05-12 08:07:30 +00:00
Stanislav Shwartsman
6180a0a733 remove unused leafs from generic_cpuid 2012-05-11 06:51:04 +00:00
Stanislav Shwartsman
b5c5082ff2 Completely remove b1() field from bxInstruction structure and resuse it for AVX instructions flags. 
the iaOpcode field has no masking anymore.

fixed bug during the code reorganization:
                        
+ XOP: Fixed instructions with operands order depending on VEX.W (fixed VEX.W read from instruction object)
 2012-05-11 06:35:16 +00:00
Volker Ruppert
53e1a5d204 - fixed typo (file names are case sensitive on Linux and others) 2012-05-08 18:33:26 +00:00
Stanislav Shwartsman
f01e5f3e11 removed b1() from shift methods in CPU - lead to removal of b1() field from bxInstruction_c 2012-05-08 16:42:15 +00:00
Stanislav Shwartsman
708fc666c8 Added Corei7 ivyBridge configuration to CPUDB 2012-05-07 12:31:22 +00:00
Stanislav Shwartsman
9d802e2762 very small cleanup 2012-05-05 18:40:37 +00:00
Stanislav Shwartsman
2188322ab3 fixed CR8 SVM intercepts 2012-05-03 16:12:58 +00:00
Stanislav Shwartsman
39c14ef0d1 Implemented EPT A/D extensions support. 
Bochs is fully aligned with the latest published revision of
Intel Architecture Manual (revision 043) now.
 2012-05-02 18:11:39 +00:00
Stanislav Shwartsman
e12494bf7b fixed segfault when setting ESP/EIP in GUI debugger 2012-04-16 19:18:23 +00:00
Stanislav Shwartsman
c7c431f88e bx_instr_mem_data_access became completely obsolete with new stack optimization merged into SVN. 
It already had limited usability before. With stack direct access optimization the callback won't be called for stack accesses as well.
See note by Brian Slechta:

=== Cut Hete ===
While using Bochs as a reference model for simulations, the simulator needs
information about what loads/stores are taking place with each instruction.
Presumably,  that  is  what  the BX_INSTR_MEM_DATA() instrumentation macros
cover (which is the place where our simulator hooks up).

The RETnear_xxx() functions call access_linear() directly, rather than call
read_virtual_xxx()  functions. This is a problem for code making use of the
BX_INSTR_MEM_DATA()   hook  because  it  does  not  get  called  for  these
instructions.  Should  this  be  changed along with some other instructions
that exhibit this?
=== Cut Hete ===

For Bryan's usage bx_instr_lin_access and bx_instr_phy_read/bx_instr_phy_write callbacks should be used.
 2012-04-11 19:01:25 +00:00
Stanislav Shwartsman
59e13d5299 fixed compilation error with 386/486 and internal dbger enabled 2012-04-11 18:11:14 +00:00
Stanislav Shwartsman
a68ad9a7f6 small code optimization 2012-04-06 09:41:58 +00:00
Stanislav Shwartsman
a6f0ca70ff more robust SVM fix 2012-04-04 19:55:36 +00:00
Stanislav Shwartsman
72a00ce9dd improved debug prints in MOV to/from CR 
SVM bugfix
remove redundant TLB flush call from SVM and VMX code
 2012-04-04 19:31:02 +00:00
Stanislav Shwartsman
279c61dc67 updated + fixed instrumentation example for instr histogram, code cleanup in the cpu 2012-03-28 21:11:19 +00:00
Stanislav Shwartsman
90fc12d9e4 switching between compatibility and long64 mode also affect SS.BASE which is always zero in long64 mode 2012-03-27 15:21:40 +00:00
Stanislav Shwartsman
e7a4a1bec8 surprisingly, opensuse 12.1 requre alignment check support in hardware so I can't disable it by default for all configurations. 
but in case you want a few %% of extra emulation performance - it is still possible to disable it with configure option.
most guests I saw do not use it !
 2012-03-26 19:33:38 +00:00
Stanislav Shwartsman
8b78f6ca2c fixed prev commit 2012-03-26 19:24:20 +00:00
Stanislav Shwartsman
97a6d0ad46 missed ; 2012-03-26 19:08:28 +00:00
Stanislav Shwartsman
547678e8bd fixed compilation error in 386 config. also fixed bugs in tasking code found by new assertion added in stack.cc new code 2012-03-26 19:05:58 +00:00
Stanislav Shwartsman
bfca96f8ce added TLB contents to param tree for debugger purposes. Nopw the TLB could be browsed through param-tree in debugger and GUI debugger as well 2012-03-25 20:56:18 +00:00
Stanislav Shwartsman
d4688e8b95 - Do not compile support for alignment check (#AC exception) by default 
for CPU emulation performance reasons, the alignment check compilation
    still can be enabled using configure option --enable-alignment-check.

There is no software in the world which enable #AC exception checking, this
x86 feature is completely legacy but its emulation support costs up to 3-5%
emulation speed.

The checking for #AC exception enable still will be done, if

 CPL == 3, EFLAGS.AC = 1 and CR0.AM = 1

but the alignment check is not compiled in, the Bochs will PANIC with corresponding message.
You can press 'always continue' and ignore the PANIC, the simulation will continue as if alignment checking is not enabled.
 2012-03-25 19:07:17 +00:00
Stanislav Shwartsman
3ca29cbdf3 stack direct access optimization - 5% emu speedup to all 32-bit guests, for 64-bit guests speedup is less because they have less stack accesses 2012-03-25 11:54:32 +00:00
Stanislav Shwartsman
b5a33e82ac fixed a lot of code duplication in debugging/instrumentation of mem access 2012-03-20 18:26:04 +00:00
Stanislav Shwartsman
e1506e3e29 some cleanup in CPU code + patch SVM SS.DPL instead of failing VMRUN 2012-03-19 19:24:15 +00:00
Stanislav Shwartsman
a8565cdfc3 added missed line in MSR fix 2012-03-17 12:07:27 +00:00
Stanislav Shwartsman
bd4aa017fe Lazy flags improvement patch by Darek Mihocka - measured 5% speedup everywhere accross the board 
The problem with Parity is it is generally referenced very rarely so the current lazy flags code is not efficient to updated Parify flag only (because it updates low 8 bits of .result value the existing Zero Flag has to be shadowed in .auxbits.
So I flipped it around, to make Parity be shadowed in auxbits.  .result now is only needed to derive Zero Flag, and both Sign and Parify are derived from .result + .auxbits (as Zero Flag is now).  For the 90% of the conditional jumps that are JZ or JNZ, this is a speedup.
Parity is now derived from 8 bits in .result and 8 bits in .auxbits, and Sign is derived from one flag in .result and 1 bit in .auxbits by XOR-ing them all together.  It makes the code sequences for SAHF and POPF simpler too.
 2012-03-17 08:51:52 +00:00
Stanislav Shwartsman
5a33b1be84 mvoed MWAIT_IS_NOP option from CPUID to CPU - it has meaning even if CPUID tree is not used because CPU is configured with CPUDB pre-defined configuration 2012-03-15 19:46:57 +00:00
Stanislav Shwartsman
9d5d33632c VMX: Fixed reading of VMX MSR-HI (0xC0000000 <= index <= 0xC0001FFF) bitmaps / Fixed memory overflow 2012-03-14 19:42:06 +00:00
Stanislav Shwartsman
a9d03340d6 correctly handle EFER.LMA and EFER.LME with unrestricted guests 2012-03-14 19:17:27 +00:00
Stanislav Shwartsman
a668ff9908 small code optimization 2012-03-13 19:41:10 +00:00
Stanislav Shwartsman
25ffaeeea8 fixed VMX issue + small code reorg 2012-03-13 15:18:21 +00:00
Stanislav Shwartsman
9c27d279b9 removed incorrect BX_INFO msg 2012-03-07 20:07:57 +00:00
Stanislav Shwartsman
562c8c91d1 fixed FMA4 instructions sources 2012-03-06 15:18:35 +00:00
Stanislav Shwartsman
bde2f4d829 correctly handle #UD because of XOP.VVV 2012-03-05 19:48:55 +00:00
Stanislav Shwartsman
95e4191cd1 any vex instruction must use VEX.VVV or #UD 2012-03-04 17:56:22 +00:00
Stanislav Shwartsman
c52d97cb7f fixed comments in paging.cc 2012-02-28 22:39:33 +00:00
Stanislav Shwartsman
1f14c171ed rename some SSE handlers 2012-02-28 18:53:58 +00:00
Stanislav Shwartsman
d4541f1a88 removed dedicated handler for MOVNTI - can be replaced with existing handlers 2012-02-27 15:50:43 +00:00
Stanislav Shwartsman
959ab435cf fixed compilation err with SVM 2012-02-24 21:31:31 +00:00
Stanislav Shwartsman
86c7033a63 name cpu log functions in lower case 2012-02-23 19:31:02 +00:00
Stanislav Shwartsman
1599031869 changed BX_INFO back to BX_DEBUG 2012-02-19 20:16:10 +00:00
Stanislav Shwartsman
f48317affc SVM: Added EXITINFO2 write on VMEXIT (missed in prev commit) 
Added phenom_8650_toliman <AMD Phenom X3 8650 (Toliman)> comment into .bochsrc example with all other supported CPU configs.
Added missed SVM definitions into Toliman CPUDB module
 2012-02-19 20:15:23 +00:00
Stanislav Shwartsman
92376fb693 svm updates 2012-02-19 12:16:58 +00:00
Stanislav Shwartsman
c70a42c5d7 merged patch ftom SF bug 3459998 Bochs cannot be compiled outside the source tree 2012-02-19 12:16:14 +00:00
Stanislav Shwartsman
c2670b40d5 small cleanup in paging code 2012-02-15 19:49:35 +00:00
Stanislav Shwartsman
2f7e5ab3a3 fixed bugs in toliman configuration 2012-02-14 22:01:50 +00:00
Stanislav Shwartsman
5c02e7cebd do not need to load PAE PDPTRs if going to nested paging mode 2012-02-14 12:36:39 +00:00
Stanislav Shwartsman
bb7a648d91 Major commit ! 
------------

Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest !
A lot of code duplication was added for now - major cleanup will follow later.

! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled.

Some CPUID modules rework done to enable Toliman configuration.

Ckean up 'executable' attribute from all CPU source files.
 2012-02-13 23:29:01 +00:00
Stanislav Shwartsman
deaf58b130 read from CPUDB svm extensions 2012-02-13 21:55:27 +00:00
Stanislav Shwartsman
813fe4e6b9 reduce code duplication - continue preparing for nested paging implementation 2012-02-13 20:06:04 +00:00
Stanislav Shwartsman
4d0a5c1b07 - VMX: EPT misconfiguration should always take priority above EPT permissions violation (translate_guest_physical corner case bug) 
- VMX: EPT reserved bits set should cause EPT misconfiguration and not EPT violation
- VMX: EPT walk for guest CR3 address should be considered as 'page walk'
 2012-02-12 21:30:22 +00:00
Stanislav Shwartsman
0b5f798af1 re-commit changes from SVN rev11026 which were accidentially undo'ed by last Volker's commit 2012-02-12 19:13:57 +00:00
Volker Ruppert
de94b08a1a - class bx_list_c now contains a chained list of parameters. Removed the now 
obsolete maxsize parameter from all lists.
 2012-02-12 18:43:20 +00:00
Stanislav Shwartsman
855d2adece cleanups in paging code 2012-02-12 16:09:35 +00:00
Stanislav Shwartsman
fa182e96b5 for future nested paging: under NP PDPTR CACHE will contain NP PDPTR entries 2012-02-10 20:39:46 +00:00
Stanislav Shwartsman
b497077b70 intel disclosed more cpuid bits 2012-02-08 19:54:22 +00:00
Stanislav Shwartsman
9bebe91826 eliminate duplicated cpu methods by adding extra param to opcodes with no modrm 2012-02-03 10:24:59 +00:00
Stanislav Shwartsman
14ec87768e expand FCMOV function to 8 different functions - each one is much simpler to implement and understand 2012-02-01 12:07:53 +00:00
Stanislav Shwartsman
2e44613032 dos2unix for avx_pfp.cc 2012-01-30 15:29:22 +00:00
Stanislav Shwartsman
457c56c822 fixup for EPT paging 2012-01-22 18:39:15 +00:00
Stanislav Shwartsman
fc6712e3a3 undo part of prev paging commit 2012-01-19 20:01:32 +00:00
Stanislav Shwartsman
12afed23a1 small fix and cleanups in paging code 2012-01-19 06:38:22 +00:00
Stanislav Shwartsman
9461797886 added extra param to debugger phy access callback + cleanup in vmexit functions 2012-01-17 21:50:15 +00:00
Stanislav Shwartsman
f4b49633d4 paging code rework (cont) 2012-01-17 18:20:55 +00:00
Stanislav Shwartsman
0d64a6cb92 fixed paging bug in previous commit 2012-01-16 15:26:25 +00:00
Stanislav Shwartsman
7d641450ec remove param from check_entry_PAE function - it is always the same for all calls 2012-01-15 20:25:39 +00:00
Stanislav Shwartsman
c7cb99787e rework in paging code before nested paging implementation for SVM - step 2 
optimize TLB flush code
 2012-01-15 19:38:00 +00:00
Stanislav Shwartsman
4db23355cd rework in paging code before nested paging implementation for SVM - step 1 2012-01-15 17:54:13 +00:00
Stanislav Shwartsman
f5d55f5eb6 - Implemented Task Switch intercept in SVM, cleanup in task switch handling code 
- Changed (c) year in several cpu files
- Cleanup and indent fixes in VMX code
 2012-01-11 20:21:29 +00:00
Stanislav Shwartsman
cb366e00c5 fixed code duplication in exceptions 2012-01-11 06:27:35 +00:00
Stanislav Shwartsman
ba7887f31c fixed code duplication with v86 interrupt redirection 2012-01-10 08:13:34 +00:00
Stanislav Shwartsman
8d698c7087 fixed compilation err ith cpu-level=5 and cleanups 2012-01-09 20:52:15 +00:00
Stanislav Shwartsman
87b1c31495 fixed SVM VmEXIT on #PF error code 2012-01-09 20:24:23 +00:00
Stanislav Shwartsman
f64c38dfaf fix in SVM event injection 2012-01-09 20:15:15 +00:00
Stanislav Shwartsman
2900956327 Split back some frequently used arithmetic and logic opcodes (which were done as Load+Op before). 2012-01-09 13:09:59 +00:00
Stanislav Shwartsman
35bfe11c3d SVM: forgot to save RFLAGS in guest state 2012-01-08 19:46:38 +00:00
Stanislav Shwartsman
a531f8081c fixed compilation with cpu-level=5 2012-01-08 16:58:14 +00:00
Stanislav Shwartsman
76ee7b499b svm updates 2012-01-08 14:09:51 +00:00
Stanislav Shwartsman
9261b2fa14 removed param_names.h include where not needed anymore 2012-01-07 17:54:19 +00:00
Stanislav Shwartsman
7defa74261 cleaned up code duplication in CPUDB classes 2012-01-07 17:06:03 +00:00
Stanislav Shwartsman
a804adac46 fixed compilation err with SMP enabled 2012-01-07 16:45:25 +00:00
Stanislav Shwartsman
edfff5bf44 fixed VMX+EPT VirtualBox failures 2012-01-06 10:30:07 +00:00
Stanislav Shwartsman
e2ff4bc6d4 clear exitinfo1/2 fields in SVM on VMENTER 2012-01-05 22:23:05 +00:00
Stanislav Shwartsman
665d4568ee convert most popular svn/vmx msgs to bx_debug - can be used together with enabling log options per device from .bochsrc 2012-01-05 19:42:58 +00:00
Stanislav Shwartsman
fddccfb498 code cleanup + copy/paste removal 2012-01-04 21:36:39 +00:00
Stanislav Shwartsman
0e17f8f195 implemented AMD APIC extensions for SVM support 2012-01-04 16:06:37 +00:00
Stanislav Shwartsman
8c8fa8ec25 vmx cleanups 2012-01-03 20:27:40 +00:00
Stanislav Shwartsman
c857488ed9 Added Corei5 750 (Lynnfield) configuration to the CPUDB 2012-01-02 20:59:02 +00:00
Stanislav Shwartsman
3b98634045 show EFER in debug print outside long mode too 2012-01-02 20:06:03 +00:00
Stanislav Shwartsman
5847e772a6 set async_event when injecting virq to SVM guest 2012-01-01 21:22:56 +00:00
Stanislav Shwartsman
269d5e3443 more SVM fixes 2012-01-01 20:26:23 +00:00
Stanislav Shwartsman
810aa1b67c fixes for SVN. also turion64_tyler supports RDTSCP - include it in CPUID 2012-01-01 17:54:41 +00:00
Stanislav Shwartsman
30d90c1dc1 more SVM fixes 2011-12-31 20:10:11 +00:00
Stanislav Shwartsman
b97a108d93 SVM: allow entering vm8086 and also paged real mode 2011-12-31 16:33:36 +00:00
Stanislav Shwartsman
a0b5ff48ec more SVM fixes 2011-12-31 14:22:51 +00:00
Stanislav Shwartsman
3c0d712146 SVM fixes 2011-12-31 13:58:55 +00:00
Stanislav Shwartsman
fe6741d84d fixed SVM bug 2011-12-31 13:26:55 +00:00
Stanislav Shwartsman
fe6328d18c correctly enable SVM support in internal CPU features list 2011-12-31 12:58:20 +00:00
Stanislav Shwartsman
46d8a5894e removed bad RDMSR/WRMSR check which disabled access to AMD extended MSRs 2011-12-31 12:37:35 +00:00
Stanislav Shwartsman
560e3ca254 compilation fix for smp=0 2011-12-30 18:55:19 +00:00
Stanislav Shwartsman
cee8a3b9ef AMD's core has special 0x80000008.ecx value 2011-12-30 18:53:41 +00:00
Stanislav Shwartsman
088ab4832f turion64 tyler supports cmpxchg16b 2011-12-30 18:46:46 +00:00
Stanislav Shwartsman
2a0d989755 fixed compilation err with SVm w/o VMX 2011-12-30 12:24:22 +00:00
Stanislav Shwartsman
93523a657d remove patch that always kept IF set after HLT - not needed anymore 2011-12-30 08:50:01 +00:00
Stanislav Shwartsman
abda3a967c added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
Stanislav Shwartsman
5da69a6fb4 fixed typo - invalid CPUID leaf should go to max std leaf 2011-12-28 21:59:39 +00:00
Stanislav Shwartsman
2b854cb101 added basic (very basic) SVM CPUID into generic_cpuid module 2011-12-28 21:54:51 +00:00
Stanislav Shwartsman
0a14f08f16 completing SVM coding, missed - CPUID, extended APIC 2011-12-28 16:12:28 +00:00
Stanislav Shwartsman
864ea23b5b take events handling logic from cpu.cc to new file event.cc 2011-12-28 12:26:45 +00:00
Stanislav Shwartsman
2b8371f2b6 implemented SVM_GIF handling 2011-12-27 20:46:15 +00:00
Stanislav Shwartsman
7f5f917a34 more SVM implementation 2011-12-27 19:42:11 +00:00
Stanislav Shwartsman
c32eaa5d05 added more svm intercepts 2011-12-26 20:51:57 +00:00
Stanislav Shwartsman
6ae86a059b firt cleanup in SVM code. added intercept check for MSR and IO 2011-12-26 19:57:39 +00:00
Stanislav Shwartsman
8b4a2c2034 implemented some more intercepts. 
fixed compilation without SVM
 2011-12-26 16:33:13 +00:00
Stanislav Shwartsman
bfcbb81602 SVM: 
- IO intercept is not implemented yet
 - MSR intercept is not implemented yet

VMX:
 Fixed Bochs PANIC crash when doing I/O access crossing VMX I/O permission bitmaps.
 This can happen because access_physical_read and access_physical_write cannot access memory cross 4K boundary.
 2011-12-25 22:09:31 +00:00
Stanislav Shwartsman
ea6dfe3dc0 added svm files 2011-12-25 20:01:48 +00:00
Stanislav Shwartsman
01080243d4 complation fix 2011-12-25 19:58:21 +00:00
Stanislav Shwartsman
a44c1b8e1e SVM and VMX share tsc offset code 2011-12-25 19:53:23 +00:00
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet) 
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
 2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
2dee4b12be added VMX .bochsrc option to ctoggle VMX ON/OFF on runtime 2011-12-21 09:11:51 +00:00
Stanislav Shwartsman
e7ed8aca5c move inhibit interrrupts functionality to icount interface 2011-12-21 06:17:45 +00:00
Stanislav Shwartsman
7cdeecf198 VMX: fixed VirtualBox VMX guest Guru Meditation - FS.BASE get corrupted after saving/restoring unusable selector 2011-12-19 16:06:53 +00:00
Stanislav Shwartsman
6cc03432d9 improve VMX debug print 2011-12-18 21:04:30 +00:00
Stanislav Shwartsman
f6203dae7d instrumentation: added special indication for indirect call/jump 2011-12-18 18:11:56 +00:00
Stanislav Shwartsman
9763643106 VMX: Fixed VMFUNC instruction behavior to align with Intel SDM revision 041 2011-12-17 14:06:23 +00:00
Stanislav Shwartsman
cbbd8bfd46 fixed some warnings after compilation with msvcpp 2010 2011-12-10 18:58:25 +00:00
Stanislav Shwartsman
ac0ebc9728 added debug prints about vmcs initialization 2011-12-09 19:57:40 +00:00
Stanislav Shwartsman
f496e78326 fixed compilation warning 2011-12-02 19:40:31 +00:00
Stanislav Shwartsman
1e3e6ff2af BMI: fixed EFLAGS after BMI instructions (set EFLAGS while preserving PF was not implemented properly in 2.5 release) 2011-11-29 19:50:26 +00:00
Stanislav Shwartsman
b8f2d91b9a fixed compilation err 2011-11-28 21:16:40 +00:00
Stanislav Shwartsman
99bec5155e fixed compilation err in instrumentation module 2011-11-28 10:08:03 +00:00
Stanislav Shwartsman
8cb359fab5 fixed flags handling for BMI instructions 2011-11-27 13:23:26 +00:00
Stanislav Shwartsman
100622e958 fix ULL suffix for 64bit int, use BX_CONST64 instead 2011-11-26 19:01:53 +00:00
Stanislav Shwartsman
f09bdf353a RDMSR can also read TSC so make it end-of-trace as well (same as RDTSC) 2011-11-24 16:03:51 +00:00
Stanislav Shwartsman
f660d3dc68 implemented missed XOP instructions FRCZPS/PD/SS/SD + update CHANGES with fixed bugs 2011-11-24 11:34:26 +00:00
Stanislav Shwartsman
c74f590077 implemented TSC-Deadline APIC timer mode 2011-11-21 12:51:50 +00:00
Stanislav Shwartsman
e4bd200119 do not report TSC Deadline for Sandy Bridge CPUID - not implemented yet 2011-11-20 18:25:39 +00:00
Stanislav Shwartsman
9be8552b80 - Implemented VM Functions support and EPTP-Switching VM Functions 
- Added VMEXIT conditions for INVPCID instruction

Now Bochs is fully aligned with latest pulished Intel's SDM rev040.
 2011-11-05 07:31:51 +00:00
Stanislav Shwartsman
42a0a178eb disasm for XOP instructions 2011-10-30 08:58:49 +00:00
Stanislav Shwartsman
ad9bdbe550 fixed compilation failure 2011-10-21 08:06:55 +00:00
Stanislav Shwartsman
b1a6b34616 implemented PERMIL2PS/PERMIL2PD XOP instructions 2011-10-20 17:37:57 +00:00
Stanislav Shwartsman
ddecc0234a fixed (c) info 2011-10-20 14:06:12 +00:00
Stanislav Shwartsman
3035fcd0af implemented XOP FMADCSWD/FMADCSSWD instructions 2011-10-20 13:55:26 +00:00
Stanislav Shwartsman
5d9bbae71c bugfix: cant use ib2 it is overlap with disp32 2011-10-19 21:28:36 +00:00
Stanislav Shwartsman
5cc04b9955 Implemented AMDs Buldozer XOP and TBM extensions. 
XOP: few instructions are still missing, coming soon

  BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
  BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
  BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
  BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
  BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
 2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
314171bb56 fixed compilation w/o AVX 2011-10-09 13:56:39 +00:00
Stanislav Shwartsman
71cbff104b fixing xsave/xrstor flows with AVX 2011-10-09 09:19:49 +00:00
Stanislav Shwartsman
8ada4ce5e4 added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
Stanislav Shwartsman
2580d8c46d added FMA4 AMD instructions support, fixed mem access length for Intel scalar FMA instructions 2011-10-07 14:09:35 +00:00
Stanislav Shwartsman
aad57310c2 disasm for FMA4, better dbg print SSE rounding control with MXCSR 2011-10-06 20:33:10 +00:00
Stanislav Shwartsman
8a9b8f4622 MXCSR.FUZ is ignoired for F16 instructions 2011-10-03 15:08:22 +00:00
Stanislav Shwartsman
e282b5e88d Move DAZ handling into softfloat library (for float16, float32 and float64 only) and cleanup SSE and AVX code 
Fix decoding of opcodes with VEX.W=1 in 32-bit mode (AVX2, FMA)
 2011-10-01 15:40:36 +00:00
Stanislav Shwartsman
f425400af5 fixed warnings from compilation with mingw-gcc 4.6.1 2011-09-30 20:38:18 +00:00
Stanislav Shwartsman
e5d0540365 commit new added files 2011-09-29 22:38:38 +00:00
Stanislav Shwartsman
6751af5d8e added AVX FMA extensions support. The implementation is based on QEMU patch by Peter Maydell (fixed) 2011-09-29 22:20:56 +00:00
Stanislav Shwartsman
275194fb32 #GP on reading VMX_EPT_VPID_CAP MSR when EPT and VPID disabled 2011-09-26 20:36:26 +00:00
Stanislav Shwartsman
f0d9f8fab7 added some comments 2011-09-26 20:10:15 +00:00
Stanislav Shwartsman
0547c8823e compilation w/o x86-64 2011-09-26 19:48:58 +00:00
Stanislav Shwartsman
12ad45395b enable Penryn VMX capabilities with VMX=1, VMX=2 is required for EPT and heavier stuff 2011-09-26 19:36:20 +00:00
Stanislav Shwartsman
54d1d8aa55 added new assertion to generic cpuid 2011-09-26 18:47:47 +00:00
Stanislav Shwartsman
aa96ecd98a compilation fix 2011-09-26 18:18:10 +00:00
Stanislav Shwartsman
0aadf88c07 more polishing for vmx configurability 2011-09-26 18:08:31 +00:00
Stanislav Shwartsman
c28c7f6a06 Supply real VMX capabilities together with the CPU MODEL .bochsrc option. 
So now the same single option will choose not only the CPUID flags but also VMX capabilities matching real HW machine.

Removed cpuid of core2_extreme_x9770 from the cpudb. I don't remember its VMX capabilities anyway.
There is another Penryn model in the cpudb - core2_penryn_t9600.
 2011-09-26 12:31:40 +00:00
Stanislav Shwartsman
8d95830562 first step to configuration of VMX through cpuid_t class 2011-09-25 19:04:55 +00:00
Stanislav Shwartsman
b66feecc86 move common instrumentation constants (valid for all stubs) to cpu.h 2011-09-25 17:38:54 +00:00
Stanislav Shwartsman
62d0c8abf7 - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 
32-bit CPU using Bochs binary compiled with x86-64 support.

The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
 2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
2b7894de7b fixed dbg print mentioned in SF bug 3029271 2011-09-22 22:08:18 +00:00
Stanislav Shwartsman
1b9f286945 - New way of CPUs scheduling in SMP mode brings up to 50% speedup to the 
SMP emulation. New implementation uses dynamic CPU quantum value and takes
   full advantage of the trace cache. Each emulated processor will execute
   the whole trace before switching to the next processor.
 * It is also safe to use large (up to 16 instructions) quantum values for
   the SMP emulation now and improve performance even further.

The same merge also completely fixes SF bug :
  [3312237] stepN command might be not working properly

Handlers chaining speedups are also supported with SMP emulation now.
 2011-09-22 19:38:52 +00:00
Stanislav Shwartsman
f81589c5d6 Don't allow traces longer than cpu_loop can execute 2011-09-21 20:28:29 +00:00
Stanislav Shwartsman
c6d07ae1b5 store modrm() for x87 in Ib() byte because x87 have no Ib() 2011-09-20 06:02:27 +00:00
Stanislav Shwartsman
2583f8549a small code duplication fix 2011-09-19 20:47:59 +00:00
Stanislav Shwartsman
d489ba3d37 generic cpuid: automatically enable lzcnt of bmi is enabled; sse4a support in cpuid 2011-09-18 18:17:34 +00:00
Stanislav Shwartsman
6fb673b9fa change BX_PANIC to BX_ERROR 2011-09-18 17:36:54 +00:00
Stanislav Shwartsman
50207eeb90 - Added support for AMD SSE4A emulation, the instructions can be enabled 
using .bochsrc CPUID option.
 2011-09-18 16:18:22 +00:00
Stanislav Shwartsman
efc588cf1e rename avx2_gather.cc -> gather.cc 2011-09-16 20:59:57 +00:00
Stanislav Shwartsman
ea54f40361 keep global pages when needed in INVPCID/INVVPID 2011-09-16 20:52:38 +00:00
Stanislav Shwartsman
3632340dac improve bochs exit dump in long64 mode 2011-09-16 20:25:05 +00:00
Stanislav Shwartsman
88a58b3781 fixed compilation with x86-64=0 2011-09-16 20:12:36 +00:00
Stanislav Shwartsman
330bf62f61 added INVPCID instruction support 2011-09-16 20:06:23 +00:00
Stanislav Shwartsman
e2f0880f1c support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
Stanislav Shwartsman
d5fcfabb38 bugfix + update changes 2011-09-13 19:38:09 +00:00
Stanislav Shwartsman
f4dbaf1cd8 re-shuffle macros, no impact in general 2011-09-13 17:55:36 +00:00
Stanislav Shwartsman
02e1a0f23c Merge lazy flags optimization by Darek Mihocka. 
I measure slight but consistent speedup of ~1-3% for all guests.
Tested: Windows XP/7 boot 32/64 bit, various Linux live CD
 2011-09-12 19:36:53 +00:00
Stanislav Shwartsman
9f1f4781b3 fixed Sandy Bridge name in err message - it is Core i7 and not Core2 2011-09-06 19:49:22 +00:00
Stanislav Shwartsman
939aee87c9 handle special case - BSF/BSR vs TZCNT/LZCNT 2011-09-06 19:18:21 +00:00
Stanislav Shwartsman
184837e0ed fixed compilation err with no handlers chaining enabled 2011-09-06 15:41:52 +00:00
Stanislav Shwartsman
96cedbc756 continue handlers-chaining optimization: update time once per trace and not for every instruction 2011-09-06 15:35:39 +00:00
Stanislav Shwartsman
e000b61cfd make RDTSC 'end of trace' instruction - guarantee that any pair ot RDTSC/RDTSCP on same CPU do not belong to same trace (and therefore will always update time and etc) - required for Win7 Thin 2011-09-06 14:13:39 +00:00
Stanislav Shwartsman
5a350143a5 bug fixes 2011-09-06 13:09:45 +00:00
Stanislav Shwartsman
c67338203c small fixups, code cleanup and reorganization 2011-09-05 17:14:49 +00:00
Stanislav Shwartsman
41f9b25777 fixed avx2 gather instructions 2011-09-04 19:50:18 +00:00
Stanislav Shwartsman
c0f5919787 small optimization 2011-09-03 15:36:40 +00:00
Stanislav Shwartsman
8099fd9efd implemented alternative access to CR8: AMD feature. Lock CR0 -> CR8 2011-09-03 15:22:56 +00:00
Stanislav Shwartsman
cf56ffb6e0 BSF/BSR should stay, only F3 prefix change opcode 2011-08-31 21:13:50 +00:00
Stanislav Shwartsman
9d18af1207 fixed compilation for AVX OFF 2011-08-31 20:52:53 +00:00
Stanislav Shwartsman
1f5e036695 lzcnt/tzcnt bmi instructions implemented 2011-08-31 20:43:47 +00:00
Stanislav Shwartsman
d2f7351be2 cpu.h cleanup + update msdev workspaces cpudb projects 2011-08-30 22:22:07 +00:00
Stanislav Shwartsman
dfd769a102 - Fixed compilation issue with cpu-level=5 
- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors
- CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported
- Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
 2011-08-30 22:00:27 +00:00
Stanislav Shwartsman
fb9da23f9b syscall/sysret are not supported outside long64 mode in Intel CPUs 2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
9693bacacb syscall/sysret in legacy mode is supported in k6-2. preparing code to it ... 2011-08-30 20:41:00 +00:00
Stanislav Shwartsman
0f73ff39df bug fix 2011-08-30 19:16:08 +00:00
Stanislav Shwartsman
c30275016e avx2 added broadcast from register 2011-08-29 21:00:25 +00:00
Stanislav Shwartsman
6bdfbeeffa fixed for gather VSIB calculation 2011-08-28 20:14:53 +00:00
Stanislav Shwartsman
239c5a449d added 'locked' information to bxInstruction_c for instrumentation and other future use 2011-08-27 20:09:18 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure 
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
 2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
d841e82d87 MOVBE instruction exists only in memory form 2011-08-25 21:20:50 +00:00
Stanislav Shwartsman
b3898f4bec small optimization for PALIGNR instruction 2011-08-25 19:29:33 +00:00
Stanislav Shwartsman
5dde2dc744 fixed typo 2011-08-23 21:56:35 +00:00
Stanislav Shwartsman
fa930961c2 small optimization 2011-08-23 21:25:34 +00:00
Stanislav Shwartsman
4fae848888 just rename variable 2011-08-23 20:27:52 +00:00
Stanislav Shwartsman
002e7a3818 MSR_TSC_AUX is not available without RDTSCP 2011-08-21 19:09:35 +00:00
Stanislav Shwartsman
371dc200fc Remove the 'trace' debug feature fro the main stream (which now runs with handlers chaining) and this way reduce each handler size. 
Another 3% speedup on WinXP boot on top of handlers chaining + reduction of Bochs binary size by 45K.
 2011-08-21 17:04:21 +00:00
Stanislav Shwartsman
a5e187189a set max trace length back to 32 2011-08-21 16:44:02 +00:00
Stanislav Shwartsman
1e2e3c8b0e forgot to merge file 2011-08-21 14:38:33 +00:00
Stanislav Shwartsman
13feb0772a - 10% emulation speedup with handlers chaining optimization implemented. The 
feature is enabled by default when configure with --enable-all-optimizations
    option, to disable handlers chaining speedups configure with
        --disable-handlers-chaining
 2011-08-21 14:31:08 +00:00
Stanislav Shwartsman
dd79431702 rename AVX handlers - match their real operands 2011-08-20 15:10:18 +00:00
Volker Ruppert
bfdbf589a0 - removed duplicate 'clean' for cpu/cpudb 
- added missing 'dist-clean' for cpu/cpudb
 2011-08-19 06:31:51 +00:00
Stanislav Shwartsman
542af0dcc1 forgot to add a file 2011-08-18 19:02:16 +00:00
Stanislav Shwartsman
b8b63ac6ea compile CPUDB to separate library 
reduce compile-time dependencies
 2011-08-18 18:55:22 +00:00
Stanislav Shwartsman
30b94b112b regen Makefile.in dep 2011-08-18 05:44:54 +00:00
Stanislav Shwartsman
367e8999d6 fixed leaf 0x7 report in cpuid 2011-08-17 21:33:55 +00:00
Stanislav Shwartsman
ed9b8478b5 undo RDTSC commit 2011-08-17 21:13:06 +00:00
Stanislav Shwartsman
165e6f0fdf separate TSC to uniq feature that can be disabled in CPU configuration 2011-08-17 20:57:44 +00:00
Stanislav Shwartsman
4a3209ae31 Increase cpu param length (exceeded with new icount variable) 
CHECK_MAX_INSTRUCTIONS is not needed for debugger anymore.
Next step: eliminate it for SMP as well and remove cpu_loop parameter.
 2011-08-17 20:00:51 +00:00
Stanislav Shwartsman
b69f728246 Fixed internal debugger part of the bug: 
#3312237 stepN command might be not working properly
The problem still can be exists for SMP.
 2011-08-17 19:51:32 +00:00
Stanislav Shwartsman
86d042a46e added AVX to msdev workspaces 2011-08-16 20:44:02 +00:00
Stanislav Shwartsman
b0d7ffeb90 fixed compilation 2011-08-16 20:07:34 +00:00
Stanislav Shwartsman
a03e0266fb added yonah CPUID to cpudb. remove bxversion.h from dep files 2011-08-16 19:58:56 +00:00
Stanislav Shwartsman
0bc93fdc59 added pentium mmx to cpudb. for now only can be enabled when cpu-level=5 2011-08-16 19:04:36 +00:00
Stanislav Shwartsman
6606c62439 cr4 available since Pentium only 2011-08-16 16:49:04 +00:00
Stanislav Shwartsman
e50e187128 #GP on EFER access when not supported 2011-08-14 20:41:46 +00:00
Stanislav Shwartsman
35ec48d17d small fixes 2011-08-13 18:39:17 +00:00
Stanislav Shwartsman
290d3bf6ad typofix 2011-08-12 18:09:24 +00:00
Stanislav Shwartsman
8962cfddde re-definition of x86-64 support, 1st step towards x86-64 enable/disable through .bochsrc 2011-08-12 18:04:56 +00:00
Stanislav Shwartsman
7af5dccdcf fixed compilation issue 2011-08-11 19:45:21 +00:00
Stanislav Shwartsman
d0344a1b84 added Id Revision to new files 2011-08-11 18:17:45 +00:00
Stanislav Shwartsman
6344c6a719 Added P2 Klamath CPUID + some code reorg again 2011-08-11 18:06:09 +00:00
Stanislav Shwartsman
f15bc6cf75 support for NX outside of x86-64. 
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
 2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
1b27438146 cleanups + small code reorg 2011-08-10 20:31:29 +00:00
Stanislav Shwartsman
360481b391 infastructure for RDMSR/WRMSR control for cpuid class 
now the order is going to be:

1. MSRs emulated in Bochs (msr.cc)
2. MSRs emulated in model specific derivative class of cpuid_t
3. MSR can be loaded from msrs.def file
4. MSR is not found. We can fault or ignore based on ignore_bad_msrs option
 2011-08-09 22:11:56 +00:00
Stanislav Shwartsman
0171324877 small favor to VMX OFF for code that compiled with VMX ON 
avoid function call when not in vmx guest.
 2011-08-09 20:50:51 +00:00
Stanislav Shwartsman
17a94fc58e warning fixes 2011-08-09 18:00:19 +00:00
Stanislav Shwartsman
c6c94a79da dos2unix for generic_cpuid.cc 
fixed xsave leaf CPUID (again)
added one more CPUID configuration: Intel Mobile Core 2 Duo T9600
 2011-08-08 18:20:29 +00:00
Stanislav Shwartsman
4476dea8f8 remove redundant code 2011-08-08 05:47:49 +00:00
Stanislav Shwartsman
20becdfbe7 fix compilation errors 2011-08-05 07:22:43 +00:00
Stanislav Shwartsman
2ee0029749 extract ffxsr support to separate CPU feature 2011-08-04 19:02:49 +00:00
Stanislav Shwartsman
b6e37b818d small changes 2011-08-04 17:35:08 +00:00
Stanislav Shwartsman
1068b4bd8c cleanup 2011-08-03 21:46:46 +00:00
Stanislav Shwartsman
5ffb201184 fixed CPU leaf 0xD 2011-08-03 21:23:08 +00:00
Stanislav Shwartsman
1adda7bf64 Fixed MWAIT leaf CPUID - required for Fedora15 startup 2011-08-03 20:29:24 +00:00
Stanislav Shwartsman
5451be2676 remove duplicated code 2011-08-03 18:09:07 +00:00
Stanislav Shwartsman
9162c0dc2a dos2unix 2011-08-03 17:50:23 +00:00
Stanislav Shwartsman
075db389a9 added atom n270 cpuid + small fixes 2011-08-03 17:49:49 +00:00
Stanislav Shwartsman
b9a44a9dbf added const to all cpudb methods 2011-08-01 18:10:48 +00:00
Stanislav Shwartsman
ea7d5e74ee fixed cpuid_limit_winnt mode 2011-07-31 21:02:04 +00:00
Stanislav Shwartsman
e958df1333 report 3dnow for amd cpudb machine 2011-07-31 20:19:09 +00:00
Stanislav Shwartsman
bccf330665 typo fix 2011-07-31 20:11:04 +00:00
Stanislav Shwartsman
d84dbcd02b fixed *x86 ISA extensions that enable this instruction* in ia_opcodes.h 2011-07-31 20:09:04 +00:00
Stanislav Shwartsman
04635ca88b small fixes 2011-07-31 19:00:56 +00:00
Stanislav Shwartsman
1d89709e62 Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). 
Reimplemented CPUDB using pure C macros magic.
Fixed compilation errors when compiling with SMP on.
 2011-07-31 18:43:46 +00:00
Stanislav Shwartsman
6e6db04b8f Fixed compilation errors, dos2unix, added missed p3_katmai.txt 2011-07-31 14:56:45 +00:00
Stanislav Shwartsman
5e291e0860 Added Athlon64 Clawhammer CPUID to CPUDB 2011-07-30 21:28:16 +00:00
Stanislav Shwartsman
fefa4d5e5b added PIII Katmai to CPUDB 2011-07-30 14:30:35 +00:00
Stanislav Shwartsman
7a157cf88d fixed vmexit for xsetbv and getsec 2011-07-30 13:21:31 +00:00
Stanislav Shwartsman
6aaf9297f8 ability to turn off rdtscp 2011-07-30 09:35:20 +00:00
Stanislav Shwartsman
e48765a511 VMX fixed, cleanups 2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
37d8523ab4 fixed compilation with VMX=1 2011-07-29 18:41:17 +00:00
Stanislav Shwartsman
4ac67ec386 compilation when cu_level < 4 2011-07-29 15:24:32 +00:00
Stanislav Shwartsman
919fbd95da fixed CPUID after correlation with real HW CPUZ output 2011-07-29 15:18:39 +00:00
Stanislav Shwartsman
1a051f9f00 Added several predefined CPUs that can be selected from .bochsrc using new CPU::MODEL option. 
Selecting CPU MODEL from .bochsrc automatically chooses real HW CPUID and also configures Bochs emulator to emulate this specific CPU including all its features only.
Supported CPUs to choose from:
	core2_extreme_x9770
	corei7_sandy_bridge_2600K
	p4_prescott_celeron_336
 2011-07-29 15:03:54 +00:00
Stanislav Shwartsman
74fc3da79d conditional compile for generic cpuid 2011-07-28 19:20:16 +00:00
Stanislav Shwartsman
5da595e603 fixed OSXSAVE CPUID reporting 2011-07-28 16:38:22 +00:00
Stanislav Shwartsman
6ef7675d03 added new file 2011-07-28 16:21:18 +00:00
Stanislav Shwartsman
6ad0f5ddb2 regenerate dep for CPU 2011-07-28 16:19:30 +00:00
Stanislav Shwartsman
78327d3e5e First step toward completely configurable CPU. 
Change CPUID to generic interface which could be chosen from .bochsrc.
Bochs CPU emulation will enable/disable features (like instruction sets) according to CPUID that is selected.
TODO: Add database of CPUID from real hardware CPUs
 2011-07-28 16:17:42 +00:00
Stanislav Shwartsman
81f6a283e2 trim cpuid info from save/restore tree 2011-07-27 14:16:51 +00:00
Stanislav Shwartsman
f8e4e7f16b clean up/fixed instrumentation examples + removed old 2-years old configure options check (deprecated) 2011-07-23 19:58:38 +00:00
Stanislav Shwartsman
d11114ac19 Patch for emulating target with larger memory than host has available by Gary Cameron. 
The patch was posted in mailing list at Thu 6/16/2011.

Desription for CHANGES:

- Memory
  - Added new configure option which enables RAM file backing for large guest
    memory with a smaller amount host memory, without causing a panic when
    host memory is exhausted (patch by Gary Cameron). To enable configure with
        --enable-large-ramfile option.
 2011-07-22 17:46:06 +00:00
Stanislav Shwartsman
1e2c7de064 register state for pause-loop exiting 2011-07-22 09:28:31 +00:00
Stanislav Shwartsman
9c3a4b8dab impemented pause-loop exiting VMX2 control 2011-07-22 09:19:35 +00:00
Stanislav Shwartsman
d1780b66de typofix 2011-07-21 21:34:56 +00:00
Stanislav Shwartsman
b4118fcbfe correct natural width VMX field read/write len 2011-07-21 20:58:54 +00:00