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- Added support for AMD SSE4A emulation, the instructions can be enabled

Browse Source 
using .bochsrc CPUID option.
This commit is contained in:
Stanislav Shwartsman 2011-09-18 16:18:22 +00:00
parent efc588cf1e
commit 50207eeb90
21 changed files with 217 additions and 35 deletions
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4
bochs/.bochsrc
View File

@ -183,6 +183,10 @@ cpu: cpuid_limit_winnt=0
# Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 could be selected.
# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# SSE4A:
# Select AMD SSE4A instructions support.
# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# AES:
# Select AES instruction set support.
# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.

2
bochs/CHANGES
View File

@ -29,6 +29,8 @@ Bochs repository moved to the SVN version control !
enabled using .bochsrc CPUID option.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
- Added support for AMD SSE4A emulation, the instructions can be enabled
using .bochsrc CPUID option.
- Implemented VMX preemption timer VMEXIT control (patch by Jianan Hao)
- Implemented Pause-Loop Exiting Secondary VMEXIT control.
- Added INVPCID instruction emulation support.

1
bochs/PARAM_TREE.txt
View File

@ -36,6 +36,7 @@ cpuid
mmx
sep
sse
sse4a
aes
movbe
xsave

14
bochs/config.cc
View File

@ -289,7 +289,7 @@ void bx_init_options()
// cpuid subtree
#if BX_CPU_LEVEL >= 4
bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 22);
bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 23);
new bx_param_string_c(cpuid_param,
"vendor_string",
@ -356,6 +356,11 @@ void bx_init_options()
BX_CPUID_SUPPORT_SSE2,
BX_CPUID_SUPPORT_NOSSE);
new bx_param_bool_c(cpuid_param,
"sse4a", "Support for AMD SSE4A instructions",
"Support for AMD SSE4A instructionã",
0);
new bx_param_bool_c(cpuid_param,
"sep", "Support for SYSENTER/SYSEXIT instructions",
"Support for SYSENTER/SYSEXIT instructions",
@ -2665,6 +2670,10 @@ static int parse_line_formatted(const char *context, int num_params, char *param
} else if (!strncmp(params[i], "sse=", 4)) {
if (! SIM->get_param_enum(BXPN_CPUID_SSE)->set_by_name(&params[i][4]))
PARSE_ERR(("%s: unsupported sse option.", context));
} else if (!strncmp(params[i], "sse4a=", 6)) {
if (parse_param_bool(params[i], 6, BXPN_CPUID_SSE4A) < 0) {
PARSE_ERR(("%s: cpuid directive malformed.", context));
}
} else if (!strncmp(params[i], "aes=", 4)) {
if (parse_param_bool(params[i], 4, BXPN_CPUID_AES) < 0) {
PARSE_ERR(("%s: cpuid directive malformed.", context));
@ -3974,8 +3983,9 @@ int bx_write_configuration(const char *rc, int overwrite)
SIM->get_param_enum(BXPN_CPUID_APIC)->get_selected());
#endif
#if BX_CPU_LEVEL >= 6
fprintf(fp, ", sse=%s, sep=%d, aes=%d, xsave=%d, xsaveopt=%d, movbe=%d, smep=%d",
fprintf(fp, ", sse=%s, sse4a=%d, sep=%d, aes=%d, xsave=%d, xsaveopt=%d, movbe=%d, smep=%d",
SIM->get_param_enum(BXPN_CPUID_SSE)->get_selected(),
SIM->get_param_bool(BXPN_CPUID_SSE4A)->get(),
SIM->get_param_bool(BXPN_CPUID_SEP)->get(),
SIM->get_param_bool(BXPN_CPUID_AES)->get(),
SIM->get_param_bool(BXPN_CPUID_XSAVE)->get(),

8
bochs/cpu/cpu.h
View File

@ -2808,6 +2808,13 @@ public: // for now...
#endif
/* BMI - TZCNT */
/* SSE4A */
BX_SMF BX_INSF_TYPE EXTRQ_UdqIbIb(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE EXTRQ_VdqUq(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE INSERTQ_VdqUqIbIb(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE INSERTQ_VdqUdq(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
/* SSE4A */
BX_SMF BX_INSF_TYPE CMPXCHG8B(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RETnear32_Iw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RETnear32(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -4472,6 +4479,7 @@ enum {
#define BxGroup15 BxSplitGroupN
#define BxGroup16 BxGroupN
#define BxGroup17 BxGroupN
#define BxGroup17A BxGroupN
#define BxGroupFP BxSplitGroupN

11
bochs/cpu/cpuid.h
View File

@ -71,8 +71,8 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPU_PENTIUM (BX_CONST64(1) << 2) /* Pentium new instruction */
#define BX_CPU_P6 (BX_CONST64(1) << 3) /* P6 new instruction */
#define BX_CPU_MMX (BX_CONST64(1) << 4) /* MMX instruction */
#define BX_CPU_3DNOW (BX_CONST64(1) << 5) /* 3DNow! instruction */
#define BX_CPU_SYSCALL_SYSRET (BX_CONST64(1) << 6) /* SYSCALL/SYSRET in legacy mode */
#define BX_CPU_3DNOW (BX_CONST64(1) << 5) /* 3DNow! instruction (AMD) */
#define BX_CPU_SYSCALL_SYSRET (BX_CONST64(1) << 6) /* SYSCALL/SYSRET in legacy mode (AMD) */
#define BX_CPU_SYSENTER_SYSEXIT (BX_CONST64(1) << 7) /* SYSENTER/SYSEXIT instruction */
#define BX_CPU_CLFLUSH (BX_CONST64(1) << 8) /* CLFLUSH instruction */
#define BX_CPU_SSE (BX_CONST64(1) << 9) /* SSE instruction */
@ -96,9 +96,10 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPU_AVX2 (BX_CONST64(1) << 27) /* AVX2 instruction */
#define BX_CPU_AVX_F16C (BX_CONST64(1) << 28) /* AVX F16 convert instruction */
#define BX_CPU_AVX_FMA (BX_CONST64(1) << 29) /* AVX FMA instruction */
#define BX_CPU_LZCNT (BX_CONST64(1) << 30) /* LZCNT instruction */
#define BX_CPU_BMI1 (BX_CONST64(1) << 31) /* BMI1 instruction */
#define BX_CPU_BMI2 (BX_CONST64(1) << 32) /* BMI2 instruction */
#define BX_CPU_SSE4A (BX_CONST64(1) << 30) /* SSE4A instruction (AMD) */
#define BX_CPU_LZCNT (BX_CONST64(1) << 31) /* LZCNT instruction */
#define BX_CPU_BMI1 (BX_CONST64(1) << 32) /* BMI1 instruction */
#define BX_CPU_BMI2 (BX_CONST64(1) << 33) /* BMI2 instruction */
// cpuid non-ISA features
#define BX_CPU_DEBUG_EXTENSIONS (1 << 0) /* Debug Extensions support */

8
bochs/cpu/fetchdecode.cc
View File

@ -584,8 +584,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 75 /w */ { BxPrefixSSE, BX_IA_PCMPEQW_PqQq, BxOpcodeGroupSSE_0f75 },
/* 0F 76 /w */ { BxPrefixSSE, BX_IA_PCMPEQD_PqQq, BxOpcodeGroupSSE_0f76 },
/* 0F 77 /w */ { BxPrefixSSE, BX_IA_EMMS, BxOpcodeGroupSSE_ERR },
/* 0F 78 /w */ { BxPrefixSSE, BX_IA_VMREAD_EdGd, BxOpcodeGroupSSE_ERR },
/* 0F 79 /w */ { BxPrefixSSE, BX_IA_VMWRITE_GdEd, BxOpcodeGroupSSE_ERR },
/* 0F 78 /w */ { BxPrefixSSE, BX_IA_VMREAD_EdGd, BxOpcodeGroupSSE4A_0f78 },
/* 0F 79 /w */ { BxPrefixSSE, BX_IA_VMWRITE_GdEd, BxOpcodeGroupSSE4A_0f79 },
/* 0F 7A /w */ { 0, BX_IA_ERROR },
/* 0F 7B /w */ { 0, BX_IA_ERROR },
/* 0F 7C /w */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
@ -1129,8 +1129,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 75 /d */ { BxPrefixSSE, BX_IA_PCMPEQW_PqQq, BxOpcodeGroupSSE_0f75 },
/* 0F 76 /d */ { BxPrefixSSE, BX_IA_PCMPEQD_PqQq, BxOpcodeGroupSSE_0f76 },
/* 0F 77 /d */ { BxPrefixSSE, BX_IA_EMMS, BxOpcodeGroupSSE_ERR },
/* 0F 78 /d */ { BxPrefixSSE, BX_IA_VMREAD_EdGd, BxOpcodeGroupSSE_ERR },
/* 0F 79 /d */ { BxPrefixSSE, BX_IA_VMWRITE_GdEd, BxOpcodeGroupSSE_ERR },
/* 0F 78 /d */ { BxPrefixSSE, BX_IA_VMREAD_EdGd, BxOpcodeGroupSSE4A_0f78 },
/* 0F 79 /d */ { BxPrefixSSE, BX_IA_VMWRITE_GdEd, BxOpcodeGroupSSE4A_0f79 },
/* 0F 7A /d */ { 0, BX_IA_ERROR },
/* 0F 7B /d */ { 0, BX_IA_ERROR },
/* 0F 7C /d */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },

12
bochs/cpu/fetchdecode64.cc
View File

@ -516,8 +516,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 75 /w */ { BxPrefixSSE, BX_IA_PCMPEQW_PqQq, BxOpcodeGroupSSE_0f75 },
/* 0F 76 /w */ { BxPrefixSSE, BX_IA_PCMPEQD_PqQq, BxOpcodeGroupSSE_0f76 },
/* 0F 77 /w */ { BxPrefixSSE, BX_IA_EMMS, BxOpcodeGroupSSE_ERR },
/* 0F 78 /w */ { BxPrefixSSE, BX_IA_VMREAD_EqGq, BxOpcodeGroupSSE_ERR },
/* 0F 79 /w */ { BxPrefixSSE, BX_IA_VMWRITE_GqEq, BxOpcodeGroupSSE_ERR },
/* 0F 78 /w */ { BxPrefixSSE, BX_IA_VMREAD_EqGq, BxOpcodeGroupSSE4A_0f78 },
/* 0F 79 /w */ { BxPrefixSSE, BX_IA_VMWRITE_GqEq, BxOpcodeGroupSSE4A_0f79 },
/* 0F 7A /w */ { 0, BX_IA_ERROR },
/* 0F 7B /w */ { 0, BX_IA_ERROR },
/* 0F 7C /w */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
@ -1031,8 +1031,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 75 /d */ { BxPrefixSSE, BX_IA_PCMPEQW_PqQq, BxOpcodeGroupSSE_0f75 },
/* 0F 76 /d */ { BxPrefixSSE, BX_IA_PCMPEQD_PqQq, BxOpcodeGroupSSE_0f76 },
/* 0F 77 /d */ { BxPrefixSSE, BX_IA_EMMS, BxOpcodeGroupSSE_ERR },
/* 0F 78 /d */ { BxPrefixSSE, BX_IA_VMREAD_EqGq, BxOpcodeGroupSSE_ERR },
/* 0F 79 /d */ { BxPrefixSSE, BX_IA_VMWRITE_GqEq, BxOpcodeGroupSSE_ERR },
/* 0F 78 /d */ { BxPrefixSSE, BX_IA_VMREAD_EqGq, BxOpcodeGroupSSE4A_0f78 },
/* 0F 79 /d */ { BxPrefixSSE, BX_IA_VMWRITE_GqEq, BxOpcodeGroupSSE4A_0f79 },
/* 0F 7A /d */ { 0, BX_IA_ERROR },
/* 0F 7B /d */ { 0, BX_IA_ERROR },
/* 0F 7C /d */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
@ -1546,8 +1546,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 75 /q */ { BxPrefixSSE, BX_IA_PCMPEQW_PqQq, BxOpcodeGroupSSE_0f75 },
/* 0F 76 /q */ { BxPrefixSSE, BX_IA_PCMPEQD_PqQq, BxOpcodeGroupSSE_0f76 },
/* 0F 77 /q */ { BxPrefixSSE, BX_IA_EMMS, BxOpcodeGroupSSE_ERR },
/* 0F 78 /q */ { BxPrefixSSE, BX_IA_VMREAD_EqGq, BxOpcodeGroupSSE_ERR },
/* 0F 79 /q */ { BxPrefixSSE, BX_IA_VMWRITE_GqEq, BxOpcodeGroupSSE_ERR },
/* 0F 78 /q */ { BxPrefixSSE, BX_IA_VMREAD_EqGq, BxOpcodeGroupSSE4A_0f78 },
/* 0F 79 /q */ { BxPrefixSSE, BX_IA_VMWRITE_GqEq, BxOpcodeGroupSSE4A_0f79 },
/* 0F 7A /q */ { 0, BX_IA_ERROR },
/* 0F 7B /q */ { 0, BX_IA_ERROR },
/* 0F 7C /q */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },

27
bochs/cpu/fetchdecode_sse.h
View File

@ -40,6 +40,29 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_PAUSE[3] = {
/* F2 */ { 0, BX_IA_NOP }
};
static const BxOpcodeInfo_t BxOpcodeInfoG17A[8] = {
/* 0 */ { BxImmediate_Ib | BxImmediate_Ib2, BX_IA_EXTRQ_UdqIbIb },
/* 1 */ { 0, BX_IA_ERROR },
/* 2 */ { 0, BX_IA_ERROR },
/* 3 */ { 0, BX_IA_ERROR },
/* 4 */ { 0, BX_IA_ERROR },
/* 5 */ { 0, BX_IA_ERROR },
/* 6 */ { 0, BX_IA_ERROR },
/* 7 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE4A_0f78[3] = {
/* 66 */ { BxGroup17A, BX_IA_ERROR, BxOpcodeInfoG17A },
/* F3 */ { 0, BX_IA_ERROR },
/* F2 */ { BxImmediate_Ib | BxImmediate_Ib2, BX_IA_INSERTQ_VdqUqIbIb }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE4A_0f79[3] = {
/* 66 */ { 0, BX_IA_EXTRQ_VdqUq },
/* F3 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_INSERTQ_VdqUdq }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_TZCNT16[3] = {
/* 66 */ { 0, BX_IA_BSF_GwEw },
/* F3 */ { 0, BX_IA_TZCNT_GwEw },
@ -156,8 +179,8 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2aQ[3] = {
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2bM[3] = {
/* 66 */ { 0, BX_IA_MOVNTPD_MpdVpd },
/* F3 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_ERROR }
/* F3 */ { 0, BX_IA_MOVNTSS_MssVss },
/* F2 */ { 0, BX_IA_MOVNTSD_MsdVsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2c[3] = {

10
bochs/cpu/generic_cpuid.cc
View File

@ -679,6 +679,16 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
if (sse_enabled >= BX_CPUID_SUPPORT_SSE2)
features_bitmask |= BX_CPU_CLFLUSH;
static bx_bool sse4a_enabled = SIM->get_param_bool(BXPN_CPUID_SSE4A)->get();
if (sse4a_enabled) {
features_bitmask |= BX_CPU_SSE4A;
if (! sse_enabled) {
BX_PANIC(("PANIC: SSE4A require SSE to be enabled !"));
return;
}
}
static bx_bool sep_enabled = SIM->get_param_bool(BXPN_CPUID_SEP)->get();
if (sep_enabled)
features_bitmask |= BX_CPU_SYSENTER_SYSEXIT;

9
bochs/cpu/ia_opcodes.h
View File

@ -1883,3 +1883,12 @@ bx_define_opcode(BX_IA_LZCNT_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::LZCNT_GdEdR, B
#if BX_SUPPORT_X86_64
bx_define_opcode(BX_IA_LZCNT_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::LZCNT_GqEqR, BX_CPU_LZCNT, 0)
#endif
// SSE4A
bx_define_opcode(BX_IA_MOVNTSS_MssVss, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::BxError, BX_CPU_SSE4A, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVNTSD_MsdVsd, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::BxError, BX_CPU_SSE4A, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_EXTRQ_UdqIbIb, &BX_CPU_C::BxError, &BX_CPU_C::EXTRQ_UdqIbIb, BX_CPU_SSE4A, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_EXTRQ_VdqUq, &BX_CPU_C::BxError, &BX_CPU_C::EXTRQ_VdqUq, BX_CPU_SSE4A, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_INSERTQ_VdqUqIbIb, &BX_CPU_C::BxError, &BX_CPU_C::INSERTQ_VdqUqIbIb, BX_CPU_SSE4A, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_INSERTQ_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::INSERTQ_VdqUdq, BX_CPU_SSE4A, BX_PREPARE_SSE)
// SSE4A

80
bochs/cpu/sse.cc
View File

@ -631,3 +631,83 @@ SSE_PSHIFT_IMM_CPU_LEVEL6(PSLLQ_UdqIb, sse_psllq);
SSE_PSHIFT_IMM_CPU_LEVEL6(PSRLDQ_UdqIb, sse_psrldq);
SSE_PSHIFT_IMM_CPU_LEVEL6(PSLLDQ_UdqIb, sse_pslldq);
/* ************************ */
/* SSE4A (AMD) INSTRUCTIONS */
/* ************************ */
#if BX_CPU_LEVEL >= 6
BX_CPP_INLINE Bit64u sse_extrq(Bit64u src, unsigned shift, unsigned len)
{
len &= 0x3f;
shift &= 0x3f;
src >>= shift;
if (len) {
Bit64u mask = (BX_CONST64(1) << len) - 1;
return src & mask;
}
return src;
}
BX_CPP_INLINE Bit64u sse_insertq(Bit64u dest, Bit64u src, unsigned shift, unsigned len)
{
Bit64u mask;
len &= 0x3f;
shift &= 0x3f;
if (len == 0) {
mask = BX_CONST64(0xffffffffffffffff);
} else {
mask = (BX_CONST64(1) << len) - 1;
}
return (dest & ~(mask << shift)) | ((src & mask) << shift);
}
#endif
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRQ_UdqIbIb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BX_WRITE_XMM_REG_LO_QWORD(i->rm(), sse_extrq(BX_READ_XMM_REG_LO_QWORD(i->rm()), i->Ib2(), i->Ib()));
#endif
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRQ_VdqUq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
Bit16u ctrl = BX_READ_XMM_REG_LO_WORD(i->rm());
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), sse_extrq(BX_READ_XMM_REG_LO_QWORD(i->nnn()), ctrl >> 8, ctrl));
#endif
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INSERTQ_VdqUqIbIb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
Bit64u dest = BX_READ_XMM_REG_LO_QWORD(i->nnn()), src = BX_READ_XMM_REG_LO_QWORD(i->rm());
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), sse_insertq(dest, src, i->Ib2(), i->Ib()));
#endif
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INSERTQ_VdqUdq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister src = BX_READ_XMM_REG(i->rm());
Bit64u dest = BX_READ_XMM_REG_LO_QWORD(i->nnn());
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), sse_insertq(dest, src.xmm64u(0), src.xmmubyte(9), src.xmmubyte(8)));
#endif
BX_NEXT_INSTR(i);
}

1
bochs/disasm/dis_groups.cc
View File

@ -419,6 +419,7 @@ void disassembler::Udq(const x86_insn *insn)
void disassembler::Ups(const x86_insn *insn) { Udq(insn); }
void disassembler::Upd(const x86_insn *insn) { Udq(insn); }
void disassembler::Uq(const x86_insn *insn) { Uq(insn); }
void disassembler::Vq(const x86_insn *insn)
{

1
bochs/disasm/dis_tables.h
View File

@ -142,6 +142,7 @@
#define Ups &disassembler::Ups
#define Upd &disassembler::Upd
#define Udq &disassembler::Udq
#define Uq &disassembler::Uq
#define Wb &disassembler::Wb
#define Ww &disassembler::Ww

31
bochs/disasm/dis_tables_sse.inc
View File

@ -121,8 +121,8 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f2a[4] = {
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f2b[4] = {
/* -- */ { 0, &Ia_movntps_Mps_Vps },
/* 66 */ { 0, &Ia_movntpd_Mpd_Vpd },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
/* F3 */ { 0, &Ia_movntss_Mss_Vss }, // SSE4A
/* F2 */ { 0, &Ia_movntsd_Msd_Vsd } // SSE4A
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f2c[4] = {
@ -398,32 +398,43 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f76[4] = {
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE4A_G17[8] = {
/* 0 */ { 0, &Ia_extrq_Udq_Ib_Ib }, // SSE4A
/* 1 */ { 0, &Ia_Invalid },
/* 2 */ { 0, &Ia_Invalid },
/* 3 */ { 0, &Ia_Invalid },
/* 4 */ { 0, &Ia_Invalid },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { 0, &Ia_Invalid },
/* 7 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f78[4] = {
/* -- */ { 0, &Ia_vmread_Ed_Gd }, // VMX
/* 66 */ { 0, &Ia_Invalid },
/* 66 */ { GRPN(SSE4A_G17) }, // SSE4A
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
/* F2 */ { 0, &Ia_insertq_Vdq_Uq_Ib_Ib } // SSE4A
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f78Q[4] = {
/* -- */ { 0, &Ia_vmread_Eq_Gq }, // VMX
/* 66 */ { 0, &Ia_Invalid },
/* 66 */ { GRPN(SSE4A_G17) }, // SSE4A
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
/* F2 */ { 0, &Ia_insertq_Vdq_Uq_Ib_Ib } // SSE4A
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f79[4] = {
/* -- */ { 0, &Ia_vmwrite_Gd_Ed }, // VMX
/* 66 */ { 0, &Ia_Invalid },
/* 66 */ { 0, &Ia_extrq_Vdq_Uq }, // SSE4A
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
/* F2 */ { 0, &Ia_insertq_Vdq_Udq } // SSE4A
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f79Q[4] = {
/* -- */ { 0, &Ia_vmwrite_Gq_Eq }, // VMX
/* 66 */ { 0, &Ia_Invalid },
/* 66 */ { 0, &Ia_extrq_Vdq_Uq }, // SSE4A
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
/* F2 */ { 0, &Ia_insertq_Vdq_Udq } // SSE4A
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f7c[4] = {

12
bochs/disasm/disasm.h
View File

@ -44,8 +44,8 @@
#define IA_PENTIUM (BX_CONST64(1) << 2) /* Pentium new instruction */
#define IA_P6 (BX_CONST64(1) << 3) /* P6 new instruction */
#define IA_MMX (BX_CONST64(1) << 4) /* MMX instruction */
#define IA_3DNOW (BX_CONST64(1) << 5) /* 3DNow! instruction */
#define IA_SYSCALL_SYSRET (BX_CONST64(1) << 6) /* SYSCALL/SYSRET in legacy mode */
#define IA_3DNOW (BX_CONST64(1) << 5) /* 3DNow! instruction (AMD) */
#define IA_SYSCALL_SYSRET (BX_CONST64(1) << 6) /* SYSCALL/SYSRET in legacy mode (AMD) */
#define IA_SYSENTER_SYSEXIT (BX_CONST64(1) << 7) /* SYSENTER/SYSEXIT instruction */
#define IA_CLFLUSH (BX_CONST64(1) << 8) /* CLFLUSH instruction */
#define IA_SSE (BX_CONST64(1) << 9) /* SSE instruction */
@ -69,9 +69,10 @@
#define IA_AVX2 (BX_CONST64(1) << 27) /* AVX2 instruction */
#define IA_AVX_F16C (BX_CONST64(1) << 28) /* AVX F16 convert instruction */
#define IA_AVX_FMA (BX_CONST64(1) << 29) /* AVX FMA instruction */
#define IA_LZCNT (BX_CONST64(1) << 30) /* LZCNT instruction */
#define IA_BMI1 (BX_CONST64(1) << 31) /* BMI1 instruction */
#define IA_BMI2 (BX_CONST64(1) << 32) /* BMI2 instruction */
#define IA_SSE4A (BX_CONST64(1) << 30) /* SSE4A instruction (AMD) */
#define IA_LZCNT (BX_CONST64(1) << 31) /* LZCNT instruction */
#define IA_BMI1 (BX_CONST64(1) << 32) /* BMI1 instruction */
#define IA_BMI2 (BX_CONST64(1) << 33) /* BMI2 instruction */
/* general purpose bit register */
enum {
@ -517,6 +518,7 @@ public:
void Ups(const x86_insn *insn);
void Upd(const x86_insn *insn);
void Udq(const x86_insn *insn);
void Uq(const x86_insn *insn);
void Vdq(const x86_insn *insn);
void Vss(const x86_insn *insn);

6
bochs/disasm/opcodes.inc
View File

@ -292,6 +292,8 @@ Ia_emms = { "emms", "emms", XX, XX, XX, XX, IA_MMX },
Ia_enter = { "enter", "enter", IwIb, XX, XX, XX, 0 },
Ia_error = { "(error)", "(error)", XX, XX, XX, XX, 0 },
Ia_extractps_Ed_Vdq_Ib = { "extractps", "extractps", Ed, Vdq, Ib, XX, IA_SSE4_1 },
Ia_extrq_Udq_Ib_Ib = { "extrq", "extrq", Udq, Ib, Ib, XX, IA_SSE4A },
Ia_extrq_Vdq_Uq = { "extrq", "extrq", Vdq, Uq, XX, XX, IA_SSE4A },
Ia_f2xm1 = { "f2xm1", "f2xm1", XX, XX, XX, XX, IA_X87 },
Ia_fabs = { "fabs", "fabs", XX, XX, XX, XX, IA_X87 },
Ia_fadd_ST0_STi = { "fadd", "fadd", ST0, STi, XX, XX, IA_X87 },
@ -467,6 +469,8 @@ Ia_inl_EAX_DX = { "in", "inl", EAX_Reg, DX_Reg, XX, XX, 0 },
Ia_inl_EAX_Ib = { "in", "inl", EAX_Reg, Ib, XX, XX, 0 },
Ia_insb_Yb_DX = { "insb", "insb", Yb, DX_Reg, XX, XX, 0 },
Ia_insertps_Vps_Wss_Ib = { "insertps", "insertps", Vps, Wss, Ib, XX, IA_SSE4_1 },
Ia_insertq_Vdq_Udq = { "insertq", "insertq", Vdq, Udq, XX, XX, IA_SSE4A },
Ia_insertq_Vdq_Uq_Ib_Ib = { "insertq", "insertq", Vdq, Uq, Ib, Ib, IA_SSE4A },
Ia_insl_Yd_DX = { "insd", "insl", Yd, DX_Reg, XX, XX, 0 },
Ia_insw_Yw_DX = { "insw", "insw", Yw, DX_Reg, XX, XX, 0 },
Ia_int_Ib = { "int", "int", Ib, XX, XX, XX, 0 },
@ -662,6 +666,8 @@ Ia_movntiq_Mq_Gq = { "movntiq", "movntiq", Mq, Gq, XX, XX, 0 },
Ia_movntpd_Mpd_Vpd = { "movntpd", "movntpd", Mpd, Vpd, XX, XX, IA_SSE2 },
Ia_movntps_Mps_Vps = { "movntps", "movntps", Mps, Vps, XX, XX, IA_SSE },
Ia_movntq_Mq_Pq = { "movntq", "movntq", Mq, Pq, XX, XX, IA_3DNOW | IA_SSE },
Ia_movntsd_Msd_Vsd = { "movntsd", "movntsd", Msd, Vsd, XX, XX, IA_SSE4A },
Ia_movntss_Mss_Vss = { "movntss", "movntss", Mss, Vss, XX, XX, IA_SSE4A },
Ia_movq_Cq_Rq = { "mov", "movq", Cq, Rq, XX, XX, 0 },
Ia_movq_Dq_Rq = { "mov", "movq", Dq, Rq, XX, XX, 0 },
Ia_movq_Eq_Gq = { "mov", "movq", Eq, Gq, XX, XX, 0 },

5
bochs/doc/docbook/user/user.dbk
View File

@ -3036,6 +3036,11 @@ Select SSE instruction set support.
Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 could be selected.
This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
</para>
<para><command>sse4a</command></para>
<para>
Select AMD SSE4A instructions support.
This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
</para>
<para><command>aes</command></para>
<para>
Select AES instruction set support.

5
bochs/doc/man/bochsrc.5
View File

@ -213,6 +213,11 @@ Select SSE instruction set support.
Any of NONE/SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 could be selected.
This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
sse4a:
Select AMD SSE4A instructions support.
This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
aes:
Select AES instruction set support.

4
bochs/main.cc
View File

@ -1048,6 +1048,7 @@ void bx_init_hardware()
bx_bool mmx_enabled = SIM->get_param_bool(BXPN_CPUID_MMX)->get();
#endif
#if BX_CPU_LEVEL >= 6
bx_bool sse4a_enabled = SIM->get_param_bool(BXPN_CPUID_SSE4A)->get();
bx_bool aes_enabled = SIM->get_param_bool(BXPN_CPUID_AES)->get();
bx_bool movbe_enabled = SIM->get_param_bool(BXPN_CPUID_MOVBE)->get();
bx_bool sep_enabled = SIM->get_param_bool(BXPN_CPUID_SEP)->get();
@ -1076,7 +1077,8 @@ void bx_init_hardware()
#endif
#if BX_CPU_LEVEL >= 6
BX_INFO((" SEP support: %s", sep_enabled?"yes":"no"));
BX_INFO((" SSE support: %s", SIM->get_param_enum(BXPN_CPUID_SSE)->get_selected()));
BX_INFO((" SSE support: %s%s", SIM->get_param_enum(BXPN_CPUID_SSE)->get_selected(),
sse4a_enabled ? "+sse4a" : ""));
BX_INFO((" XSAVE support: %s %s",
xsave_enabled?"xsave":"no", xsaveopt_enabled?"xsaveopt":""));
BX_INFO((" AES support: %s", aes_enabled?"yes":"no"));

1
bochs/param_names.h
View File

@ -49,6 +49,7 @@
#define BXPN_CPUID_STEPPING "cpuid.stepping"
#define BXPN_CPUID_MMX "cpuid.mmx"
#define BXPN_CPUID_SSE "cpuid.sse"
#define BXPN_CPUID_SSE4A "cpuid.sse4a"
#define BXPN_CPUID_AES "cpuid.aes"
#define BXPN_CPUID_MOVBE "cpuid.movbe"
#define BXPN_CPUID_SEP "cpuid.sep"