compilation w/o x86-64

This commit is contained in:
Stanislav Shwartsman 2011-09-26 19:48:58 +00:00
parent 12ad45395b
commit 0547c8823e
6 changed files with 19 additions and 18 deletions

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@ -3996,13 +3996,13 @@ public: // for now...
BX_SMF void init_VMCS(void);
BX_SMF bx_bool vmcs_field_supported(Bit32u encoding);
BX_SMF void register_vmx_state(bx_param_c *parent);
BX_SMF bx_bool is_virtual_apic_page(bx_phy_address paddr) BX_CPP_AttrRegparmN(1);
BX_SMF void VMX_Virtual_Apic_Read(bx_phy_address paddr, unsigned len, void *data);
BX_SMF void VMX_Virtual_Apic_Write(bx_phy_address paddr, unsigned len, void *data);
#if BX_SUPPORT_VMX >= 2
BX_SMF Bit16u VMX_Get_Current_VPID(void);
#endif
#if BX_SUPPORT_X86_64
BX_SMF bx_bool is_virtual_apic_page(bx_phy_address paddr) BX_CPP_AttrRegparmN(1);
BX_SMF void VMX_Virtual_Apic_Read(bx_phy_address paddr, unsigned len, void *data);
BX_SMF void VMX_Virtual_Apic_Write(bx_phy_address paddr, unsigned len, void *data);
BX_SMF Bit32u VMX_Read_VTPR(void);
BX_SMF void VMX_Write_VTPR(Bit8u vtpr);
#endif
@ -4020,8 +4020,8 @@ public: // for now...
BX_SMF void VMexit_INVLPG(bxInstruction_c *i, bx_address laddr) BX_CPP_AttrRegparmN(2);
BX_SMF void VMexit_RDTSC(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF void VMexit_RDPMC(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
#if BX_SUPPORT_VMX >= 2
BX_SMF void VMexit_WBINVD(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
#if BX_SUPPORT_VMX >= 2
BX_SMF void VMexit_PreemptionTimerExpired(void);
#endif
BX_SMF bx_bool VMexit_CLTS(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);

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@ -1740,7 +1740,7 @@ void BX_CPU_C::access_read_linear(bx_address laddr, unsigned len, unsigned curr_
void BX_CPU_C::access_write_physical(bx_phy_address paddr, unsigned len, void *data)
{
#if BX_SUPPORT_VMX
#if BX_SUPPORT_VMX && BX_SUPPORT_X86_64
if (is_virtual_apic_page(paddr)) {
VMX_Virtual_Apic_Write(paddr, len, data);
return;
@ -1759,7 +1759,7 @@ void BX_CPU_C::access_write_physical(bx_phy_address paddr, unsigned len, void *d
void BX_CPU_C::access_read_physical(bx_phy_address paddr, unsigned len, void *data)
{
#if BX_SUPPORT_VMX
#if BX_SUPPORT_VMX && BX_SUPPORT_X86_64
if (is_virtual_apic_page(paddr)) {
VMX_Virtual_Apic_Read(paddr, len, data);
return;
@ -1778,7 +1778,7 @@ void BX_CPU_C::access_read_physical(bx_phy_address paddr, unsigned len, void *da
bx_hostpageaddr_t BX_CPU_C::getHostMemAddr(bx_phy_address ppf, unsigned rw)
{
#if BX_SUPPORT_VMX
#if BX_SUPPORT_VMX && BX_SUPPORT_X86_64
if (is_virtual_apic_page(ppf))
return 0; // Do not allow direct access to virtual apic page
#endif

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@ -227,11 +227,11 @@ bx_bool BX_CPU_C::vmcs_field_supported(Bit32u encoding)
return BX_SUPPORT_VMX_EXTENSION(BX_VMX_TPR_SHADOW);
else
return 0;
#endif
case VMCS_64BIT_CONTROL_APIC_ACCESS_ADDR:
case VMCS_64BIT_CONTROL_APIC_ACCESS_ADDR_HI:
return BX_SUPPORT_VMX_EXTENSION(BX_VMX_APIC_VIRTUALIZATION);
#endif
#if BX_SUPPORT_VMX >= 2
case VMCS_64BIT_CONTROL_EPTPTR:
@ -457,14 +457,14 @@ void BX_CPU_C::init_vmx_capabilities(void)
// secondary proc based vm exec controls
// -----------------------------------------------------------
// [00] Apic Virtualization
// [01] EPT Enable
// [00] Apic Virtualization (require x86-64 for TPR shadow)
// [01] EPT Enable (require x86-64 for 4-level page walk)
// [02] Descriptor Table Exiting
// [03] RDTSCP Exiting (require RDTSCP instruction support)
// [04] Virtualize X2APIC Mode (doesn't require actual X2APIC to be enabled)
// [05] VPID Enable
// [06] WBINVD Exiting
// [07] Unrestricted Guest
// [07] Unrestricted Guest (require EPT)
// [08] Reserved
// [09] Reserved
// [10] PAUSE Loop Exiting
@ -472,8 +472,10 @@ void BX_CPU_C::init_vmx_capabilities(void)
cap->vmx_vmexec_ctrl2_supported_bits = 0;
#if BX_SUPPORT_X86_64
if (BX_SUPPORT_VMX_EXTENSION(BX_VMX_APIC_VIRTUALIZATION))
cap->vmx_vmexec_ctrl2_supported_bits |= VMX_VM_EXEC_CTRL3_VIRTUALIZE_APIC_ACCESSES;
#endif
#if BX_SUPPORT_VMX >= 2
if (BX_SUPPORT_VMX_EXTENSION(BX_VMX_EPT))
cap->vmx_vmexec_ctrl2_supported_bits |= VMX_VM_EXEC_CTRL3_EPT_ENABLE;

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@ -730,7 +730,6 @@ void BX_CPU_C::VMX_Write_VTPR(Bit8u vtpr)
VMexit(0, VMX_VMEXIT_TPR_THRESHOLD, 0);
}
}
#endif
// apic virtualization
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::is_virtual_apic_page(bx_phy_address paddr)
@ -789,6 +788,8 @@ void BX_CPU_C::VMX_Virtual_Apic_Write(bx_phy_address paddr, unsigned len, void *
VMexit(0, VMX_VMEXIT_APIC_ACCESS, qualification);
}
#endif
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_WBINVD(bxInstruction_c *i)
{
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);

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@ -427,7 +427,6 @@ VMX_error_code BX_CPU_C::VMenterLoadCheckVmControls(void)
}
}
}
#endif
if (vm->vmexec_ctrls3 & VMX_VM_EXEC_CTRL3_VIRTUALIZE_APIC_ACCESSES) {
vm->apic_access_page = (bx_phy_address) VMread64(VMCS_64BIT_CONTROL_APIC_ACCESS_ADDR);
@ -436,6 +435,7 @@ VMX_error_code BX_CPU_C::VMenterLoadCheckVmControls(void)
return VMXERR_VMENTRY_INVALID_VM_CONTROL_FIELD;
}
}
#endif
#if BX_SUPPORT_VMX >= 2
if (vm->vmexec_ctrls3 & VMX_VM_EXEC_CTRL3_VIRTUALIZE_X2APIC_MODE) {
@ -3141,8 +3141,8 @@ void BX_CPU_C::register_vmx_state(bx_param_c *parent)
#if BX_SUPPORT_X86_64
BXRS_HEX_PARAM_FIELD(vmexec_ctrls, virtual_apic_page_addr, BX_CPU_THIS_PTR vmcs.virtual_apic_page_addr);
BXRS_HEX_PARAM_FIELD(vmexec_ctrls, vm_tpr_threshold, BX_CPU_THIS_PTR vmcs.vm_tpr_threshold);
#endif
BXRS_HEX_PARAM_FIELD(vmexec_ctrls, apic_access_page, BX_CPU_THIS_PTR vmcs.apic_access_page);
#endif
#if BX_SUPPORT_VMX >= 2
BXRS_HEX_PARAM_FIELD(vmexec_ctrls, eptptr, BX_CPU_THIS_PTR vmcs.eptptr);
BXRS_HEX_PARAM_FIELD(vmexec_ctrls, vpid, BX_CPU_THIS_PTR vmcs.vpid);

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@ -593,9 +593,8 @@ typedef struct bx_VMCS
#if BX_SUPPORT_X86_64
bx_phy_address virtual_apic_page_addr;
Bit32u vm_tpr_threshold;
#endif
bx_phy_address apic_access_page;
#endif
#if BX_SUPPORT_VMX >= 2
Bit64u eptptr;
@ -943,8 +942,6 @@ enum VMX_Activity_State {
((((Bit64u) VMX_MSR_VMCS_ENUM_HI) << 32) | VMX_MSR_VMCS_ENUM_LO)
#if BX_SUPPORT_VMX >= 2
// IA32_VMX_MSR_PROCBASED_CTRLS2 MSR (0x48b)
// -----------------------------
@ -957,6 +954,7 @@ enum VMX_Activity_State {
#define VMX_MSR_VMX_PROCBASED_CTRLS2 \
((((Bit64u) VMX_MSR_VMX_PROCBASED_CTRLS2_HI) << 32) | VMX_MSR_VMX_PROCBASED_CTRLS2_LO)
#if BX_SUPPORT_VMX >= 2
// IA32_VMX_EPT_VPID_CAP MSR (0x48c)
// ---------------------