rename AVX handlers - match their real operands
This commit is contained in:
Stanislav Shwartsman
parent
d5973c06cf
commit
dd79431702
@ -246,7 +246,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHPD_VpdMq(bxInstruction_c *i)
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/* VUNPCKLPS: VEX. 0F 14 (VEX.W ignore) */
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/* VPUNPCKLDQ: VEX.66.0F 62 (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKLPS_VpsWpsR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKLPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -264,7 +264,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKLPS_VpsWpsR(bxInstruction_c
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/* VUNPCKHPS: VEX. 0F 15 (VEX.W ignore) */
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/* VPUNPCKHDQ: VEX.66.0F 6A (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKHPS_VpsWpsR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKHPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -283,7 +283,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKHPS_VpsWpsR(bxInstruction_c
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/* VUNPCKLPD: VEX.66.0F 14 (VEX.W ignore) */
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/* VPUNPCKLQDQ: VEX.66.0F 6C (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKLPD_VpdWpdR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKLPD_VpdHpdWpdR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -298,7 +298,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKLPD_VpdWpdR(bxInstruction_c
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/* VUNPCKLPD: VEX.66.0F 15 (VEX.W ignore) */
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/* VPUNPCKLQDQ: VEX.66.0F 6D (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKHPD_VpdWpdR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKHPD_VpdHpdWpdR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -361,7 +361,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVMSKB_GdUdq(bxInstruction_c *i
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/* VANDPS: VEX 0F 54 (VEX.W ignore) */
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/* VANDPD: VEX.66.0F 54 (VEX.W ignore) */
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/* VPAND: VEX.66.0F DB (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VANDPS_VpsWpsR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VANDPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -377,7 +377,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VANDPS_VpsWpsR(bxInstruction_c *i)
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/* VANDNPS: VEX 0F 55 (VEX.W ignore) */
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/* VANDNPD: VEX.66.0F 55 (VEX.W ignore) */
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/* VPANDN: VEX.66.0F DF (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VANDNPS_VpsWpsR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VANDNPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -393,7 +393,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VANDNPS_VpsWpsR(bxInstruction_c *i
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/* VORPS: VEX 0F 56 (VEX.W ignore) */
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/* VORPD: VEX.66.0F 56 (VEX.W ignore) */
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/* VPOR: VEX.66.0F EB (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VORPS_VpsWpsR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VORPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -409,7 +409,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VORPS_VpsWpsR(bxInstruction_c *i)
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/* VXORPS: VEX 0F 57 (VEX.W ignore) */
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/* VXORPD: VEX.66.0F 57 (VEX.W ignore) */
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/* VPXOR: VEX.66.0F EF (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VXORPS_VpsWpsR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VXORPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -423,7 +423,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VXORPS_VpsWpsR(bxInstruction_c *i)
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}
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/* Opcode: VEX.0F.C6 (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPS_VpsWpsIbR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPS_VpsHpsWpsIbR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
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@ -444,7 +444,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPS_VpsWpsIbR(bxInstruction_c
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}
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/* Opcode: VEX.66.0F.C6 (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPD_VpdWpdIbR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPD_VpdHpdWpdIbR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
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@ -542,7 +542,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBROADCASTF128_VdqMdq(bxInstructio
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}
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/* Opcode: VEX.66.0F.3A 0C (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPS_VpsWpsIbR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPS_VpsHpsWpsIbR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -559,7 +559,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPS_VpsWpsIbR(bxInstruction_c
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}
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/* Opcode: VEX.66.0F.3A 0D (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPD_VpdWpdIbR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPD_VpdHpdWpdIbR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -576,7 +576,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPD_VpdWpdIbR(bxInstruction_c
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}
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/* Opcode: VEX.66.0F.3A 4A (VEX.W=0) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPS_VpsWpsIbR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPS_VpsHpsWpsIbR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()),
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mask = BX_READ_AVX_REG(i->Ib());
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@ -592,7 +592,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPS_VpsWpsIbR(bxInstruction_
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}
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/* Opcode: VEX.66.0F.3A 4B (VEX.W=0) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPD_VpdWpdIbR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPD_VpdHpdWpdIbR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()),
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mask = BX_READ_AVX_REG(i->Ib());
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@ -608,7 +608,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPD_VpdWpdIbR(bxInstruction_
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}
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/* Opcode: VEX.66.0F.3A 4C (VEX.W=0) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDVB_VdqWdqIbR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()),
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mask = BX_READ_AVX_REG(i->Ib());
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@ -657,7 +657,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF128_WdqVdqIbR(bxInstructi
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}
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/* Opcode: VEX.66.0F.38 0C (VEX.W=0) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsWpsR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
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@ -676,7 +676,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsWpsR(bxInstruction_c
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}
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/* Opcode: VEX.66.0F.3A 05 (VEX.W=0) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdWpdR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdHpdWpdR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
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BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
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@ -759,7 +759,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERM2F128_VdqWdqIbR(bxInstruction
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}
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/* Opcode: VEX.66.0F.38 2C (VEX.W=0) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsMps(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsHpsMps(bxInstruction_c *i)
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{
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BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), result;
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unsigned len = i->getVL();
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@ -790,7 +790,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsMps(bxInstruction_c
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}
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/* Opcode: VEX.66.0F.38 2D (VEX.W=0) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdMpd(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdHpdMpd(bxInstruction_c *i)
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{
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BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), result;
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unsigned len = i->getVL();
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@ -821,7 +821,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdMpd(bxInstruction_c
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}
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/* Opcode: VEX.66.0F.38 2C (VEX.W=0) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsVps(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsHpsVps(bxInstruction_c *i)
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{
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BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), op = BX_READ_AVX_REG(i->nnn());
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unsigned len = i->getVL();
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@ -854,7 +854,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsVps(bxInstruction_c
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}
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/* Opcode: VEX.66.0F.38 2D (VEX.W=0) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_MpdVpd(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_MpdHpdVpd(bxInstruction_c *i)
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{
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BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), op = BX_READ_AVX_REG(i->nnn());
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unsigned len = i->getVL();
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@ -228,7 +228,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTPD_VpdWpdR(bxInstruction_c *i
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}
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/* Opcode: VEX.NDS.F3.0F 51 (VEX.W ignore, VEX.L ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSS_VssWssR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSS_VssHpsWssR(bxInstruction_c *i)
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{
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BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
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@ -246,7 +246,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSS_VssWssR(bxInstruction_c *i
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}
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/* Opcode: VEX.NDS.F2.0F 51 (VEX.W ignore, VEX.L ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSD_VsdWsdR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSD_VsdHpdWsdR(bxInstruction_c *i)
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{
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BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
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float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
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@ -278,7 +278,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VRSQRTPS_VpsWpsR(bxInstruction_c *
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}
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/* Opcode: VEX.NDS.F3.0F 52 (VEX.W ignore, VEX.L ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VRSQRTSS_VssWssR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VRSQRTSS_VssHpsWssR(bxInstruction_c *i)
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{
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BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
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@ -305,7 +305,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VRCPPS_VpsWpsR(bxInstruction_c *i)
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}
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/* Opcode: VEX.NDS.F3.0F 53 (VEX.W ignore, VEX.L ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VRCPSS_VssWssR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VRCPSS_VssHpsWssR(bxInstruction_c *i)
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{
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BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
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float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
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@ -318,7 +318,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VRCPSS_VssWssR(bxInstruction_c *i)
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}
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/* Opcode: VEX.NDS.0F 58 (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPS_VpsWpsR(bxInstruction_c *i)
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPS_VpsHpsWpsR(bxInstruction_c *i)
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{
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
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unsigned len = i->getVL();
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@ -344,7 +344,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPS_VpsWpsR(bxInstruction_c *i)
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}
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/* Opcode: VEX.NDS.66.0F 58 (VEX.W ignore) */
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPD_VpdWpdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPD_VpdHpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -370,7 +370,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPD_VpdWpdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F3.0F 58 (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSS_VssWssR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSS_VssHpsWssR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
@ -392,7 +392,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSS_VssWssR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F 58 (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSD_VsdWsdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSD_VsdHpdWsdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
@ -414,7 +414,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSD_VsdWsdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.0F 59 (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPS_VpsWpsR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPS_VpsHpsWpsR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -440,7 +440,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPS_VpsWpsR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.66.0F 59 (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPD_VpdWpdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPD_VpdHpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -466,7 +466,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPD_VpdWpdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F3.0F 59 (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSS_VssWssR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSS_VssHpsWssR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
@ -488,7 +488,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSS_VssWssR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F 59 (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSD_VsdWsdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSD_VsdHpdWsdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
@ -665,7 +665,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTTPS2DQ_VdqWpsR(bxInstruction_c
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.0F 5C (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPS_VpsWpsR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPS_VpsHpsWpsR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -691,7 +691,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPS_VpsWpsR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.66.0F 5C (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPD_VpdWpdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPD_VpdHpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -717,7 +717,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPD_VpdWpdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F3.0F 5C (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSS_VssWssR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSS_VssHpsWssR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
@ -739,7 +739,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSS_VssWssR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F 5C (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSD_VsdWsdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSD_VsdHpdWsdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
@ -761,7 +761,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSD_VsdWsdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.0F 5D (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPS_VpsWpsR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPS_VpsHpsWpsR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -788,7 +788,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPS_VpsWpsR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.66.0F 5D (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPD_VpdWpdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPD_VpdHpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -815,7 +815,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPD_VpdWpdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F3.0F 5D (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSS_VssWssR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSS_VssHpsWssR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
@ -839,7 +839,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSS_VssWssR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F 5D (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSD_VsdWsdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSD_VsdHpdWsdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
@ -863,7 +863,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSD_VsdWsdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.0F 5E (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPS_VpsWpsR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPS_VpsHpsWpsR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -889,7 +889,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPS_VpsWpsR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.66.0F 5E (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPD_VpdWpdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPD_VpdHpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -915,7 +915,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPD_VpdWpdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F3.0F 5E (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSS_VssWssR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSS_VssHpsWssR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
@ -937,7 +937,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSS_VssWssR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F 5E (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSD_VsdWsdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSD_VsdHpdWsdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
@ -959,7 +959,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSD_VsdWsdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.0F 5F (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPS_VpsWpsR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPS_VpsHpsWpsR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -986,7 +986,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPS_VpsWpsR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.66.0F 5F (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPD_VpdWpdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPD_VpdHpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -1013,7 +1013,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPD_VpdWpdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F3.0F 5F (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSS_VssWssR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSS_VssHpsWssR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
@ -1037,7 +1037,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSS_VssWssR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F 5F (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSD_VsdWsdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSD_VsdHpdWsdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
@ -1061,7 +1061,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSD_VsdWsdR(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.66.0F 7C (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPD_VpdWpdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPD_VpdHpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -1090,7 +1090,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPD_VpdWpdR(bxInstruction_c *i
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F 7C (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPS_VpsWpsR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPS_VpsHpsWpsR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -1126,7 +1126,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPS_VpsWpsR(bxInstruction_c *i
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.66.0F 7D (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPD_VpdWpdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPD_VpdHpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -1155,7 +1155,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPD_VpdWpdR(bxInstruction_c *i
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F 7D (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPS_VpsWpsR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPS_VpsHpsWpsR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -1191,7 +1191,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPS_VpsWpsR(bxInstruction_c *i
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.0F C2 (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPS_VpsWpsIbR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPS_VpsHpsWpsIbR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -1217,7 +1217,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPS_VpsWpsIbR(bxInstruction_c *
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.66.0F C2 (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPD_VpdWpdIbR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPD_VpdHpdWpdIbR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -1244,7 +1244,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPD_VpdWpdIbR(bxInstruction_c *
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F C2 (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSD_VsdWsdIbR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSD_VsdHpdWsdIbR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
@ -1272,7 +1272,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSD_VsdWsdIbR(bxInstruction_c *
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F3.0F C2 (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSS_VssWssIbR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSS_VssHpsWssIbR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
@ -1300,7 +1300,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSS_VssWssIbR(bxInstruction_c *
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F D0 (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPD_VpdWpdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPD_VpdHpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -1329,7 +1329,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPD_VpdWpdR(bxInstruction_c
|
||||
}
|
||||
|
||||
/* Opcode: VEX.NDS.F2.0F D0 (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPS_VpsWpsR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPS_VpsHpsWpsR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
@ -1534,7 +1534,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDPD_VpdWpdIbR(bxInstruction_c
|
||||
}
|
||||
|
||||
/* Opcode: VEX.66.0F.3A.0A (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDSS_VssWssIbR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDSS_VssHpsWssIbR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
@ -1562,7 +1562,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDSS_VssWssIbR(bxInstruction_c
|
||||
}
|
||||
|
||||
/* Opcode: VEX.66.0F.3A.0B (VEX.W ignore, VEX.L ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDSD_VsdWsdIbR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDSD_VsdHpdWsdIbR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
|
||||
float64 op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
@ -1590,7 +1590,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDSD_VsdWsdIbR(bxInstruction_c
|
||||
}
|
||||
|
||||
/* Opcode: VEX.66.0F.3A.40 (VEX.W ignore) */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDPPS_VpsWpsIbR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDPPS_VpsHpsWpsIbR(bxInstruction_c *i)
|
||||
{
|
||||
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
|
||||
unsigned len = i->getVL();
|
||||
|
||||
124
bochs/cpu/cpu.h
124
bochs/cpu/cpu.h
@ -2400,33 +2400,33 @@ public: // for now...
|
||||
BX_SMF BX_INSF_TYPE VMOVSHDUP_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMOVSLDUP_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMOVDDUP_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VUNPCKLPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VUNPCKHPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VUNPCKLPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VUNPCKHPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VUNPCKLPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VUNPCKHPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VUNPCKLPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VUNPCKHPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMOVMSKPS_GdVRps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMOVMSKPD_GdVRpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPMOVMSKB_GdUdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSQRTPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSQRTSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSQRTSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VHADDPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VHADDPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VHSUBPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VHSUBPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMULPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMULPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMULSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMULSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSUBPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSUBPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSUBSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSUBSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSQRTSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSQRTSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VHADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VHADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VHSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VHSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMULPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMULPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMULSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMULSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSUBSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSUBSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCVTSS2SD_VsdWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCVTSD2SS_VssWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCVTDQ2PS_VpsWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
@ -2441,62 +2441,62 @@ public: // for now...
|
||||
BX_SMF BX_INSF_TYPE VCVTSI2SS_VssEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCVTSI2SD_VsdEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCVTSI2SS_VssEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMINPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMINPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMINSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMINSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VDIVPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VDIVPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VDIVSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VDIVSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMAXPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMAXPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMAXSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMAXSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCMPPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCMPSS_VssWssIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCMPPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCMPSD_VsdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDSUBPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDSUBPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMINPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMINPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMINSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMINSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VDIVPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VDIVPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VDIVSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VDIVSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMAXPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMAXPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMAXSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMAXSD_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCMPPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCMPSS_VssHpsWssIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCMPPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCMPSD_VsdHpdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDSUBPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VADDSUBPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VROUNDPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VROUNDPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VROUNDSS_VssWssIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VROUNDSD_VsdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VDPPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VROUNDSS_VssHpsWssIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VROUNDSD_VsdHpdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VDPPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VRSQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VRSQRTSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VRSQRTSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VRCPPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VRCPSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSHUFPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSHUFPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBLENDPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBLENDPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPBLENDVB_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VRCPSS_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSHUFPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VSHUFPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBLENDPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBLENDPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPBLENDVB_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPTEST_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VTESTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VTESTPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VANDPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VANDNPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VORPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VXORPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VANDPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VANDNPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VORPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VXORPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBROADCASTSS_VpsMss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBROADCASTSD_VpdMsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBROADCASTF128_VdqMdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBLENDVPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBLENDVPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBLENDVPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VBLENDVPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VINSERTF128_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VEXTRACTF128_WdqVdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VEXTRACTF128_WdqVdqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPERMILPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPERMILPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPERMILPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPERMILPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPERMILPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPERMILPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VPERM2F128_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMASKMOVPS_VpsMps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMASKMOVPD_VpdMpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMASKMOVPS_MpsVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMASKMOVPD_MpdVpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMASKMOVPS_VpsHpsMps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMASKMOVPD_VpdHpdMpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMASKMOVPS_MpsHpsVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VMASKMOVPD_MpdHpdVpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
BX_SMF BX_INSF_TYPE VCVTPH2PS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
BX_SMF BX_INSF_TYPE VCVTPS2PH_WpsVpsIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
|
||||
|
||||
@ -110,13 +110,13 @@ static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f13M[6] = {
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f14[6] = {
|
||||
/* 66 */ { 0, BX_IA_VUNPCKLPD_VpdWpd },
|
||||
/* 66 */ { 0, BX_IA_VUNPCKLPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f15[6] = {
|
||||
/* 66 */ { 0, BX_IA_VUNPCKHPD_VpdWpd },
|
||||
/* 66 */ { 0, BX_IA_VUNPCKHPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
@ -189,56 +189,56 @@ static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f50R[6] = {
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f51[6] = {
|
||||
/* 66 */ { 0, BX_IA_VSQRTPD_VpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VSQRTSS_VssWss },
|
||||
/* F2 */ { 0, BX_IA_VSQRTSD_VsdWsd }
|
||||
/* F3 */ { 0, BX_IA_VSQRTSS_VssHpsWss },
|
||||
/* F2 */ { 0, BX_IA_VSQRTSD_VsdHpdWsd }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f52[6] = {
|
||||
/* 66 */ { 0, BX_IA_ERROR },
|
||||
/* F3 */ { 0, BX_IA_VRSQRTSS_VssWss },
|
||||
/* F3 */ { 0, BX_IA_VRSQRTSS_VssHpsWss },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f53[6] = {
|
||||
/* 66 */ { 0, BX_IA_ERROR },
|
||||
/* F3 */ { 0, BX_IA_VRCPSS_VssWss },
|
||||
/* F3 */ { 0, BX_IA_VRCPSS_VssHpsWss },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f54[6] = {
|
||||
/* 66 */ { 0, BX_IA_VANDPD_VpdWpd },
|
||||
/* 66 */ { 0, BX_IA_VANDPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f55[6] = {
|
||||
/* 66 */ { 0, BX_IA_VANDNPD_VpdWpd },
|
||||
/* 66 */ { 0, BX_IA_VANDNPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f56[6] = {
|
||||
/* 66 */ { 0, BX_IA_VORPD_VpdWpd },
|
||||
/* 66 */ { 0, BX_IA_VORPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f57[6] = {
|
||||
/* 66 */ { 0, BX_IA_VXORPD_VpdWpd },
|
||||
/* 66 */ { 0, BX_IA_VXORPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f58[6] = {
|
||||
/* 66 */ { 0, BX_IA_VADDPD_VpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VADDSS_VssWss },
|
||||
/* F2 */ { 0, BX_IA_VADDSD_VsdWsd }
|
||||
/* 66 */ { 0, BX_IA_VADDPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VADDSS_VssHpsWss },
|
||||
/* F2 */ { 0, BX_IA_VADDSD_VsdHpdWsd }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f59[6] = {
|
||||
/* 66 */ { 0, BX_IA_VMULPD_VpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VMULSS_VssWss },
|
||||
/* F2 */ { 0, BX_IA_VMULSD_VsdWsd }
|
||||
/* 66 */ { 0, BX_IA_VMULPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VMULSS_VssHpsWss },
|
||||
/* F2 */ { 0, BX_IA_VMULSD_VsdHpdWsd }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f5a[6] = {
|
||||
@ -254,27 +254,27 @@ static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f5b[6] = {
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f5c[6] = {
|
||||
/* 66 */ { 0, BX_IA_VSUBPD_VpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VSUBSS_VssWss },
|
||||
/* F2 */ { 0, BX_IA_VSUBSD_VsdWsd }
|
||||
/* 66 */ { 0, BX_IA_VSUBPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VSUBSS_VssHpsWss },
|
||||
/* F2 */ { 0, BX_IA_VSUBSD_VsdHpdWsd }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f5d[6] = {
|
||||
/* 66 */ { 0, BX_IA_VMINPD_VpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VMINSS_VssWss },
|
||||
/* F2 */ { 0, BX_IA_VMINSD_VsdWsd }
|
||||
/* 66 */ { 0, BX_IA_VMINPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VMINSS_VssHpsWss },
|
||||
/* F2 */ { 0, BX_IA_VMINSD_VsdHpdWsd }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f5e[6] = {
|
||||
/* 66 */ { 0, BX_IA_VDIVPD_VpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VDIVSS_VssWss },
|
||||
/* F2 */ { 0, BX_IA_VDIVSD_VsdWsd }
|
||||
/* 66 */ { 0, BX_IA_VDIVPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VDIVSS_VssHpsWss },
|
||||
/* F2 */ { 0, BX_IA_VDIVSD_VsdHpdWsd }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f5f[6] = {
|
||||
/* 66 */ { 0, BX_IA_VMAXPD_VpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VMAXSS_VssWss },
|
||||
/* F2 */ { 0, BX_IA_VMAXSD_VsdWsd }
|
||||
/* 66 */ { 0, BX_IA_VMAXPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_VMAXSS_VssHpsWss },
|
||||
/* F2 */ { 0, BX_IA_VMAXSD_VsdHpdWsd }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f6f[6] = {
|
||||
@ -290,15 +290,15 @@ static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f70[6] = {
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f7c[6] = {
|
||||
/* 66 */ { 0, BX_IA_VHADDPD_VpdWpd },
|
||||
/* 66 */ { 0, BX_IA_VHADDPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_VHADDPS_VpsWps }
|
||||
/* F2 */ { 0, BX_IA_VHADDPS_VpsHpsWps }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f7d[6] = {
|
||||
/* 66 */ { 0, BX_IA_VHSUBPD_VpdWpd },
|
||||
/* 66 */ { 0, BX_IA_VHSUBPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_VHSUBPS_VpsWps }
|
||||
/* F2 */ { 0, BX_IA_VHSUBPS_VpsHpsWps }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f7e[6] = {
|
||||
@ -314,21 +314,21 @@ static const BxOpcodeInfo_t BxOpcodeGroupAVX_0f7f[6] = {
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0fc2[6] = {
|
||||
/* 66 */ { 0, BX_IA_VCMPPD_VpdWpdIb },
|
||||
/* F3 */ { 0, BX_IA_VCMPSS_VssWssIb },
|
||||
/* F2 */ { 0, BX_IA_VCMPSD_VsdWsdIb }
|
||||
/* 66 */ { 0, BX_IA_VCMPPD_VpdHpdWpdIb },
|
||||
/* F3 */ { 0, BX_IA_VCMPSS_VssHpsWssIb },
|
||||
/* F2 */ { 0, BX_IA_VCMPSD_VsdHpdWsdIb }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0fc6[6] = {
|
||||
/* 66 */ { 0, BX_IA_VSHUFPD_VpdWpdIb },
|
||||
/* 66 */ { 0, BX_IA_VSHUFPD_VpdHpdWpdIb },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0fd0[6] = {
|
||||
/* 66 */ { 0, BX_IA_VADDSUBPD_VpdWpd },
|
||||
/* 66 */ { 0, BX_IA_VADDSUBPD_VpdHpdWpd },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_VADDSUBPS_VpsWps }
|
||||
/* F2 */ { 0, BX_IA_VADDSUBPS_VpsHpsWps }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupAVX_0fe6[6] = {
|
||||
@ -421,8 +421,8 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3] = {
|
||||
/* 11 */ { BxPrefixSSE | BxArithDstRM, BX_IA_VMOVUPS_WpsVps, BxOpcodeGroupAVX_0f11 },
|
||||
/* 12 */ { BxPrefixSSE, BX_IA_VMOVLPS_VpsMq, BxOpcodeGroupAVX_0f12 },
|
||||
/* 13 */ { BxPrefixSSE, BX_IA_VMOVLPS_MqVps, BxOpcodeGroupAVX_0f13M },
|
||||
/* 14 */ { BxPrefixSSE, BX_IA_VUNPCKLPS_VpsWps, BxOpcodeGroupAVX_0f14 },
|
||||
/* 15 */ { BxPrefixSSE, BX_IA_VUNPCKHPS_VpsWps, BxOpcodeGroupAVX_0f15 },
|
||||
/* 14 */ { BxPrefixSSE, BX_IA_VUNPCKLPS_VpsHpsWps, BxOpcodeGroupAVX_0f14 },
|
||||
/* 15 */ { BxPrefixSSE, BX_IA_VUNPCKHPS_VpsHpsWps, BxOpcodeGroupAVX_0f15 },
|
||||
/* 16 */ { BxPrefixSSE, BX_IA_VMOVHPS_VpsMq, BxOpcodeGroupAVX_0f16 },
|
||||
/* 17 */ { BxPrefixSSE, BX_IA_VMOVHPS_MqVps, BxOpcodeGroupAVX_0f17M },
|
||||
/* 18 */ { 0, BX_IA_ERROR },
|
||||
@ -485,18 +485,18 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3] = {
|
||||
/* 51 */ { BxPrefixSSE, BX_IA_VSQRTPS_VpsWps, BxOpcodeGroupAVX_0f51 },
|
||||
/* 52 */ { BxPrefixSSE, BX_IA_VRSQRTPS_VpsWps, BxOpcodeGroupAVX_0f52 },
|
||||
/* 53 */ { BxPrefixSSE, BX_IA_VRCPPS_VpsWps, BxOpcodeGroupAVX_0f53 },
|
||||
/* 54 */ { BxPrefixSSE, BX_IA_VANDPS_VpsWps, BxOpcodeGroupAVX_0f54 },
|
||||
/* 55 */ { BxPrefixSSE, BX_IA_VANDNPS_VpsWps, BxOpcodeGroupAVX_0f55 },
|
||||
/* 56 */ { BxPrefixSSE, BX_IA_VORPS_VpsWps, BxOpcodeGroupAVX_0f56 },
|
||||
/* 57 */ { BxPrefixSSE, BX_IA_VXORPS_VpsWps, BxOpcodeGroupAVX_0f57 },
|
||||
/* 58 */ { BxPrefixSSE, BX_IA_VADDPS_VpsWps, BxOpcodeGroupAVX_0f58 },
|
||||
/* 59 */ { BxPrefixSSE, BX_IA_VMULPS_VpsWps, BxOpcodeGroupAVX_0f59 },
|
||||
/* 54 */ { BxPrefixSSE, BX_IA_VANDPS_VpsHpsWps, BxOpcodeGroupAVX_0f54 },
|
||||
/* 55 */ { BxPrefixSSE, BX_IA_VANDNPS_VpsHpsWps, BxOpcodeGroupAVX_0f55 },
|
||||
/* 56 */ { BxPrefixSSE, BX_IA_VORPS_VpsHpsWps, BxOpcodeGroupAVX_0f56 },
|
||||
/* 57 */ { BxPrefixSSE, BX_IA_VXORPS_VpsHpsWps, BxOpcodeGroupAVX_0f57 },
|
||||
/* 58 */ { BxPrefixSSE, BX_IA_VADDPS_VpsHpsWps, BxOpcodeGroupAVX_0f58 },
|
||||
/* 59 */ { BxPrefixSSE, BX_IA_VMULPS_VpsHpsWps, BxOpcodeGroupAVX_0f59 },
|
||||
/* 5A */ { BxPrefixSSE, BX_IA_VCVTPS2PD_VpdWps, BxOpcodeGroupAVX_0f5a },
|
||||
/* 5B */ { BxPrefixSSE, BX_IA_VCVTDQ2PS_VpsWdq, BxOpcodeGroupAVX_0f5b },
|
||||
/* 5C */ { BxPrefixSSE, BX_IA_VSUBPS_VpsWps, BxOpcodeGroupAVX_0f5c },
|
||||
/* 5D */ { BxPrefixSSE, BX_IA_VMINPS_VpsWps, BxOpcodeGroupAVX_0f5d },
|
||||
/* 5E */ { BxPrefixSSE, BX_IA_VDIVPS_VpsWps, BxOpcodeGroupAVX_0f5e },
|
||||
/* 5F */ { BxPrefixSSE, BX_IA_VMAXPS_VpsWps, BxOpcodeGroupAVX_0f5f },
|
||||
/* 5C */ { BxPrefixSSE, BX_IA_VSUBPS_VpsHpsWps, BxOpcodeGroupAVX_0f5c },
|
||||
/* 5D */ { BxPrefixSSE, BX_IA_VMINPS_VpsHpsWps, BxOpcodeGroupAVX_0f5d },
|
||||
/* 5E */ { BxPrefixSSE, BX_IA_VDIVPS_VpsHpsWps, BxOpcodeGroupAVX_0f5e },
|
||||
/* 5F */ { BxPrefixSSE, BX_IA_VMAXPS_VpsHpsWps, BxOpcodeGroupAVX_0f5f },
|
||||
/* 60 */ { BxPrefixSSE66, BX_IA_VPUNPCKLBW_VdqWdq },
|
||||
/* 61 */ { BxPrefixSSE66, BX_IA_VPUNPCKLWD_VdqWdq },
|
||||
/* 62 */ { BxPrefixSSE66, BX_IA_VPUNPCKLDQ_VdqWdq },
|
||||
@ -595,11 +595,11 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3] = {
|
||||
/* BF */ { 0, BX_IA_ERROR },
|
||||
/* C0 */ { 0, BX_IA_ERROR },
|
||||
/* C1 */ { 0, BX_IA_ERROR },
|
||||
/* C2 */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_VCMPPS_VpsWpsIb, BxOpcodeGroupAVX_0fc2 },
|
||||
/* C2 */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_VCMPPS_VpsHpsWpsIb, BxOpcodeGroupAVX_0fc2 },
|
||||
/* C3 */ { 0, BX_IA_ERROR },
|
||||
/* C4 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VPINSRW_VdqEwIb },
|
||||
/* C5 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VPEXTRW_GdUdqIb },
|
||||
/* C6 */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_VSHUFPS_VpsWpsIb, BxOpcodeGroupAVX_0fc6 },
|
||||
/* C6 */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_VSHUFPS_VpsHpsWpsIb, BxOpcodeGroupAVX_0fc6 },
|
||||
/* C7 */ { 0, BX_IA_ERROR },
|
||||
/* C8 */ { 0, BX_IA_ERROR },
|
||||
/* C9 */ { 0, BX_IA_ERROR },
|
||||
@ -671,8 +671,8 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3] = {
|
||||
/* 09 */ { BxPrefixSSE66, BX_IA_VPSIGNW_VdqWdq },
|
||||
/* 0A */ { BxPrefixSSE66, BX_IA_VPSIGND_VdqWdq },
|
||||
/* 0B */ { BxPrefixSSE66, BX_IA_VPMULHRSW_VdqWdq },
|
||||
/* 0C */ { BxPrefixSSE66 | BxVexW0, BX_IA_VPERMILPS_VpsWps },
|
||||
/* 0D */ { BxPrefixSSE66 | BxVexW0, BX_IA_VPERMILPD_VpdWpd },
|
||||
/* 0C */ { BxPrefixSSE66 | BxVexW0, BX_IA_VPERMILPS_VpsHpsWps },
|
||||
/* 0D */ { BxPrefixSSE66 | BxVexW0, BX_IA_VPERMILPD_VpdHpdWpd },
|
||||
/* 0E */ { BxPrefixSSE66 | BxVexW0, BX_IA_VTESTPS_VpsWps },
|
||||
/* 0F */ { BxPrefixSSE66 | BxVexW0, BX_IA_VTESTPD_VpdWpd },
|
||||
/* 10 */ { 0, BX_IA_ERROR },
|
||||
@ -703,10 +703,10 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3] = {
|
||||
/* 29 */ { BxPrefixSSE66, BX_IA_VPCMPEQQ_VdqWdq },
|
||||
/* 2A */ { BxPrefixSSE66, BX_IA_VMOVNTDQA_VdqMdq },
|
||||
/* 2B */ { BxPrefixSSE66, BX_IA_VPACKUSDW_VdqWdq },
|
||||
/* 2C */ { BxPrefixSSE66 | BxVexW0, BX_IA_VMASKMOVPS_VpsMps },
|
||||
/* 2D */ { BxPrefixSSE66 | BxVexW0, BX_IA_VMASKMOVPD_VpdMpd },
|
||||
/* 2E */ { BxPrefixSSE66 | BxVexW0, BX_IA_VMASKMOVPS_MpsVps },
|
||||
/* 2F */ { BxPrefixSSE66 | BxVexW0, BX_IA_VMASKMOVPD_MpdVpd },
|
||||
/* 2C */ { BxPrefixSSE66 | BxVexW0, BX_IA_VMASKMOVPS_VpsHpsMps },
|
||||
/* 2D */ { BxPrefixSSE66 | BxVexW0, BX_IA_VMASKMOVPD_VpdHpdMpd },
|
||||
/* 2E */ { BxPrefixSSE66 | BxVexW0, BX_IA_VMASKMOVPS_MpsHpsVps },
|
||||
/* 2F */ { BxPrefixSSE66 | BxVexW0, BX_IA_VMASKMOVPD_MpdHpdVpd },
|
||||
/* 30 */ { BxPrefixSSE66, BX_IA_VPMOVZXBW_VdqWq },
|
||||
/* 31 */ { BxPrefixSSE66, BX_IA_VPMOVZXBD_VdqWd },
|
||||
/* 32 */ { BxPrefixSSE66, BX_IA_VPMOVZXBQ_VdqWw },
|
||||
@ -927,10 +927,10 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3] = {
|
||||
/* 07 */ { 0, BX_IA_ERROR },
|
||||
/* 08 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VROUNDPS_VpsWpsIb },
|
||||
/* 09 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VROUNDPD_VpdWpdIb },
|
||||
/* 0A */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VROUNDSS_VssWssIb },
|
||||
/* 0B */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VROUNDSD_VsdWsdIb },
|
||||
/* 0C */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VBLENDPS_VpsWpsIb },
|
||||
/* 0D */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VBLENDPD_VpdWpdIb },
|
||||
/* 0A */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VROUNDSS_VssHpsWssIb },
|
||||
/* 0B */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VROUNDSD_VsdHpdWsdIb },
|
||||
/* 0C */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VBLENDPS_VpsHpsWpsIb },
|
||||
/* 0D */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VBLENDPD_VpdHpdWpdIb },
|
||||
/* 0E */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VPBLENDW_VdqWdqIb },
|
||||
/* 0F */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VPALIGNR_VdqWdqIb },
|
||||
/* 10 */ { 0, BX_IA_ERROR },
|
||||
@ -981,8 +981,8 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3] = {
|
||||
/* 3D */ { 0, BX_IA_ERROR },
|
||||
/* 3E */ { 0, BX_IA_ERROR },
|
||||
/* 3F */ { 0, BX_IA_ERROR },
|
||||
/* 40 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VDPPS_VpsWpsIb },
|
||||
/* 41 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VDPPD_VpdWpdIb },
|
||||
/* 40 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VDPPS_VpsHpsWpsIb },
|
||||
/* 41 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VDPPD_VpdHpdWpdIb },
|
||||
/* 42 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VMPSADBW_VdqWdqIb },
|
||||
/* 43 */ { 0, BX_IA_ERROR },
|
||||
/* 44 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_VPCLMULQDQ_VdqWdqIb },
|
||||
@ -991,9 +991,9 @@ static const BxOpcodeInfo_t BxOpcodeTableAVX[256*3] = {
|
||||
/* 47 */ { 0, BX_IA_ERROR },
|
||||
/* 48 */ { 0, BX_IA_ERROR },
|
||||
/* 49 */ { 0, BX_IA_ERROR },
|
||||
/* 4A */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_VBLENDVPS_VpsWpsIb },
|
||||
/* 4B */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_VBLENDVPD_VpdWpdIb },
|
||||
/* 4C */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_VPBLENDVB_VdqWdqIb },
|
||||
/* 4A */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_VBLENDVPS_VpsHpsWpsIb },
|
||||
/* 4B */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_VBLENDVPD_VpdHpdWpdIb },
|
||||
/* 4C */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib4, BX_IA_VPBLENDVB_VdqHdqWdqIb },
|
||||
/* 4D */ { 0, BX_IA_ERROR },
|
||||
/* 4E */ { 0, BX_IA_ERROR },
|
||||
/* 4F */ { 0, BX_IA_ERROR },
|
||||
|
||||
@ -1367,24 +1367,36 @@ bx_define_opcode(BX_IA_GETSEC, &BX_CPU_C::GETSEC, &BX_CPU_C::GETSEC, BX_CPU_SMX,
|
||||
|
||||
// AVX
|
||||
#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
|
||||
bx_define_opcode(BX_IA_VZEROUPPER, NULL, &BX_CPU_C::VZEROUPPER, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVAPS_VpsWps, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVAPS_WpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVAPD_WpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVUPS_WpsVps, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVUPD_VpdWpd, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVUPD_WpdVpd, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVDQA_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVDQU_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVDQA_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVDQU_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVSD_VsdWsd, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::VMOVSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVSS_VssWss, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::VMOVSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVSD_WsdVsd, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::VMOVSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVSS_WssVss, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::VMOVSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVLPD_VpdMq, &BX_CPU_C::VMOVLPD_VpdMq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVLPD_MqVsd, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVHPD_VpdMq, &BX_CPU_C::VMOVHPD_VpdMq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVHPD_MqVsd, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVNTPS_MpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVNTPD_MpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVNTDQ_MdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VUNPCKLPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VUNPCKHPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVHPD_VpdMq, &BX_CPU_C::VMOVHPD_VpdMq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVHPD_MqVsd, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVAPD_WpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVNTPD_MpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VUNPCKLPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VUCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCOMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
@ -1392,20 +1404,20 @@ bx_define_opcode(BX_IA_VMOVMSKPS_GdVRps, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKP
|
||||
bx_define_opcode(BX_IA_VMOVMSKPD_GdVRpd, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPD_GdVRpd, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSQRTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSQRTSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VRSQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRSQRTSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSQRTSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VRSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRSQRTSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VRSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRSQRTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VRCPSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRCPSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VRCPSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRCPSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VRCPPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRCPPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VANDPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VANDPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VANDNPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VANDNPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VORPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VORPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VXORPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VXORPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VANDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VANDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VANDNPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VANDNPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VXORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VXORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPD2DQ_VqWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCVTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2DQ_VqWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCVTDQ2PD_VpdWq, &BX_CPU_C::LOAD_VectorQ, &BX_CPU_C::VCVTDQ2PD_VpdWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
@ -1415,50 +1427,47 @@ bx_define_opcode(BX_IA_VCVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2
|
||||
bx_define_opcode(BX_IA_VCVTDQ2PS_VpsWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTDQ2PS_VpsWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPS2DQ_VdqWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCVTTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPS2DQ_VdqWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMULPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMULPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMULSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMULSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSUBPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSUBPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSUBSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSUBSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VDIVPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VDIVPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VDIVSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VDIVSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMAXPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMAXPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMAXSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMAXSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMINPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMINPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMINSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMINSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVDQA_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVDQU_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMULPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMULPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMULSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMULSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSUBSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSUBSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VDIVPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VDIVPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VDIVSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VDIVSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMAXPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMAXPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMAXSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMAXSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMINPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMINPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMINSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMINSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSHUFHW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSHUFLW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VHADDPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VHADDPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VHSUBPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VHSUBPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VHADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VHADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VHSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VHSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVQ_WqVq, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::MOVQ_VqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVDQA_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVDQU_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VCMPPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCMPPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCMPSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCMPSD_VsdWsdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCMPSS_VssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCMPSS_VssWssIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSHUFPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDSUBPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDSUBPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCMPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCMPPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCMPSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCMPSD_VsdHpdWsdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCMPSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCMPSS_VssHpsWssIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSHUFPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VSHUFPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VADDSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPSRLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPSRAW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPSLLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
@ -1471,22 +1480,17 @@ bx_define_opcode(BX_IA_VPSLLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLQ_UdqI
|
||||
bx_define_opcode(BX_IA_VPSLLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLDQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VLDMXCSR, &BX_CPU_C::LDMXCSR, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VSTMXCSR, &BX_CPU_C::STMXCSR, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVUPS_WpsVps, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVLPS_VpsMq, &BX_CPU_C::VMOVLPD_VpdMq, &BX_CPU_C::VMOVHLPS_VpsWps, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVHPS_VpsMq, &BX_CPU_C::VMOVHPD_VpdMq, &BX_CPU_C::VMOVLHPS_VpsWps, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVLPS_MqVps, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVHPS_MqVps, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VUNPCKLPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VUNPCKHPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVAPS_VpsWps, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMOVAPS_WpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
|
||||
bx_define_opcode(BX_IA_VMOVNTPS_MpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VUNPCKLPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VUNPCKHPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCOMISS_VpsWps, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VCVTPS2PD_VpdWps, &BX_CPU_C::LOAD_VectorQ, &BX_CPU_C::VCVTPS2PD_VpdWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPUNPCKHDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPUNPCKLDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPUNPCKHDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPUNPCKLDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPACKSSWB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKSSWB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPCMPGTB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPGTB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPCMPGTW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPGTW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
@ -1498,16 +1502,14 @@ bx_define_opcode(BX_IA_VPUNPCKLWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPC
|
||||
bx_define_opcode(BX_IA_VPUNPCKHBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPCKHBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPUNPCKHWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPCKHWD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPACKUSDW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKUSDW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPUNPCKLQDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPUNPCKHQDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPUNPCKLQDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPUNPCKHQDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPCMPEQB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPCMPEQW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPCMPEQD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPCMPEQQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VZEROUPPER, NULL, &BX_CPU_C::VZEROUPPER, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::PINSRW_VdqEwIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VSHUFPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPSRLW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPSRLD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPSRLQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
@ -1522,15 +1524,14 @@ bx_define_opcode(BX_IA_VPSRAW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAW_Vdq
|
||||
bx_define_opcode(BX_IA_VPSRAD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPMULHUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULHUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPMULHW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULHW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMOVNTDQ_MdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPSUBSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPSUBSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPADDSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPADDSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPANDN_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPAND_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPOR_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPXOR_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPANDN_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPAND_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPOR_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
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||||
bx_define_opcode(BX_IA_VPXOR_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
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||||
bx_define_opcode(BX_IA_VLDDQU_VdqMdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
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||||
bx_define_opcode(BX_IA_VPSLLW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
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||||
bx_define_opcode(BX_IA_VPSLLD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
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||||
@ -1569,12 +1570,11 @@ bx_define_opcode(BX_IA_VPABSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PABSB_Vdq
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bx_define_opcode(BX_IA_VPABSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PABSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
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||||
bx_define_opcode(BX_IA_VPABSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PABSD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
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||||
bx_define_opcode(BX_IA_VPMULDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULDQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
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||||
bx_define_opcode(BX_IA_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
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||||
bx_define_opcode(BX_IA_VPACKSSDW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKSSDW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
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||||
bx_define_opcode(BX_IA_VMASKMOVPS_VpsMps, &BX_CPU_C::VMASKMOVPS_VpsMps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
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||||
bx_define_opcode(BX_IA_VMASKMOVPD_VpdMpd, &BX_CPU_C::VMASKMOVPD_VpdMpd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMASKMOVPS_MpsVps, &BX_CPU_C::VMASKMOVPS_MpsVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMASKMOVPD_MpdVpd, &BX_CPU_C::VMASKMOVPD_MpdVpd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMASKMOVPS_VpsHpsMps, &BX_CPU_C::VMASKMOVPS_VpsHpsMps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
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||||
bx_define_opcode(BX_IA_VMASKMOVPS_MpsHpsVps, &BX_CPU_C::VMASKMOVPS_MpsHpsVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPMOVSXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXBW_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXBD_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPMOVSXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVSXBQ_VdqWwR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
@ -1601,17 +1601,17 @@ bx_define_opcode(BX_IA_VPMAXUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXUW_V
|
||||
bx_define_opcode(BX_IA_VPMAXUD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXUD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPMULLD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULLD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPHMINPOSUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPERMILPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPERMILPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPERMILPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPERMILPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPERMILPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPERMILPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPERM2F128_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VROUNDPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VROUNDSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VROUNDSD_VsdWsdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VROUNDSS_VssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VROUNDSS_VssWssIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VBLENDPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VBLENDPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VROUNDSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VROUNDSD_VsdHpdWsdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VROUNDSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VROUNDSS_VssHpsWssIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VBLENDPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VBLENDPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPBLENDW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PBLENDW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPALIGNR_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PALIGNR_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, &BX_CPU_C::PEXTRB_EbdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
@ -1621,12 +1621,12 @@ bx_define_opcode(BX_IA_VINSERTF128_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VI
|
||||
bx_define_opcode(BX_IA_VEXTRACTF128_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqEbIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsWssIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VDPPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDPPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VDPPD_VpdWpdIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::DPPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VDPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDPPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VDPPD_VpdHpdWpdIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::DPPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::MPSADBW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VBLENDVPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VBLENDVPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPBLENDVB_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDVB_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VBLENDVPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VBLENDVPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
|
||||
bx_define_opcode(BX_IA_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPCMPESTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
bx_define_opcode(BX_IA_VPCMPISTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user