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support more than 32-bit cpu features vector

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This commit is contained in:
Stanislav Shwartsman 2011-09-14 20:22:24 +00:00
parent 3f230d115e
commit e2f0880f1c
32 changed files with 136 additions and 134 deletions
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2
bochs/cpu/cpu.h
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@ -813,7 +813,7 @@ public: // for now...
bx_cpuid_t *cpuid;
#endif
Bit32u isa_extensions_bitmask;
Bit64u isa_extensions_bitmask;
Bit32u cpu_extensions_bitmask;
#define BX_CPUID_SUPPORT_ISA_EXTENSION(feature) \

2
bochs/cpu/cpudb/amd_k6_2_chomper.cc
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@ -72,7 +72,7 @@ void amd_k6_2_chomper_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpu
}
}
Bit32u amd_k6_2_chomper_t::get_isa_extensions_bitmask(void) const
Bit64u amd_k6_2_chomper_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/amd_k6_2_chomper.h
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@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "amd_k6_2_chomper"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/athlon64_clawhammer.cc
View File

@ -78,7 +78,7 @@ void athlon64_clawhammer_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction,
}
}
Bit32u athlon64_clawhammer_t::get_isa_extensions_bitmask(void) const
Bit64u athlon64_clawhammer_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/athlon64_clawhammer.h
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@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "athlon64_clawhammer"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/atom_n270.cc
View File

@ -107,7 +107,7 @@ void atom_n270_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_func
}
}
Bit32u atom_n270_t::get_isa_extensions_bitmask(void) const
Bit64u atom_n270_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/atom_n270.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "atom_n270"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/core2_extreme_x9770.cc
View File

@ -107,7 +107,7 @@ void core2_extreme_x9770_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction,
}
}
Bit32u core2_extreme_x9770_t::get_isa_extensions_bitmask(void) const
Bit64u core2_extreme_x9770_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/core2_extreme_x9770.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "core2_extreme_x9770"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/core2_penryn_t9600.cc
View File

@ -114,7 +114,7 @@ void core2_penryn_t9600_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, c
}
}
Bit32u core2_penryn_t9600_t::get_isa_extensions_bitmask(void) const
Bit64u core2_penryn_t9600_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/core2_penryn_t9600.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "core2_penryn_t9600"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/core_duo_t2400_yonah.cc
View File

@ -107,7 +107,7 @@ void core_duo_t2400_yonah_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction,
}
}
Bit32u core_duo_t2400_yonah_t::get_isa_extensions_bitmask(void) const
Bit64u core_duo_t2400_yonah_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/core_duo_t2400_yonah.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "core_duo_t2400_yonah"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc
View File

@ -121,7 +121,7 @@ void corei7_sandy_bridge_2600k_t::get_cpuid_leaf(Bit32u function, Bit32u subfunc
}
}
Bit32u corei7_sandy_bridge_2600k_t::get_isa_extensions_bitmask(void) const
Bit64u corei7_sandy_bridge_2600k_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/corei7_sandy_bridge_2600K.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "corei7_sandy_bridge_2600k"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/p2_klamath.cc
View File

@ -53,7 +53,7 @@ void p2_klamath_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_fun
}
}
Bit32u p2_klamath_t::get_isa_extensions_bitmask(void) const
Bit64u p2_klamath_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/p2_klamath.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "p2_klamath"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/p3_katmai.cc
View File

@ -56,7 +56,7 @@ void p3_katmai_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_func
}
}
Bit32u p3_katmai_t::get_isa_extensions_bitmask(void) const
Bit64u p3_katmai_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/p3_katmai.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "p3_katmai"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/p4_prescott_celeron_336.cc
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@ -84,7 +84,7 @@ void p4_prescott_celeron_336_t::get_cpuid_leaf(Bit32u function, Bit32u subfuncti
}
}
Bit32u p4_prescott_celeron_336_t::get_isa_extensions_bitmask(void) const
Bit64u p4_prescott_celeron_336_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/p4_prescott_celeron_336.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "p4_prescott_celeron_336"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/p4_willamette.cc
View File

@ -69,7 +69,7 @@ void p4_willamette_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_
}
}
Bit32u p4_willamette_t::get_isa_extensions_bitmask(void) const
Bit64u p4_willamette_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/p4_willamette.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "p4_willamette"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

2
bochs/cpu/cpudb/pentium_mmx.cc
View File

@ -51,7 +51,7 @@ void pentium_mmx_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_fu
}
}
Bit32u pentium_mmx_t::get_isa_extensions_bitmask(void) const
Bit64u pentium_mmx_t::get_isa_extensions_bitmask(void) const
{
return BX_CPU_X87 |
BX_CPU_486 |

2
bochs/cpu/cpudb/pentium_mmx.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "pentium_mmx"; }
virtual Bit32u get_isa_extensions_bitmask(void) const;
virtual Bit64u get_isa_extensions_bitmask(void) const;
virtual Bit32u get_cpu_extensions_bitmask(void) const;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;

101
bochs/cpu/cpuid.h
View File

@ -39,7 +39,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return NULL; }
virtual Bit32u get_isa_extensions_bitmask(void) const = 0;
virtual Bit64u get_isa_extensions_bitmask(void) const = 0;
virtual Bit32u get_cpu_extensions_bitmask(void) const = 0;
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const = 0;
@ -66,57 +66,58 @@ protected:
typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// cpuid ISA (duplicated in disasm.h)
#define BX_CPU_X87 (1 << 0) /* FPU (X87) instruction */
#define BX_CPU_486 (1 << 1) /* 486 new instruction */
#define BX_CPU_PENTIUM (1 << 2) /* Pentium new instruction */
#define BX_CPU_P6 (1 << 3) /* P6 new instruction */
#define BX_CPU_MMX (1 << 4) /* MMX instruction */
#define BX_CPU_3DNOW (1 << 5) /* 3DNow! instruction */
#define BX_CPU_SYSCALL_SYSRET (1 << 6) /* SYSCALL/SYSRET in legacy mode */
#define BX_CPU_SYSENTER_SYSEXIT (1 << 7) /* SYSENTER/SYSEXIT instruction */
#define BX_CPU_CLFLUSH (1 << 8) /* CLFLUSH instruction */
#define BX_CPU_SSE (1 << 9) /* SSE instruction */
#define BX_CPU_SSE2 (1 << 10) /* SSE2 instruction */
#define BX_CPU_SSE3 (1 << 11) /* SSE3 instruction */
#define BX_CPU_SSSE3 (1 << 12) /* SSSE3 instruction */
#define BX_CPU_SSE4_1 (1 << 13) /* SSE4_1 instruction */
#define BX_CPU_SSE4_2 (1 << 14) /* SSE4_2 instruction */
#define BX_CPU_MONITOR_MWAIT (1 << 15) /* MONITOR/MWAIT instruction */
#define BX_CPU_VMX (1 << 16) /* VMX instruction */
#define BX_CPU_SMX (1 << 17) /* SMX instruction */
#define BX_CPU_LM_LAHF_SAHF (1 << 18) /* Long Mode LAHF/SAHF instruction */
#define BX_CPU_RDTSCP (1 << 19) /* RDTSCP instruction */
#define BX_CPU_XSAVE (1 << 20) /* XSAVE/XRSTOR extensions instruction */
#define BX_CPU_XSAVEOPT (1 << 21) /* XSAVEOPT instruction */
#define BX_CPU_AES_PCLMULQDQ (1 << 22) /* AES+PCLMULQDQ instruction */
#define BX_CPU_MOVBE (1 << 23) /* MOVBE Intel Atom(R) instruction */
#define BX_CPU_FSGSBASE (1 << 24) /* FS/GS BASE access instruction */
#define BX_CPU_INVPCID (1 << 25) /* INVPCID instruction */
#define BX_CPU_AVX (1 << 26) /* AVX instruction */
#define BX_CPU_AVX2 (1 << 27) /* AVX2 instruction */
#define BX_CPU_AVX_F16C (1 << 28) /* AVX F16 convert instruction */
#define BX_CPU_AVX_FMA (1 << 29) /* AVX FMA instruction */
#define BX_CPU_BMI1 (1 << 30) /* BMI1 instruction */
#define BX_CPU_BMI2 (1 << 31) /* BMI2 instruction */
#define BX_CPU_X87 (BX_CONST64(1) << 0) /* FPU (X87) instruction */
#define BX_CPU_486 (BX_CONST64(1) << 1) /* 486 new instruction */
#define BX_CPU_PENTIUM (BX_CONST64(1) << 2) /* Pentium new instruction */
#define BX_CPU_P6 (BX_CONST64(1) << 3) /* P6 new instruction */
#define BX_CPU_MMX (BX_CONST64(1) << 4) /* MMX instruction */
#define BX_CPU_3DNOW (BX_CONST64(1) << 5) /* 3DNow! instruction */
#define BX_CPU_SYSCALL_SYSRET (BX_CONST64(1) << 6) /* SYSCALL/SYSRET in legacy mode */
#define BX_CPU_SYSENTER_SYSEXIT (BX_CONST64(1) << 7) /* SYSENTER/SYSEXIT instruction */
#define BX_CPU_CLFLUSH (BX_CONST64(1) << 8) /* CLFLUSH instruction */
#define BX_CPU_SSE (BX_CONST64(1) << 9) /* SSE instruction */
#define BX_CPU_SSE2 (BX_CONST64(1) << 10) /* SSE2 instruction */
#define BX_CPU_SSE3 (BX_CONST64(1) << 11) /* SSE3 instruction */
#define BX_CPU_SSSE3 (BX_CONST64(1) << 12) /* SSSE3 instruction */
#define BX_CPU_SSE4_1 (BX_CONST64(1) << 13) /* SSE4_1 instruction */
#define BX_CPU_SSE4_2 (BX_CONST64(1) << 14) /* SSE4_2 instruction */
#define BX_CPU_MONITOR_MWAIT (BX_CONST64(1) << 15) /* MONITOR/MWAIT instruction */
#define BX_CPU_VMX (BX_CONST64(1) << 16) /* VMX instruction */
#define BX_CPU_SMX (BX_CONST64(1) << 17) /* SMX instruction */
#define BX_CPU_LM_LAHF_SAHF (BX_CONST64(1) << 18) /* Long Mode LAHF/SAHF instruction */
#define BX_CPU_RDTSCP (BX_CONST64(1) << 19) /* RDTSCP instruction */
#define BX_CPU_XSAVE (BX_CONST64(1) << 20) /* XSAVE/XRSTOR extensions instruction */
#define BX_CPU_XSAVEOPT (BX_CONST64(1) << 21) /* XSAVEOPT instruction */
#define BX_CPU_AES_PCLMULQDQ (BX_CONST64(1) << 22) /* AES+PCLMULQDQ instruction */
#define BX_CPU_MOVBE (BX_CONST64(1) << 23) /* MOVBE Intel Atom(R) instruction */
#define BX_CPU_FSGSBASE (BX_CONST64(1) << 24) /* FS/GS BASE access instruction */
#define BX_CPU_INVPCID (BX_CONST64(1) << 25) /* INVPCID instruction */
#define BX_CPU_AVX (BX_CONST64(1) << 26) /* AVX instruction */
#define BX_CPU_AVX2 (BX_CONST64(1) << 27) /* AVX2 instruction */
#define BX_CPU_AVX_F16C (BX_CONST64(1) << 28) /* AVX F16 convert instruction */
#define BX_CPU_AVX_FMA (BX_CONST64(1) << 29) /* AVX FMA instruction */
#define BX_CPU_LZCNT (BX_CONST64(1) << 30) /* LZCNT instruction */
#define BX_CPU_BMI1 (BX_CONST64(1) << 31) /* BMI1 instruction */
#define BX_CPU_BMI2 (BX_CONST64(1) << 32) /* BMI2 instruction */
// cpuid non-ISA features
#define BX_CPU_DEBUG_EXTENSIONS (1 << 0) /* Debug Extensions support */
#define BX_CPU_VME (1 << 1) /* VME support */
#define BX_CPU_PSE (1 << 2) /* PSE support */
#define BX_CPU_PAE (1 << 3) /* PAE support */
#define BX_CPU_PGE (1 << 4) /* Global Pages support */
#define BX_CPU_PSE36 (1 << 5) /* PSE-36 support */
#define BX_CPU_MTRR (1 << 6) /* MTRR support */
#define BX_CPU_PAT (1 << 7) /* PAT support */
#define BX_CPU_XAPIC (1 << 8) /* XAPIC support */
#define BX_CPU_X2APIC (1 << 9) /* X2APIC support */
#define BX_CPU_NX (1 << 10) /* Non-Execute support */
#define BX_CPU_LONG_MODE (1 << 11) /* Long Mode (x86-64) support */
#define BX_CPU_1G_PAGES (1 << 12) /* 1Gb pages support */
#define BX_CPU_PCID (1 << 13) /* PCID pages support */
#define BX_CPU_SMEP (1 << 14) /* SMEP support */
#define BX_CPU_FFXSR (1 << 15) /* EFER.FFXSR support */
#define BX_CPU_ALT_MOV_CR8 (1 << 16) /* LOCK CR0 access CR8 */
#define BX_CPU_DEBUG_EXTENSIONS (1 << 0) /* Debug Extensions support */
#define BX_CPU_VME (1 << 1) /* VME support */
#define BX_CPU_PSE (1 << 2) /* PSE support */
#define BX_CPU_PAE (1 << 3) /* PAE support */
#define BX_CPU_PGE (1 << 4) /* Global Pages support */
#define BX_CPU_PSE36 (1 << 5) /* PSE-36 support */
#define BX_CPU_MTRR (1 << 6) /* MTRR support */
#define BX_CPU_PAT (1 << 7) /* PAT support */
#define BX_CPU_XAPIC (1 << 8) /* XAPIC support */
#define BX_CPU_X2APIC (1 << 9) /* X2APIC support */
#define BX_CPU_NX (1 << 10) /* No-Execute support */
#define BX_CPU_LONG_MODE (1 << 11) /* Long Mode (x86-64) support */
#define BX_CPU_1G_PAGES (1 << 12) /* 1Gb pages support */
#define BX_CPU_PCID (1 << 13) /* PCID pages support */
#define BX_CPU_SMEP (1 << 14) /* SMEP support */
#define BX_CPU_FFXSR (1 << 15) /* EFER.FFXSR support */
#define BX_CPU_ALT_MOV_CR8 (1 << 16) /* LOCK CR0 access CR8 */
// CPUID defines - STD features CPUID[0x00000001].EDX
// ----------------------------

34
bochs/cpu/fetchdecode.cc
View File

@ -1958,14 +1958,14 @@ const char *get_bx_opcode_name(Bit16u ia_opcode)
void BX_CPU_C::init_FetchDecodeTables(void)
{
static Bit32u BxOpcodeFeatures[BX_IA_LAST] =
static Bit64u BxOpcodeFeatures[BX_IA_LAST] =
{
#define bx_define_opcode(a, b, c, d, e) d,
#include "ia_opcodes.h"
};
#undef bx_define_opcode
Bit32u features = BX_CPU_THIS_PTR isa_extensions_bitmask;
Bit64u features = BX_CPU_THIS_PTR isa_extensions_bitmask;
#if BX_CPU_LEVEL > 3
if (! features)
BX_PANIC(("init_FetchDecodeTables: CPU features bitmask is empty !"));
@ -1975,29 +1975,29 @@ void BX_CPU_C::init_FetchDecodeTables(void)
BX_PANIC(("init_FetchDecodeTables: too many opcodes defined !"));
for (unsigned n=0; n < BX_IA_LAST; n++) {
Bit32u ia_opcode_features = BxOpcodeFeatures[n];
if (ia_opcode_features) {
if ((ia_opcode_features & features) == 0) {
BxOpcodesTable[n].execute1 = &BX_CPU_C::BxError;
BxOpcodesTable[n].execute2 = &BX_CPU_C::BxError;
// won't allow this new #UD opcode to check prepare_SSE and similar
BxOpcodesTable[n].flags = 0;
}
Bit64u ia_opcode_features = BxOpcodeFeatures[n];
if (ia_opcode_features && (ia_opcode_features & features) == 0) {
BxOpcodesTable[n].execute1 = &BX_CPU_C::BxError;
BxOpcodesTable[n].execute2 = &BX_CPU_C::BxError;
// won't allow this new #UD opcode to check prepare_SSE and similar
BxOpcodesTable[n].flags = 0;
}
}
// handle special case - BSF/BSR vs TZCNT/LZCNT
if (! BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_BMI1)) {
BxOpcodesTable[BX_IA_TZCNT_GwEw] = BxOpcodesTable[BX_IA_BSF_GwEw];
BxOpcodesTable[BX_IA_TZCNT_GdEd] = BxOpcodesTable[BX_IA_BSF_GdEd];
#if BX_SUPPORT_X86_64
BxOpcodesTable[BX_IA_TZCNT_GqEq] = BxOpcodesTable[BX_IA_BSF_GqEq];
#endif
if (! BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_LZCNT)) {
BxOpcodesTable[BX_IA_LZCNT_GwEw] = BxOpcodesTable[BX_IA_BSR_GwEw];
BxOpcodesTable[BX_IA_LZCNT_GdEd] = BxOpcodesTable[BX_IA_BSR_GdEd];
#if BX_SUPPORT_X86_64
BxOpcodesTable[BX_IA_LZCNT_GqEq] = BxOpcodesTable[BX_IA_BSR_GqEq];
#endif
}
if (! BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_BMI1)) {
BxOpcodesTable[BX_IA_TZCNT_GwEw] = BxOpcodesTable[BX_IA_BSF_GwEw];
BxOpcodesTable[BX_IA_TZCNT_GdEd] = BxOpcodesTable[BX_IA_BSF_GdEd];
#if BX_SUPPORT_X86_64
BxOpcodesTable[BX_IA_TZCNT_GqEq] = BxOpcodesTable[BX_IA_BSF_GqEq];
#endif
}
}

2
bochs/cpu/generic_cpuid.cc
View File

@ -614,7 +614,7 @@ void bx_generic_cpuid_t::get_ext_cpuid_leaf_8(cpuid_function_t *leaf) const
void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
{
Bit32u features_bitmask = 0;
Bit64u features_bitmask = 0;
#if BX_SUPPORT_FPU
features_bitmask |= BX_CPU_X87;

4
bochs/cpu/generic_cpuid.h
View File

@ -36,7 +36,7 @@ public:
// return CPU name
virtual const char *get_name(void) const { return "bochs"; }
virtual Bit32u get_isa_extensions_bitmask(void) const { return isa_extensions_bitmask; }
virtual Bit64u get_isa_extensions_bitmask(void) const { return isa_extensions_bitmask; }
virtual Bit32u get_cpu_extensions_bitmask(void) const { return cpu_extensions_bitmask; }
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;
@ -47,7 +47,7 @@ private:
void init_isa_extensions_bitmask(void);
void init_cpu_extensions_bitmask(void);
Bit32u isa_extensions_bitmask;
Bit64u isa_extensions_bitmask;
Bit32u cpu_extensions_bitmask;
#if BX_SUPPORT_SMP

6
bochs/cpu/ia_opcodes.h
View File

@ -1874,8 +1874,8 @@ bx_define_opcode(BX_IA_TZCNT_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::TZCNT_GdEdR, B
bx_define_opcode(BX_IA_TZCNT_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::TZCNT_GqEqR, BX_CPU_BMI1, 0)
#endif
bx_define_opcode(BX_IA_LZCNT_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::LZCNT_GwEwR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_LZCNT_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::LZCNT_GdEdR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_LZCNT_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::LZCNT_GwEwR, BX_CPU_LZCNT, 0)
bx_define_opcode(BX_IA_LZCNT_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::LZCNT_GdEdR, BX_CPU_LZCNT, 0)
#if BX_SUPPORT_X86_64
bx_define_opcode(BX_IA_LZCNT_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::LZCNT_GqEqR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_LZCNT_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::LZCNT_GqEqR, BX_CPU_LZCNT, 0)
#endif

67
bochs/disasm/disasm.h
View File

@ -39,38 +39,39 @@
}
/* Instruction set attributes (duplicated in cpu.h) */
#define IA_X87 (1 << 0) /* FPU (X87) instruction */
#define IA_486 (1 << 1) /* 486 new instruction */
#define IA_PENTIUM (1 << 2) /* Pentium new instruction */
#define IA_P6 (1 << 3) /* P6 new instruction */
#define IA_MMX (1 << 4) /* MMX instruction */
#define IA_3DNOW (1 << 5) /* 3DNow! instruction */
#define IA_SYSCALL_SYSRET (1 << 6) /* SYSCALL/SYSRET in legacy mode */
#define IA_SYSENTER_SYSEXIT (1 << 7) /* SYSENTER/SYSEXIT instruction */
#define IA_CLFLUSH (1 << 8) /* CLFLUSH instruction */
#define IA_SSE (1 << 9) /* SSE instruction */
#define IA_SSE2 (1 << 10) /* SSE2 instruction */
#define IA_SSE3 (1 << 11) /* SSE3 instruction */
#define IA_SSSE3 (1 << 12) /* SSSE3 instruction */
#define IA_SSE4_1 (1 << 13) /* SSE4_1 instruction */
#define IA_SSE4_2 (1 << 14) /* SSE4_2 instruction */
#define IA_MONITOR_MWAIT (1 << 15) /* MONITOR/MWAIT instruction */
#define IA_VMX (1 << 16) /* VMX instruction */
#define IA_SMX (1 << 17) /* SMX instruction */
#define IA_LM_LAHF_SAHF (1 << 18) /* Long Mode LAHF/SAHF instruction */
#define IA_RDTSCP (1 << 19) /* RDTSCP instruction */
#define IA_XSAVE (1 << 20) /* XSAVE/XRSTOR extensions instruction */
#define IA_XSAVEOPT (1 << 21) /* XSAVEOPT instruction */
#define IA_AES_PCLMULQDQ (1 << 22) /* AES+PCLMULQDQ instruction */
#define IA_MOVBE (1 << 23) /* MOVBE Intel Atom(R) instruction */
#define IA_FSGSBASE (1 << 24) /* FS/GS BASE access instruction */
#define IA_INVPCID (1 << 25) /* INVPCID instruction */
#define IA_AVX (1 << 26) /* AVX instruction */
#define IA_AVX2 (1 << 27) /* AVX2 instruction */
#define IA_AVX_F16C (1 << 28) /* AVX F16 convert instruction */
#define IA_AVX_FMA (1 << 29) /* AVX FMA instruction */
#define IA_BMI1 (1 << 30) /* BMI1 instruction */
#define IA_BMI2 (1 << 31) /* BMI2 instruction */
#define IA_X87 (BX_CONST64(1) << 0) /* FPU (X87) instruction */
#define IA_486 (BX_CONST64(1) << 1) /* 486 new instruction */
#define IA_PENTIUM (BX_CONST64(1) << 2) /* Pentium new instruction */
#define IA_P6 (BX_CONST64(1) << 3) /* P6 new instruction */
#define IA_MMX (BX_CONST64(1) << 4) /* MMX instruction */
#define IA_3DNOW (BX_CONST64(1) << 5) /* 3DNow! instruction */
#define IA_SYSCALL_SYSRET (BX_CONST64(1) << 6) /* SYSCALL/SYSRET in legacy mode */
#define IA_SYSENTER_SYSEXIT (BX_CONST64(1) << 7) /* SYSENTER/SYSEXIT instruction */
#define IA_CLFLUSH (BX_CONST64(1) << 8) /* CLFLUSH instruction */
#define IA_SSE (BX_CONST64(1) << 9) /* SSE instruction */
#define IA_SSE2 (BX_CONST64(1) << 10) /* SSE2 instruction */
#define IA_SSE3 (BX_CONST64(1) << 11) /* SSE3 instruction */
#define IA_SSSE3 (BX_CONST64(1) << 12) /* SSSE3 instruction */
#define IA_SSE4_1 (BX_CONST64(1) << 13) /* SSE4_1 instruction */
#define IA_SSE4_2 (BX_CONST64(1) << 14) /* SSE4_2 instruction */
#define IA_MONITOR_MWAIT (BX_CONST64(1) << 15) /* MONITOR/MWAIT instruction */
#define IA_VMX (BX_CONST64(1) << 16) /* VMX instruction */
#define IA_SMX (BX_CONST64(1) << 17) /* SMX instruction */
#define IA_LM_LAHF_SAHF (BX_CONST64(1) << 18) /* Long Mode LAHF/SAHF instruction */
#define IA_RDTSCP (BX_CONST64(1) << 19) /* RDTSCP instruction */
#define IA_XSAVE (BX_CONST64(1) << 20) /* XSAVE/XRSTOR extensions instruction */
#define IA_XSAVEOPT (BX_CONST64(1) << 21) /* XSAVEOPT instruction */
#define IA_AES_PCLMULQDQ (BX_CONST64(1) << 22) /* AES+PCLMULQDQ instruction */
#define IA_MOVBE (BX_CONST64(1) << 23) /* MOVBE Intel Atom(R) instruction */
#define IA_FSGSBASE (BX_CONST64(1) << 24) /* FS/GS BASE access instruction */
#define IA_INVPCID (BX_CONST64(1) << 25) /* INVPCID instruction */
#define IA_AVX (BX_CONST64(1) << 26) /* AVX instruction */
#define IA_AVX2 (BX_CONST64(1) << 27) /* AVX2 instruction */
#define IA_AVX_F16C (BX_CONST64(1) << 28) /* AVX F16 convert instruction */
#define IA_AVX_FMA (BX_CONST64(1) << 29) /* AVX FMA instruction */
#define IA_LZCNT (BX_CONST64(1) << 30) /* LZCNT instruction */
#define IA_BMI1 (BX_CONST64(1) << 31) /* BMI1 instruction */
#define IA_BMI2 (BX_CONST64(1) << 32) /* BMI2 instruction */
/* general purpose bit register */
enum {
@ -110,7 +111,7 @@ struct BxDisasmOpcodeInfo_t
BxDisasmPtr_t Operand2;
BxDisasmPtr_t Operand3;
BxDisasmPtr_t Operand4;
Bit32u Attr;
Bit64u Feature;
};
struct BxDisasmOpcodeTable_t

6
bochs/disasm/opcodes.inc
View File

@ -588,9 +588,9 @@ Ia_lssl_Gd_Mp = { "lss", "lssl", Gd, Mp, XX, XX, 0 },
Ia_lssq_Gq_Mp = { "lss", "lssq", Gq, Mp, XX, XX, 0 },
Ia_lssw_Gw_Mp = { "lss", "lssw", Gw, Mp, XX, XX, 0 },
Ia_ltr = { "ltr", "ltr", Ew, XX, XX, XX, 0 },
Ia_lzcntl_Gd_Ed = { "lzcntl", "lzcntl", Gd, Ed, XX, XX, IA_BMI1 },
Ia_lzcntq_Gq_Eq = { "lzcntq", "lzcntq", Gq, Eq, XX, XX, IA_BMI1 },
Ia_lzcntw_Gw_Ew = { "lzcntw", "lzcntw", Gw, Ew, XX, XX, IA_BMI1 },
Ia_lzcntl_Gd_Ed = { "lzcntl", "lzcntl", Gd, Ed, XX, XX, IA_LZCNT },
Ia_lzcntq_Gq_Eq = { "lzcntq", "lzcntq", Gq, Eq, XX, XX, IA_LZCNT },
Ia_lzcntw_Gw_Ew = { "lzcntw", "lzcntw", Gw, Ew, XX, XX, IA_LZCNT },
Ia_maskmovdqu_Vdq_Udq = { "maskmovdqu", "maskmovdqu", Vdq, Udq, sYdq, XX, IA_SSE2 },
Ia_maskmovq_Pq_Nq = { "maskmovq", "maskmovq", Pq, Nq, sYq, XX, IA_3DNOW | IA_SSE },
Ia_maxpd_Vpd_Wpd = { "maxpd", "maxpd", Vpd, Wpd, XX, XX, IA_SSE2 },