fixing xsave/xrstor flows with AVX
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1c0a257b16
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@ -53,8 +53,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XSAVE(bxInstruction_c *i)
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Bit64u header1 = read_virtual_qword(i->seg(), (eaddr + 512) & asize_mask);
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Bit32u features_save_enable_mask = BX_CPU_THIS_PTR xcr0.get32() & EAX;
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/////////////////////////////////////////////////////////////////////////////
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if (BX_CPU_THIS_PTR xcr0.get_FPU() && (EAX & BX_XCR0_FPU_MASK) != 0)
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if ((features_save_enable_mask & BX_XCR0_FPU_MASK) != 0)
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{
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xmm.xmm16u(0) = BX_CPU_THIS_PTR the_i387.get_control_word();
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xmm.xmm16u(1) = BX_CPU_THIS_PTR the_i387.get_status_word();
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@ -125,11 +127,16 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XSAVE(bxInstruction_c *i)
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}
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/////////////////////////////////////////////////////////////////////////////
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if (BX_CPU_THIS_PTR xcr0.get_SSE() && (EAX & BX_XCR0_SSE_MASK) != 0)
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if ((features_save_enable_mask & (BX_XCR0_SSE_MASK | BX_XCR0_AVX_MASK)) != 0)
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{
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// store MXCSR
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write_virtual_dword(i->seg(), (eaddr + 24) & asize_mask, BX_MXCSR_REGISTER);
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write_virtual_dword(i->seg(), (eaddr + 28) & asize_mask, MXCSR_MASK);
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}
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/////////////////////////////////////////////////////////////////////////////
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if ((features_save_enable_mask & BX_XCR0_SSE_MASK) != 0)
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{
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/* store XMM register file */
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for(index=0; index < BX_XMM_REGISTERS; index++)
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{
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@ -145,7 +152,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XSAVE(bxInstruction_c *i)
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#if BX_SUPPORT_AVX
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/////////////////////////////////////////////////////////////////////////////
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if (BX_CPU_THIS_PTR xcr0.get_AVX() && (EAX & BX_XCR0_AVX_MASK) != 0)
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if ((features_save_enable_mask & BX_XCR0_AVX_MASK) != 0)
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{
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/* store AVX state */
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for(index=0; index < BX_XMM_REGISTERS; index++)
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@ -153,7 +160,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XSAVE(bxInstruction_c *i)
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// save YMM8-YMM15 only in 64-bit mode
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if (index < 8 || long64_mode()) {
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write_virtual_dqword(i->seg(),
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(eaddr+index*16+576) & asize_mask, (Bit8u *)(&BX_READ_AVX_REG_LINE(index, 1)));
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(eaddr+index*16+576) & asize_mask, (Bit8u *)(&BX_READ_AVX_REG_LINE(index, 1)));
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}
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}
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@ -207,8 +214,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XRSTOR(bxInstruction_c *i)
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// We will go feature-by-feature and not run over all XCR0 bits
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//
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Bit32u features_load_enable_mask = BX_CPU_THIS_PTR xcr0.get32() & EAX;
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/////////////////////////////////////////////////////////////////////////////
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if (BX_CPU_THIS_PTR xcr0.get_FPU() && (EAX & BX_XCR0_FPU_MASK) != 0)
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if ((features_load_enable_mask & BX_XCR0_FPU_MASK) != 0)
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{
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if (header1 & BX_XCR0_FPU_MASK) {
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// load FPU state from XSAVE area
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@ -292,16 +301,20 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XRSTOR(bxInstruction_c *i)
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}
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}
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static BxPackedXmmRegister xmmnil; /* compiler will clear the variable */
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/////////////////////////////////////////////////////////////////////////////
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if (BX_CPU_THIS_PTR xcr0.get_SSE() && (EAX & BX_XCR0_SSE_MASK) != 0)
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if ((features_load_enable_mask & (BX_XCR0_SSE_MASK | BX_XCR0_AVX_MASK)) != 0)
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{
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Bit32u new_mxcsr = read_virtual_dword(i->seg(), (eaddr + 24) & asize_mask);
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if(new_mxcsr & ~MXCSR_MASK)
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exception(BX_GP_EXCEPTION, 0);
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BX_MXCSR_REGISTER = new_mxcsr;
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}
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static BxPackedXmmRegister xmmnil; /* compiler will clear the variable */
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/////////////////////////////////////////////////////////////////////////////
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if ((features_load_enable_mask & BX_XCR0_SSE_MASK) != 0)
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{
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if (header1 & BX_XCR0_SSE_MASK) {
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// load SSE state from XSAVE area
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for(index=0; index < BX_XMM_REGISTERS; index++)
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@ -325,7 +338,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XRSTOR(bxInstruction_c *i)
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#if BX_SUPPORT_AVX
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/////////////////////////////////////////////////////////////////////////////
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if (BX_CPU_THIS_PTR xcr0.get_AVX() && (EAX & BX_XCR0_AVX_MASK) != 0)
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if ((features_load_enable_mask & BX_XCR0_AVX_MASK) != 0)
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{
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if (header1 & BX_XCR0_AVX_MASK) {
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// load AVX state from XSAVE area
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