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make RDTSC 'end of trace' instruction - guarantee that any pair ot RDTSC/RDTSCP on same CPU do not belong to same trace (and therefore will always update time and etc) - required for Win7 Thin

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This commit is contained in:
Stanislav Shwartsman 2011-09-06 14:13:39 +00:00
parent 5a350143a5
commit e000b61cfd
3 changed files with 7 additions and 7 deletions
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4
bochs/cpu/fetchdecode.cc
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@ -505,7 +505,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 2E /w */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
/* 0F 2F /w */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
/* 0F 30 /w */ { 0, BX_IA_WRMSR },
/* 0F 31 /w */ { 0, BX_IA_RDTSC },
/* 0F 31 /w */ { BxTraceEnd, BX_IA_RDTSC }, // end trace to avoid multiple TSC samples in one cycle
/* 0F 32 /w */ { 0, BX_IA_RDMSR },
/* 0F 33 /w */ { 0, BX_IA_RDPMC },
/* 0F 34 /w */ { BxTraceEnd, BX_IA_SYSENTER },
@ -1050,7 +1050,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 2E /d */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
/* 0F 2F /d */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
/* 0F 30 /d */ { 0, BX_IA_WRMSR },
/* 0F 31 /d */ { 0, BX_IA_RDTSC },
/* 0F 31 /d */ { BxTraceEnd, BX_IA_RDTSC }, // end trace to avoid multiple TSC samples in one cycle
/* 0F 32 /d */ { 0, BX_IA_RDMSR },
/* 0F 33 /d */ { 0, BX_IA_RDPMC },
/* 0F 34 /d */ { BxTraceEnd, BX_IA_SYSENTER },

4
bochs/cpu/fetchdecode.h
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@ -443,7 +443,7 @@ static const BxOpcodeInfo_t BxOpcodeInfoG7[64+8] = {
/* 0F 01 F6 */ { BxTraceEnd, BX_IA_LMSW_Ew },
/* 0F 01 F7 */ { BxTraceEnd, BX_IA_LMSW_Ew },
/* 0F 01 F8 */ { 0, BX_IA_ERROR },
/* 0F 01 F9 */ { 0, BX_IA_RDTSCP },
/* 0F 01 F9 */ { BxTraceEnd, BX_IA_RDTSCP }, // end trace to avoid multiple TSC samples in one cycle
/* 0F 01 FA */ { 0, BX_IA_ERROR },
/* 0F 01 FB */ { 0, BX_IA_ERROR },
/* 0F 01 FC */ { 0, BX_IA_ERROR },
@ -522,7 +522,7 @@ static const BxOpcodeInfo_t BxOpcodeInfoG7q[64+8] = {
/* 0F 01 F6 */ { BxTraceEnd, BX_IA_LMSW_Ew },
/* 0F 01 F7 */ { BxTraceEnd, BX_IA_LMSW_Ew },
/* 0F 01 F8 */ { 0, BX_IA_SWAPGS },
/* 0F 01 F9 */ { 0, BX_IA_RDTSCP },
/* 0F 01 F9 */ { BxTraceEnd, BX_IA_RDTSCP }, // end trace to avoid multiple TSC samples in one cycle
/* 0F 01 FA */ { 0, BX_IA_ERROR },
/* 0F 01 FB */ { 0, BX_IA_ERROR },
/* 0F 01 FC */ { 0, BX_IA_ERROR },

6
bochs/cpu/fetchdecode64.cc
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@ -445,7 +445,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 2E /w */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
/* 0F 2F /w */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
/* 0F 30 /w */ { 0, BX_IA_WRMSR },
/* 0F 31 /w */ { 0, BX_IA_RDTSC },
/* 0F 31 /w */ { BxTraceEnd, BX_IA_RDTSC }, // end trace to avoid multiple TSC samples in one cycle
/* 0F 32 /w */ { 0, BX_IA_RDMSR },
/* 0F 33 /w */ { 0, BX_IA_RDPMC },
/* 0F 34 /w */ { BxTraceEnd, BX_IA_SYSENTER },
@ -960,7 +960,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 2E /d */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
/* 0F 2F /d */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
/* 0F 30 /d */ { 0, BX_IA_WRMSR },
/* 0F 31 /d */ { 0, BX_IA_RDTSC },
/* 0F 31 /d */ { BxTraceEnd, BX_IA_RDTSC }, // end trace to avoid multiple TSC samples in one cycle
/* 0F 32 /d */ { 0, BX_IA_RDMSR },
/* 0F 33 /d */ { 0, BX_IA_RDPMC },
/* 0F 34 /d */ { BxTraceEnd, BX_IA_SYSENTER },
@ -1475,7 +1475,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 2E /q */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
/* 0F 2F /q */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
/* 0F 30 /q */ { 0, BX_IA_WRMSR },
/* 0F 31 /q */ { 0, BX_IA_RDTSC },
/* 0F 31 /q */ { BxTraceEnd, BX_IA_RDTSC }, // end trace to avoid multiple TSC samples in one cycle
/* 0F 32 /q */ { 0, BX_IA_RDMSR },
/* 0F 33 /q */ { 0, BX_IA_RDPMC },
/* 0F 34 /q */ { BxTraceEnd, BX_IA_SYSENTER },