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- Added support for AVX and AVX2 instructions emulation, to enable configure

Browse Source 
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
This commit is contained in:
Stanislav Shwartsman 2011-08-27 13:47:16 +00:00
parent 0d15044913
commit 44241a1e56
36 changed files with 6141 additions and 4027 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
bochs/.bochsrc
View File

@ -78,7 +78,7 @@
# Bochs. The start address optional, since it can be calculated from image size.
#=======================================================================
romimage: file=$BXSHARE/BIOS-bochs-latest
#romimage: file=bios/seabios-0.5.1.bin
#romimage: file=bios/seabios-0.6.1.bin
#romimage: file=mybios.bin, address=0xfff80000 # 512k at memory top
#=======================================================================
@ -199,13 +199,17 @@ cpu: cpuid_limit_winnt=0
# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
#
# AVX:
# Select AVX instruction set support.
# Select AVX/AVX2 instruction set support.
# This option exists only if Bochs compiled with --enable-avx option.
#
# AVX_F16C:
# Select AVX float16 convert instructions support.
# This option exists only if Bochs compiled with --enable-avx option.
#
# BMI:
# Select BMI1/BMI2 instructions support.
# This option exists only if Bochs compiled with --enable-avx option.
#
# 1G_PAGES:
# Enable 1G page size support in long mode.
# This option exists only if Bochs compiled with x86-64 support.
@ -248,8 +252,8 @@ cpu: cpuid_limit_winnt=0
# STEPPING:
# Set stepping information returned by CPUID. Default stepping value is 3.
#=======================================================================
cpuid: mmx=1, sep=1, sse=sse4_2, apic=xapic, aes=1, movbe=1, xsave=1
cpuid: family=6, model=0x1a, stepping=5
#cpuid: mmx=1, sep=1, sse=sse4_2, apic=xapic, aes=1, movbe=1, xsave=1
#cpuid: family=6, model=0x1a, stepping=5
#=======================================================================
# MEMORY

8
bochs/CHANGES
View File

@ -21,11 +21,13 @@ Bochs repository moved to the SVN version control !
be enabled using .bochsrc CPUID option.
- Added support for XSAVEOPT instruction, the instruction can be enabled
using .bochsrc CPUID option.
- Added support for AVX instruction set emulation, to enable configure with
--enable-avx option.
When compiled in, AVX still has to be enabled using .bochsrc CPUID option.
- Added support for AVX and AVX2 instructions emulation, to enable configure
with --enable-avx option. When compiled in, AVX still has to be enabled
using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.
- Added emulation of AVX float16 convert instructions, the feature can be
enabled using .bochsrc CPUID option.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
- Implemented VMX preemption timer VMEXIT control (patch by Jianan Hao)
- Implemented Pause-Loop Exiting Secondary VMEXIT control
- Redefined/Updated/Fixed instrumentation callbacks.

1
bochs/PARAM_TREE.txt
View File

@ -42,6 +42,7 @@ cpuid
xsaveopt
avx
avx_f16c
bmi
apic
1g_pages
pcid

23
bochs/config.cc
View File

@ -289,7 +289,7 @@ void bx_init_options()
// cpuid subtree
#if BX_CPU_LEVEL >= 4
bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 21);
bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 22);
new bx_param_string_c(cpuid_param,
"vendor_string",
@ -377,14 +377,20 @@ void bx_init_options()
"Support for XSAVEOPT instruction",
0);
#if BX_SUPPORT_AVX
new bx_param_bool_c(cpuid_param,
new bx_param_num_c(cpu_param,
"avx", "Support for AVX instruction set",
"Support for AVX instruction set",
0, 2,
0);
new bx_param_bool_c(cpuid_param,
"avx_f16c", "Support for AVX F16 convert instructions",
"Support for AVX F16 convert instructions",
0);
new bx_param_num_c(cpuid_param,
"bmi", "Support for BMI instructions",
"Support for Bit Manipulation Instructions (BMI)",
0, 2,
0);
#endif
#if BX_SUPPORT_X86_64
new bx_param_bool_c(cpuid_param,
@ -2685,13 +2691,13 @@ static int parse_line_formatted(const char *context, int num_params, char *param
}
#if BX_SUPPORT_AVX
} else if (!strncmp(params[i], "avx=", 4)) {
if (parse_param_bool(params[i], 4, BXPN_CPUID_AVX) < 0) {
PARSE_ERR(("%s: cpuid directive malformed.", context));
}
SIM->get_param_num(BXPN_CPUID_AVX)->set(atol(&params[i][4]));
} else if (!strncmp(params[i], "avx_f16c=", 9)) {
if (parse_param_bool(params[i], 9, BXPN_CPUID_AVX_F16CVT) < 0) {
PARSE_ERR(("%s: cpuid directive malformed.", context));
}
} else if (!strncmp(params[i], "bmi=", 4)) {
SIM->get_param_num(BXPN_CPUID_BMI)->set(atol(&params[i][4]));
#endif
#if BX_SUPPORT_X86_64
} else if (!strncmp(params[i], "1g_pages=", 9)) {
@ -3981,9 +3987,10 @@ int bx_write_configuration(const char *rc, int overwrite)
SIM->get_param_bool(BXPN_CPUID_MOVBE)->get(),
SIM->get_param_bool(BXPN_CPUID_SMEP)->get());
#if BX_SUPPORT_AVX
fprintf(fp, ", avx=%d, avx_f16c=%d",
SIM->get_param_bool(BXPN_CPUID_AVX)->get(),
SIM->get_param_bool(BXPN_CPUID_AVX_F16CVT)->get());
fprintf(fp, ", avx=%d, avx_f16c=%d, bmi=%d",
SIM->get_param_num(BXPN_CPUID_AVX)->get(),
SIM->get_param_bool(BXPN_CPUID_AVX_F16CVT)->get(),
SIM->get_param_num(BXPN_CPUID_BMI)->get());
#endif
#if BX_SUPPORT_X86_64
fprintf(fp, ", 1g_pages=%d, pcid=%d, fsgsbase=%d",

43
bochs/cpu/Makefile.in
View File

@ -61,6 +61,9 @@ OBJS = \
sse_string.o \
avx.o \
avx_pfp.o \
avx2.o \
avx2_gather.o \
bmi32.o \
xsave.o \
aes.o \
vmx.o \
@ -124,7 +127,8 @@ OBJS64 = \
mult64.o \
shift64.o \
bit64.o \
stack64.o
stack64.o \
bmi64.o
BX_INCLUDES = ../bochs.h ../config.h
@ -232,6 +236,20 @@ avx.o: avx.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h descriptor.h \
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h simd_int.h
avx2.o: avx2.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../gui/siminterface.h \
../cpudb.h ../gui/paramtree.h ../memory/memory.h ../pc_system.h \
../gui/gui.h ../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h simd_int.h
avx2_gather.o: avx2_gather.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../gui/siminterface.h \
../cpudb.h ../gui/paramtree.h ../memory/memory.h ../pc_system.h \
../gui/gui.h ../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h
avx_pfp.o: avx_pfp.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../gui/siminterface.h \
@ -240,7 +258,7 @@ avx_pfp.o: avx_pfp.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h ../fpu/softfloat-compare.h ../fpu/softfloat.h \
../fpu/softfloat-specialize.h
../fpu/softfloat-specialize.h simd_pfp.h
bcd.o: bcd.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../config.h ../osdep.h ../gui/siminterface.h ../cpudb.h \
../gui/paramtree.h ../memory/memory.h ../pc_system.h ../gui/gui.h \
@ -276,6 +294,20 @@ bit64.o: bit64.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h
bmi32.o: bmi32.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../config.h ../osdep.h ../gui/siminterface.h ../cpudb.h \
../gui/paramtree.h ../memory/memory.h ../pc_system.h ../gui/gui.h \
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h descriptor.h \
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h
bmi64.o: bmi64.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../config.h ../osdep.h ../gui/siminterface.h ../cpudb.h \
../gui/paramtree.h ../memory/memory.h ../pc_system.h ../gui/gui.h \
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h descriptor.h \
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h
call_far.o: call_far.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../gui/siminterface.h \
../cpudb.h ../gui/paramtree.h ../memory/memory.h ../pc_system.h \
@ -637,14 +669,14 @@ sse.o: sse.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h descriptor.h \
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h
xmm.h vmx.h stack.h simd_int.h
sse_move.o: sse_move.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../gui/siminterface.h \
../cpudb.h ../gui/paramtree.h ../memory/memory.h ../pc_system.h \
../gui/gui.h ../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h
xmm.h vmx.h stack.h simd_int.h
sse_pfp.o: sse_pfp.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../gui/siminterface.h \
../cpudb.h ../gui/paramtree.h ../memory/memory.h ../pc_system.h \
@ -652,7 +684,7 @@ sse_pfp.o: sse_pfp.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h ../fpu/softfloat-compare.h ../fpu/softfloat.h \
../fpu/softfloat-specialize.h
../fpu/softfloat-specialize.h simd_pfp.h
sse_rcp.o: sse_rcp.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../gui/siminterface.h \
../cpudb.h ../gui/paramtree.h ../memory/memory.h ../pc_system.h \
@ -738,4 +770,3 @@ xsave.o: xsave.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h \
../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h ../fpu/control_w.h \
xmm.h vmx.h stack.h

294
bochs/cpu/avx.cc
View File

@ -28,33 +28,37 @@
#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
#include "simd_int.h"
/* VZEROUPPER: VEX.128.0F.77 (VEX.W ignore, VEX.VVV #UD) */
/* VZEROALL: VEX.256.0F.77 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VZEROUPPER(bxInstruction_c *i)
{
if (i->getVL() == BX_VL128) {
for(unsigned index=0; index < BX_XMM_REGISTERS; index++)
{
if (index < 8 || long64_mode())
BX_CLEAR_AVX_HIGH(index);
}
for(unsigned index=0; index < BX_XMM_REGISTERS; index++)
{
if (index < 8 || long64_mode())
BX_CLEAR_AVX_HIGH(index);
}
else {
// prepare empty AVX register - zeroed by compiler because of static variable
static BxPackedAvxRegister nil;
BX_NEXT_INSTR(i);
}
/* VZEROALL: VEX.256.0F.77 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VZEROALL(bxInstruction_c *i)
{
// prepare empty AVX register - zeroed by compiler because of static variable
static BxPackedAvxRegister nil;
for(unsigned index=0; index < BX_XMM_REGISTERS; index++)
{
if (index < 8 || long64_mode())
BX_WRITE_AVX_REG(index, nil);
}
for(unsigned index=0; index < BX_XMM_REGISTERS; index++)
{
if (index < 8 || long64_mode())
BX_WRITE_AVX_REG(index, nil);
}
BX_NEXT_INSTR(i);
}
/* VMOVSS: VEX.F3.0F 10 (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSS_VssWssR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSS_VssHpsWssR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->vvv());
@ -66,7 +70,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSS_VssWssR(bxInstruction_c *i)
}
/* VMOVSS: VEX.F2.0F 10 (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSD_VsdWsdR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSD_VsdHpdWsdR(bxInstruction_c *i)
{
BxPackedXmmRegister op;
@ -189,7 +193,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSHDUP_VpsWpsR(bxInstruction_c
}
/* VEX.0F 12 (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHLPS_VpsWps(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHLPS_VpsHpsWps(bxInstruction_c *i)
{
BxPackedXmmRegister op;
@ -202,7 +206,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHLPS_VpsWps(bxInstruction_c *i
}
/* VEX.66.0F 12 (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLPD_VpdMq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLPD_VpdHpdMq(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -217,7 +221,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLPD_VpdMq(bxInstruction_c *i)
}
/* VEX.0F 16 (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLHPS_VpsWps(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLHPS_VpsHpsWps(bxInstruction_c *i)
{
BxPackedXmmRegister op;
@ -230,7 +234,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLHPS_VpsWps(bxInstruction_c *i
}
/* VEX.66.0F 16 (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHPD_VpdMq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHPD_VpdHpdMq(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -244,86 +248,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHPD_VpdMq(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
/* VUNPCKLPS: VEX. 0F 14 (VEX.W ignore) */
/* VPUNPCKLDQ: VEX.66.0F 62 (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKLPS_VpsHpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++) {
op1.avx32u(n*4+3) = op2.avx32u(n*4+1);
op1.avx32u(n*4+2) = op1.avx32u(n*4+1);
op1.avx32u(n*4+1) = op2.avx32u(n*4);
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_NEXT_INSTR(i);
}
/* VUNPCKHPS: VEX. 0F 15 (VEX.W ignore) */
/* VPUNPCKHDQ: VEX.66.0F 6A (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKHPS_VpsHpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++) {
op1.avx32u(n*4+0) = op1.avx32u(n*4+2);
op1.avx32u(n*4+1) = op2.avx32u(n*4+2);
op1.avx32u(n*4+2) = op1.avx32u(n*4+3);
op1.avx32u(n*4+3) = op2.avx32u(n*4+3);
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_NEXT_INSTR(i);
}
/* VUNPCKLPD: VEX.66.0F 14 (VEX.W ignore) */
/* VPUNPCKLQDQ: VEX.66.0F 6C (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKLPD_VpdHpdWpdR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
op1.avx64u(n*2+1) = op2.avx64u(n*2);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_NEXT_INSTR(i);
}
/* VUNPCKLPD: VEX.66.0F 15 (VEX.W ignore) */
/* VPUNPCKLQDQ: VEX.66.0F 6D (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKHPD_VpdHpdWpdR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++) {
op1.avx64u(n*2) = op1.avx64u(n*2+1);
op1.avx64u(n*2+1) = op2.avx64u(n*2+1);
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_NEXT_INSTR(i);
}
/* VEX.0F 50 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVMSKPS_GdVRps(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
Bit32u val32 = 0;
Bit32u mask = 0;
for (unsigned n=0; n < (4*len); n++)
if(op.avx32u(n) & 0x80000000) val32 |= (1 << n);
for (unsigned n=0; n < len; n++)
mask |= sse_pmovmskd(&op.avx128(n)) << (4*n);
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
BX_NEXT_INSTR(i);
}
@ -333,12 +268,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVMSKPD_GdVRpd(bxInstruction_c *
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
Bit32u val32 = 0;
Bit32u mask = 0;
for (unsigned n=0; n < (2*len); n++)
if(op.avx32u(2*n+1) & 0x80000000) val32 |= (1 << n);
for (unsigned n=0; n < len; n++)
mask |= sse_pmovmskq(&op.avx128(n)) << (2*n);
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
BX_NEXT_INSTR(i);
}
@ -348,76 +283,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVMSKB_GdUdq(bxInstruction_c *i
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
Bit32u val32 = 0;
Bit32u mask = 0;
for (unsigned n=0; n < (16*len); n++)
if(op.avxubyte(n) & 0x80) val32 |= (1 << n);
for (unsigned n=0; n < len; n++)
mask |= sse_pmovmskb(&op.avx128(n)) << (16*n);
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
BX_NEXT_INSTR(i);
}
/* VANDPS: VEX 0F 54 (VEX.W ignore) */
/* VANDPD: VEX.66.0F 54 (VEX.W ignore) */
/* VPAND: VEX.66.0F DB (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VANDPS_VpsHpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n++)
op1.avx64u(n) &= op2.avx64u(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_NEXT_INSTR(i);
}
/* VANDNPS: VEX 0F 55 (VEX.W ignore) */
/* VANDNPD: VEX.66.0F 55 (VEX.W ignore) */
/* VPANDN: VEX.66.0F DF (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VANDNPS_VpsHpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n++)
op1.avx64u(n) = ~(op1.avx64u(n)) & op2.avx64u(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_NEXT_INSTR(i);
}
/* VORPS: VEX 0F 56 (VEX.W ignore) */
/* VORPD: VEX.66.0F 56 (VEX.W ignore) */
/* VPOR: VEX.66.0F EB (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VORPS_VpsHpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n++)
op1.avx64u(n) |= op2.avx64u(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_NEXT_INSTR(i);
}
/* VXORPS: VEX 0F 57 (VEX.W ignore) */
/* VXORPD: VEX.66.0F 57 (VEX.W ignore) */
/* VPXOR: VEX.66.0F EF (VEX.W ignore) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VXORPS_VpsHpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n++)
op1.avx64u(n) ^= op2.avx64u(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
BX_NEXT_INSTR(i);
}
@ -427,16 +298,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPS_VpsHpsWpsIbR(bxInstruction
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
Bit8u order = i->Ib();
for (unsigned n=0; n < (4*len); n+=4) {
result.avx32u(n) = op1.avx32u(n + ((order >> 0) & 0x3));
result.avx32u(n+1) = op1.avx32u(n + ((order >> 2) & 0x3));
result.avx32u(n+2) = op2.avx32u(n + ((order >> 4) & 0x3));
result.avx32u(n+3) = op2.avx32u(n + ((order >> 6) & 0x3));
}
for (unsigned n=0; n < len; n++)
sse_shufps(&result.avx128(n), &op1.avx128(n), &op2.avx128(n), i->Ib());
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
@ -451,10 +316,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPD_VpdHpdWpdIbR(bxInstruction
unsigned len = i->getVL();
Bit8u order = i->Ib();
for (unsigned n=0; n < (2*len); n+=2) {
result.avx64u(n) = op1.avx64u(n + ((order >> 0) & 0x1));
result.avx64u(n+1) = op2.avx64u(n + ((order >> 1) & 0x1));
for (unsigned n=0; n < len; n++) {
sse_shufpd(&result.avx128(n), &op1.avx128(n), &op2.avx128(n), order);
order >>= 2;
}
@ -490,12 +354,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBROADCASTSS_VpsMss(bxInstruction_
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u val32 = read_virtual_dword(i->seg(), eaddr);
for (unsigned n=0; n < len; n++) {
op.avx32u(n*4) = val32;
op.avx32u(n*4+1) = val32;
op.avx32u(n*4+2) = val32;
op.avx32u(n*4+3) = val32;
}
for (unsigned n=0; n < len; n++)
sse_pbroadcastd(&op.avx128(n), val32);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
@ -511,10 +371,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBROADCASTSD_VpdMsd(bxInstruction_
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit64u val64 = read_virtual_qword(i->seg(), eaddr);
for (unsigned n=0; n < len; n++) {
op.avx64u(n*2) = val64;
op.avx64u(n*2+1) = val64;
}
for (unsigned n=0; n < len; n++)
sse_pbroadcastq(&op.avx128(n), val64);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
@ -548,9 +406,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPS_VpsHpsWpsIbR(bxInstructio
unsigned len = i->getVL();
Bit8u mask = i->Ib();
for (unsigned n=0; n < (4*len); n++) {
if (mask & 0x1) op1.avx32u(n) = op2.avx32u(n);
mask >>= 1;
for (unsigned n=0; n < len; n++) {
sse_blendps(&op1.avx128(n), &op2.avx128(n), mask);
mask >>= 4;
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
@ -565,9 +423,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPD_VpdHpdWpdIbR(bxInstructio
unsigned len = i->getVL();
Bit8u mask = i->Ib();
for (unsigned n=0; n < (2*len); n++) {
if (mask & 0x1) op1.avx64u(n) = op2.avx64u(n);
mask >>= 1;
for (unsigned n=0; n < len; n++) {
sse_blendpd(&op1.avx128(n), &op2.avx128(n), mask);
mask >>= 2;
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
@ -583,8 +441,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPS_VpsHpsWpsIbR(bxInstructi
unsigned len = i->getVL();
for (unsigned n=0; n < (4*len); n++)
if (mask.avx32u(n) & 0x80000000) op1.avx32u(n) = op2.avx32u(n);
for (unsigned n=0; n < len; n++)
sse_blendvps(&op1.avx128(n), &op2.avx128(n), &mask.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
@ -599,8 +457,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPD_VpdHpdWpdIbR(bxInstructi
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n++)
if (mask.avx32u(n*2+1) & 0x80000000) op1.avx64u(n) = op2.avx64u(n);
for (unsigned n=0; n < len; n++)
sse_blendvpd(&op1.avx128(n), &op2.avx128(n), &mask.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
@ -615,8 +473,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR(bxInstructi
unsigned len = i->getVL();
for(unsigned n=0; n<(16*len); n++)
if (mask.avxubyte(n) & 0x80) op1.avxubyte(n) = op2.avxubyte(n);
for (unsigned n=0; n < len; n++)
sse_pblendvb(&op1.avx128(n), &op2.avx128(n), &mask.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
@ -624,12 +482,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR(bxInstructi
}
/* Opcode: VEX.66.0F.3A 18 (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF128_VdqWdqIbR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF128_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
op1.avx128(i->Ib() & 1) = op2;
op1.avx128(i->Ib() & 1) = BX_READ_XMM_REG(i->rm());
BX_WRITE_AVX_REG(i->nnn(), op1);
@ -663,12 +520,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsHpsWpsR(bxInstruction
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < (4*len); n+=4) {
result.avx32u(n) = op1.avx32u(n + (op2.avx32u(n) & 0x3));
result.avx32u(n+1) = op1.avx32u(n + (op2.avx32u(n+1) & 0x3));
result.avx32u(n+2) = op1.avx32u(n + (op2.avx32u(n+2) & 0x3));
result.avx32u(n+3) = op1.avx32u(n + (op2.avx32u(n+3) & 0x3));
}
for (unsigned n=0; n < len; n++)
sse_permilps(&result.avx128(n), &op1.avx128(n), &op2.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
@ -682,10 +535,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdHpdWpdR(bxInstruction
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n+=2) {
result.avx64u(n) = op1.avx64u(n + ((op2.avx32u(n*2+0) >> 1) & 0x1));
result.avx64u(n+1) = op1.avx64u(n + ((op2.avx32u(n*2+2) >> 1) & 0x1));
}
for (unsigned n=0; n < len; n++)
sse_permilpd(&result.avx128(n), &op1.avx128(n), &op2.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
@ -696,16 +547,10 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdHpdWpdR(bxInstruction
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsWpsIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
Bit8u order = i->Ib();
for (unsigned n=0; n < (4*len); n+=4) {
result.avx32u(n) = op1.avx32u(n + ((order >> 0) & 0x3));
result.avx32u(n+1) = op1.avx32u(n + ((order >> 2) & 0x3));
result.avx32u(n+2) = op1.avx32u(n + ((order >> 4) & 0x3));
result.avx32u(n+3) = op1.avx32u(n + ((order >> 6) & 0x3));
}
for (unsigned n=0; n < len; n++)
sse_shufps(&result.avx128(n), &op1.avx128(n), &op1.avx128(n), i->Ib());
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
@ -720,9 +565,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdWpdIbR(bxInstruction_
unsigned len = i->getVL();
Bit8u order = i->Ib();
for (unsigned n=0; n < (2*len); n+=2) {
result.avx64u(n) = op1.avx64u(n + ((order >> 0) & 0x1));
result.avx64u(n+1) = op1.avx64u(n + ((order >> 1) & 0x1));
for (unsigned n=0; n < len; n++) {
sse_shufpd(&result.avx128(n), &op1.avx128(n), &op1.avx128(n), order);
order >>= 2;
}
@ -732,7 +576,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdWpdIbR(bxInstruction_
}
/* Opcode: VEX.66.0F.3A 06 (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERM2F128_VdqWdqIbR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERM2F128_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;

597
bochs/cpu/avx2.cc Normal file
View File

@ -0,0 +1,597 @@
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
//
/////////////////////////////////////////////////////////////////////////
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
#include "simd_int.h"
#define AVX_2OP(HANDLER, func) \
/* AVX instruction with two src operands */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C :: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()); \
unsigned len = i->getVL(); \
\
for (unsigned n=0; n < len; n++) \
(func)(&op1.avx128(n), &op2.avx128(n)); \
\
BX_WRITE_AVX_REGZ(i->nnn(), op1, len); \
\
BX_NEXT_INSTR(i); \
}
AVX_2OP(VANDPS_VpsHpsWpsR, sse_andps)
AVX_2OP(VANDNPS_VpsHpsWpsR, sse_andnps)
AVX_2OP(VXORPS_VpsHpsWpsR, sse_xorps)
AVX_2OP(VORPS_VpsHpsWpsR, sse_orps)
AVX_2OP(VUNPCKLPS_VpsHpsWpsR, sse_unpcklps)
AVX_2OP(VUNPCKLPD_VpdHpdWpdR, sse_unpcklpd)
AVX_2OP(VUNPCKHPS_VpsHpsWpsR, sse_unpckhps)
AVX_2OP(VUNPCKHPD_VpdHpdWpdR, sse_unpckhpd)
AVX_2OP(VPADDB_VdqHdqWdqR, sse_paddb)
AVX_2OP(VPADDW_VdqHdqWdqR, sse_paddw)
AVX_2OP(VPADDD_VdqHdqWdqR, sse_paddd)
AVX_2OP(VPADDQ_VdqHdqWdqR, sse_paddq)
AVX_2OP(VPSUBB_VdqHdqWdqR, sse_psubb)
AVX_2OP(VPSUBW_VdqHdqWdqR, sse_psubw)
AVX_2OP(VPSUBD_VdqHdqWdqR, sse_psubd)
AVX_2OP(VPSUBQ_VdqHdqWdqR, sse_psubq)
AVX_2OP(VPCMPEQB_VdqHdqWdqR, sse_pcmpeqb)
AVX_2OP(VPCMPEQW_VdqHdqWdqR, sse_pcmpeqw)
AVX_2OP(VPCMPEQD_VdqHdqWdqR, sse_pcmpeqd)
AVX_2OP(VPCMPEQQ_VdqHdqWdqR, sse_pcmpeqq)
AVX_2OP(VPCMPGTB_VdqHdqWdqR, sse_pcmpgtb)
AVX_2OP(VPCMPGTW_VdqHdqWdqR, sse_pcmpgtw)
AVX_2OP(VPCMPGTD_VdqHdqWdqR, sse_pcmpgtd)
AVX_2OP(VPCMPGTQ_VdqHdqWdqR, sse_pcmpgtq)
AVX_2OP(VPMINSB_VdqHdqWdqR, sse_pminsb)
AVX_2OP(VPMINSW_VdqHdqWdqR, sse_pminsw)
AVX_2OP(VPMINSD_VdqHdqWdqR, sse_pminsd)
AVX_2OP(VPMINUB_VdqHdqWdqR, sse_pminub)
AVX_2OP(VPMINUW_VdqHdqWdqR, sse_pminuw)
AVX_2OP(VPMINUD_VdqHdqWdqR, sse_pminud)
AVX_2OP(VPMAXSB_VdqHdqWdqR, sse_pmaxsb)
AVX_2OP(VPMAXSW_VdqHdqWdqR, sse_pmaxsw)
AVX_2OP(VPMAXSD_VdqHdqWdqR, sse_pmaxsd)
AVX_2OP(VPMAXUB_VdqHdqWdqR, sse_pmaxub)
AVX_2OP(VPMAXUW_VdqHdqWdqR, sse_pmaxuw)
AVX_2OP(VPMAXUD_VdqHdqWdqR, sse_pmaxud)
AVX_2OP(VPSIGNB_VdqHdqWdqR, sse_psignb)
AVX_2OP(VPSIGNW_VdqHdqWdqR, sse_psignw)
AVX_2OP(VPSIGND_VdqHdqWdqR, sse_psignd)
AVX_2OP(VPSUBSB_VdqHdqWdqR, sse_psubsb)
AVX_2OP(VPSUBSW_VdqHdqWdqR, sse_psubsw)
AVX_2OP(VPSUBUSB_VdqHdqWdqR, sse_psubusb)
AVX_2OP(VPSUBUSW_VdqHdqWdqR, sse_psubusw)
AVX_2OP(VPADDSB_VdqHdqWdqR, sse_paddsb)
AVX_2OP(VPADDSW_VdqHdqWdqR, sse_paddsw)
AVX_2OP(VPADDUSB_VdqHdqWdqR, sse_paddusb)
AVX_2OP(VPADDUSW_VdqHdqWdqR, sse_paddusw)
AVX_2OP(VPHADDW_VdqHdqWdqR, sse_phaddw)
AVX_2OP(VPHADDD_VdqHdqWdqR, sse_phaddd)
AVX_2OP(VPHADDSW_VdqHdqWdqR, sse_phaddsw)
AVX_2OP(VPHSUBW_VdqHdqWdqR, sse_phsubw)
AVX_2OP(VPHSUBD_VdqHdqWdqR, sse_phsubd)
AVX_2OP(VPHSUBSW_VdqHdqWdqR, sse_phsubsw)
AVX_2OP(VPAVGB_VdqHdqWdqR, sse_pavgb)
AVX_2OP(VPAVGW_VdqHdqWdqR, sse_pavgw)
AVX_2OP(VPACKUSWB_VdqHdqWdqR, sse_packuswb)
AVX_2OP(VPACKSSWB_VdqHdqWdqR, sse_packsswb)
AVX_2OP(VPACKUSDW_VdqHdqWdqR, sse_packusdw)
AVX_2OP(VPACKSSDW_VdqHdqWdqR, sse_packssdw)
AVX_2OP(VPUNPCKLBW_VdqHdqWdqR, sse_punpcklbw)
AVX_2OP(VPUNPCKLWD_VdqHdqWdqR, sse_punpcklwd)
AVX_2OP(VPUNPCKHBW_VdqHdqWdqR, sse_punpckhbw)
AVX_2OP(VPUNPCKHWD_VdqHdqWdqR, sse_punpckhwd)
AVX_2OP(VPMULLD_VdqHdqWdqR, sse_pmulld)
AVX_2OP(VPMULLW_VdqHdqWdqR, sse_pmullw)
AVX_2OP(VPMULHW_VdqHdqWdqR, sse_pmulhw)
AVX_2OP(VPMULHUW_VdqHdqWdqR, sse_pmulhuw)
AVX_2OP(VPMULDQ_VdqHdqWdqR, sse_pmuldq)
AVX_2OP(VPMULUDQ_VdqHdqWdqR, sse_pmuludq)
AVX_2OP(VPMULHRSW_VdqHdqWdqR, sse_pmulhrsw)
AVX_2OP(VPMADDWD_VdqHdqWdqR, sse_pmaddwd)
AVX_2OP(VPMADDUBSW_VdqHdqWdqR, sse_pmaddubsw)
AVX_2OP(VPSADBW_VdqHdqWdqR, sse_psadbw)
AVX_2OP(VPSRAVD_VdqHdqWdqR, sse_psravd)
AVX_2OP(VPSLLVD_VdqHdqWdqR, sse_psllvd)
AVX_2OP(VPSLLVQ_VdqHdqWdqR, sse_psllvq)
AVX_2OP(VPSRLVD_VdqHdqWdqR, sse_psrlvd)
AVX_2OP(VPSRLVQ_VdqHdqWdqR, sse_psrlvq)
#define AVX_1OP(HANDLER, func) \
/* AVX instruction with single src operand */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C :: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm()); \
unsigned len = i->getVL(); \
\
for (unsigned n=0; n < len; n++) \
(func)(&op.avx128(n)); \
\
BX_WRITE_AVX_REGZ(i->nnn(), op, len); \
\
BX_NEXT_INSTR(i); \
}
AVX_1OP(VPABSB_VdqWdqR, sse_pabsb)
AVX_1OP(VPABSW_VdqWdqR, sse_pabsw)
AVX_1OP(VPABSD_VdqWdqR, sse_pabsd)
#define AVX_PSHIFT(HANDLER, func) \
/* AVX packed shift instruction */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op = BX_READ_AVX_REG(i->vvv()); \
unsigned len = i->getVL(); \
\
for (unsigned n=0; n < len; n++) \
(func)(&op.avx128(n), BX_READ_XMM_REG_LO_QWORD(i->rm())); \
\
BX_WRITE_AVX_REGZ(i->nnn(), op, len); \
\
BX_NEXT_INSTR(i); \
}
AVX_PSHIFT(VPSRLW_VdqHdqWdqR, sse_psrlw);
AVX_PSHIFT(VPSRLD_VdqHdqWdqR, sse_psrld);
AVX_PSHIFT(VPSRLQ_VdqHdqWdqR, sse_psrlq);
AVX_PSHIFT(VPSRAW_VdqHdqWdqR, sse_psraw);
AVX_PSHIFT(VPSRAD_VdqHdqWdqR, sse_psrad);
AVX_PSHIFT(VPSLLW_VdqHdqWdqR, sse_psllw);
AVX_PSHIFT(VPSLLD_VdqHdqWdqR, sse_pslld);
AVX_PSHIFT(VPSLLQ_VdqHdqWdqR, sse_psllq);
#define AVX_PSHIFT_IMM(HANDLER, func) \
/* AVX packed shift with imm8 instruction */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C:: HANDLER (bxInstruction_c *i) \
{ \
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm()); \
unsigned len = i->getVL(); \
\
for (unsigned n=0; n < len; n++) \
(func)(&op.avx128(n), i->Ib()); \
\
BX_WRITE_AVX_REGZ(i->vvv(), op, len); \
\
BX_NEXT_INSTR(i); \
}
AVX_PSHIFT_IMM(VPSRLW_UdqIb, sse_psrlw);
AVX_PSHIFT_IMM(VPSRLD_UdqIb, sse_psrld);
AVX_PSHIFT_IMM(VPSRLQ_UdqIb, sse_psrlq);
AVX_PSHIFT_IMM(VPSRAW_UdqIb, sse_psraw);
AVX_PSHIFT_IMM(VPSRAD_UdqIb, sse_psrad);
AVX_PSHIFT_IMM(VPSLLW_UdqIb, sse_psllw);
AVX_PSHIFT_IMM(VPSLLD_UdqIb, sse_pslld);
AVX_PSHIFT_IMM(VPSLLQ_UdqIb, sse_psllq);
AVX_PSHIFT_IMM(VPSRLDQ_UdqIb, sse_psrldq);
AVX_PSHIFT_IMM(VPSLLDQ_UdqIb, sse_pslldq);
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPSHUFHW_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm()), result;
Bit8u order = i->Ib();
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_pshufhw(&result.avx128(n), &op.avx128(n), order);
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPSHUFLW_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm()), result;
Bit8u order = i->Ib();
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_pshuflw(&result.avx128(n), &op.avx128(n), order);
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPSHUFB_VdqHdqWdqR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
sse_pshufb(&result.avx128(n), &op1.avx128(n), &op2.avx128(n));
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMPSADBW_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
Bit8u control = i->Ib();
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++) {
sse_mpsadbw(&result.avx128(n), &op1.avx128(n), &op2.avx128(n), control & 0x7);
control >>= 3;
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDW_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
Bit8u mask = i->Ib();
for (unsigned n=0; n < len; n++)
sse_pblendw(&op1.avx128(n), &op2.avx128(n), mask);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTB_VdqWb(bxInstruction_c *i)
{
unsigned len = i->getVL();
BxPackedAvxRegister op;
Bit8u val_8 = BX_READ_XMM_REG_LO_BYTE(i->rm());
for (unsigned n=0; n < len; n++)
sse_pbroadcastb(&op.avx128(n), val_8);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTW_VdqWw(bxInstruction_c *i)
{
unsigned len = i->getVL();
BxPackedAvxRegister op;
Bit16u val_16 = BX_READ_XMM_REG_LO_WORD(i->rm());
for (unsigned n=0; n < len; n++)
sse_pbroadcastw(&op.avx128(n), val_16);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTD_VdqWd(bxInstruction_c *i)
{
unsigned len = i->getVL();
BxPackedAvxRegister op;
Bit32u val_32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
for (unsigned n=0; n < len; n++)
sse_pbroadcastd(&op.avx128(n), val_32);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTQ_VdqWq(bxInstruction_c *i)
{
unsigned len = i->getVL();
BxPackedAvxRegister op;
Bit64u val_64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
for (unsigned n=0; n < len; n++)
sse_pbroadcastq(&op.avx128(n), val_64);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBW256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedAvxRegister result;
for (int n=0; n<16; n++)
result.avx16u(n) = (Bit8s) op.xmmsbyte(n);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBD256_VdqWqR(bxInstruction_c *i)
{
BxPackedAvxRegister result;
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
result.avx32u(0) = (Bit8s) MMXSB0(op);
result.avx32u(1) = (Bit8s) MMXSB1(op);
result.avx32u(2) = (Bit8s) MMXSB2(op);
result.avx32u(3) = (Bit8s) MMXSB3(op);
result.avx32u(4) = (Bit8s) MMXSB4(op);
result.avx32u(5) = (Bit8s) MMXSB5(op);
result.avx32u(6) = (Bit8s) MMXSB6(op);
result.avx32u(7) = (Bit8s) MMXSB7(op);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBQ256_VdqWdR(bxInstruction_c *i)
{
BxPackedAvxRegister result;
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
result.avx64u(0) = (Bit8s) (val32 & 0xFF);
result.avx64u(1) = (Bit8s) ((val32 >> 8) & 0xFF);
result.avx64u(2) = (Bit8s) ((val32 >> 16) & 0xFF);
result.avx64u(3) = (Bit8s) (val32 >> 24);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXWD256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedAvxRegister result;
result.avx32u(0) = op.xmm16s(0);
result.avx32u(1) = op.xmm16s(1);
result.avx32u(2) = op.xmm16s(2);
result.avx32u(3) = op.xmm16s(3);
result.avx32u(4) = op.xmm16s(4);
result.avx32u(5) = op.xmm16s(5);
result.avx32u(6) = op.xmm16s(6);
result.avx32u(7) = op.xmm16s(7);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXWQ256_VdqWqR(bxInstruction_c *i)
{
BxPackedAvxRegister result;
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
result.avx64u(0) = MMXSW0(op);
result.avx64u(1) = MMXSW1(op);
result.avx64u(2) = MMXSW2(op);
result.avx64u(3) = MMXSW3(op);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXDQ256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedAvxRegister result;
result.avx64u(0) = op.xmm32s(0);
result.avx64u(1) = op.xmm32s(1);
result.avx64u(2) = op.xmm32s(2);
result.avx64u(3) = op.xmm32s(3);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBW256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedAvxRegister result;
for (int n=0; n<16; n++)
result.avx16u(n) = op.xmmubyte(n);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBD256_VdqWqR(bxInstruction_c *i)
{
BxPackedAvxRegister result;
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
result.avx32u(0) = MMXUB0(op);
result.avx32u(1) = MMXUB1(op);
result.avx32u(2) = MMXUB2(op);
result.avx32u(3) = MMXUB3(op);
result.avx32u(4) = MMXUB4(op);
result.avx32u(5) = MMXUB5(op);
result.avx32u(6) = MMXUB6(op);
result.avx32u(7) = MMXUB7(op);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBQ256_VdqWdR(bxInstruction_c *i)
{
BxPackedAvxRegister result;
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->rm());
result.avx64u(0) = (Bit8u) (val32 & 0xFF);
result.avx64u(1) = (Bit8u) ((val32 >> 8) & 0xFF);
result.avx64u(2) = (Bit8u) ((val32 >> 16) & 0xFF);
result.avx64u(3) = (Bit8u) (val32 >> 24);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXWD256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedAvxRegister result;
result.avx32u(0) = op.xmm16u(0);
result.avx32u(1) = op.xmm16u(1);
result.avx32u(2) = op.xmm16u(2);
result.avx32u(3) = op.xmm16u(3);
result.avx32u(4) = op.xmm16u(4);
result.avx32u(5) = op.xmm16u(5);
result.avx32u(6) = op.xmm16u(6);
result.avx32u(7) = op.xmm16u(7);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXWQ256_VdqWqR(bxInstruction_c *i)
{
BxPackedAvxRegister result;
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
result.avx64u(0) = MMXUW0(op);
result.avx64u(1) = MMXUW1(op);
result.avx64u(2) = MMXUW2(op);
result.avx64u(3) = MMXUW3(op);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXDQ256_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
BxPackedAvxRegister result;
result.avx64u(0) = op.xmm32u(0);
result.avx64u(1) = op.xmm32u(1);
result.avx64u(2) = op.xmm32u(2);
result.avx64u(3) = op.xmm32u(3);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPALIGNR_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n<len; n++)
sse_palignr(&op2.avx128(n), &op1.avx128(n), i->Ib());
BX_WRITE_AVX_REGZ(i->nnn(), op2, i->getVL());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMD_VdqHdqWdqR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
result.avx32u(0) = op2.avx32u(op1.avx32u(0) & 0x7);
result.avx32u(1) = op2.avx32u(op1.avx32u(1) & 0x7);
result.avx32u(2) = op2.avx32u(op1.avx32u(2) & 0x7);
result.avx32u(3) = op2.avx32u(op1.avx32u(3) & 0x7);
result.avx32u(4) = op2.avx32u(op1.avx32u(4) & 0x7);
result.avx32u(5) = op2.avx32u(op1.avx32u(5) & 0x7);
result.avx32u(6) = op2.avx32u(op1.avx32u(6) & 0x7);
result.avx32u(7) = op2.avx32u(op1.avx32u(7) & 0x7);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMQ_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
Bit8u control = i->Ib();
result.avx64u(0) = op2.avx64u((control) & 0x3);
result.avx64u(1) = op2.avx64u((control >> 2) & 0x3);
result.avx64u(2) = op2.avx64u((control >> 4) & 0x3);
result.avx64u(3) = op2.avx64u((control >> 6) & 0x3);
BX_WRITE_AVX_REG(i->nnn(), result);
BX_NEXT_INSTR(i);
}
#endif

191
bochs/cpu/avx2_gather.cc Normal file
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@ -0,0 +1,191 @@
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
//
/////////////////////////////////////////////////////////////////////////
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
bx_address BX_CPP_AttrRegparmN(2) BX_CPU_C::BxResolveGatherD(bxInstruction_c *i, unsigned element)
{
Bit32s index = BX_READ_AVX_REG(i->sibIndex()).avx32s(element);
if (i->as64L())
return (BX_READ_64BIT_REG(i->sibBase()) + (((Bit64s) index) << i->sibScale()) + i->displ32s());
else
return (Bit32u) (BX_READ_32BIT_REG(i->sibBase()) + (index << i->sibScale()) + i->displ32s());
}
bx_address BX_CPP_AttrRegparmN(2) BX_CPU_C::BxResolveGatherQ(bxInstruction_c *i, unsigned element)
{
Bit64s index = BX_READ_AVX_REG(i->sibIndex()).avx64s(element);
if (i->as64L())
return (BX_READ_64BIT_REG(i->sibBase()) + (index << i->sibScale()) + i->displ32s());
else
return (Bit32u) (BX_READ_32BIT_REG(i->sibBase()) + (index << i->sibScale()) + i->displ32s());
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERDPS_VpsHps(bxInstruction_c *i)
{
if (! i->as32L()) {
BX_ERROR(("VGATHERDPS_VpsHps: Gather with 16-bit address size"));
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == BX_NIL_REGISTER) {
BX_ERROR(("VGATHERDPS_VpsHps: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == i->vvv() || i->sibIndex() == i->nnn() || i->vvv() == i->nnn()) {
BX_ERROR(("VGATHERDPS_VpsHps: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
BxPackedAvxRegister *mask = &BX_AVX_REG(i->vvv()), *dest = &BX_AVX_REG(i->nnn());
unsigned num_elements = 4 * i->getVL();
for (unsigned n=0; n < 8; n++) // index size = 32, element_size = 32, max vector size = 256
{
if (n >= num_elements) {
mask->avx32u(n) = 0;
dest->avx32u(n) = 0;
continue;
}
if (mask->avx32u(n) & 0x80000000) {
dest->avx32u(n) = read_virtual_dword(i->seg(), BxResolveGatherD(i, n));
}
mask->avx32u(n) = 0;
}
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERQPS_VpsHps(bxInstruction_c *i)
{
if (! i->as32L()) {
BX_ERROR(("VGATHERQPS_VpsHps: Gather with 16-bit address size"));
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == BX_NIL_REGISTER) {
BX_ERROR(("VGATHERQPS_VpsHps: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == i->vvv() || i->sibIndex() == i->nnn() || i->vvv() == i->nnn()) {
BX_ERROR(("VGATHERQPS_VpsHps: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
BxPackedAvxRegister *mask = &BX_AVX_REG(i->vvv()), *dest = &BX_AVX_REG(i->nnn());
unsigned num_elements = 2 * i->getVL();
for (unsigned n=0; n < 4; n++) // index size = 64, element_size = 32, max vector size = 256
{
if (n >= num_elements) {
mask->avx32u(n) = 0;
dest->avx32u(n) = 0;
continue;
}
if (mask->avx32u(n) & 0x80000000) {
dest->avx32u(n) = read_virtual_dword(i->seg(), BxResolveGatherQ(i, n));
}
mask->avx32u(n) = 0;
}
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERDPD_VpdHpd(bxInstruction_c *i)
{
if (! i->as32L()) {
BX_ERROR(("VGATHERDPD_VpdHpd: Gather with 16-bit address size"));
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == BX_NIL_REGISTER) {
BX_ERROR(("VGATHERDPD_VpdHpd: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == i->vvv() || i->sibIndex() == i->nnn() || i->vvv() == i->nnn()) {
BX_ERROR(("VGATHERDPD_VpdHpd: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
BxPackedAvxRegister *mask = &BX_AVX_REG(i->vvv()), *dest = &BX_AVX_REG(i->nnn());
unsigned num_elements = 2 * i->getVL();
for (unsigned n=0; n < 4; n++) // index size = 32, element_size = 64, max vector size = 256
{
if (n >= num_elements) {
mask->avx64u(n) = 0;
dest->avx64u(n) = 0;
continue;
}
if (mask->avx64u(n) & BX_CONST64(0x8000000000000000)) {
dest->avx64u(n) = read_virtual_qword(i->seg(), BxResolveGatherD(i, n));
}
mask->avx64u(n) = 0;
}
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERQPD_VpdHpd(bxInstruction_c *i)
{
if (! i->as32L()) {
BX_ERROR(("VGATHERQPD_VpdHpd: Gather with 16-bit address size"));
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == BX_NIL_REGISTER) {
BX_ERROR(("VGATHERQPD_VpdHpd: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
if (i->sibIndex() == i->vvv() || i->sibIndex() == i->nnn() || i->vvv() == i->nnn()) {
BX_ERROR(("VGATHERQPD_VpdHpd: incorrect source operands"));
exception(BX_UD_EXCEPTION, 0);
}
BxPackedAvxRegister *mask = &BX_AVX_REG(i->vvv()), *dest = &BX_AVX_REG(i->nnn());
unsigned num_elements = 2 * i->getVL();
for (unsigned n=0; n < 4; n++) // index size = 64, element_size = 64, max vector size = 256
{
if (n >= num_elements) {
mask->avx64u(n) = 0;
dest->avx64u(n) = 0;
continue;
}
if (mask->avx64u(n) & BX_CONST64(0x8000000000000000)) {
dest->avx64u(n) = read_virtual_qword(i->seg(), BxResolveGatherQ(i, n));
}
mask->avx64u(n) = 0;
}
}
#endif

218
bochs/cpu/avx_pfp.cc
View File

@ -36,6 +36,8 @@ extern float32 approximate_rcp(float32 op);
#include "fpu/softfloat-compare.h"
#include "fpu/softfloat-specialize.h"
#include "simd_pfp.h"
void BX_CPU_C::print_state_AVX(void)
{
BX_DEBUG(("MXCSR: 0x%08x\n", BX_MXCSR_REGISTER));
@ -326,14 +328,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (4*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx32u(n) = float32_denormal_to_zero(op1.avx32u(n));
op2.avx32u(n) = float32_denormal_to_zero(op2.avx32u(n));
}
op1.avx32u(n) = float32_add(op1.avx32u(n), op2.avx32u(n), status);
for (unsigned n=0; n < len; n++) {
sse_addps(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -422,14 +418,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (4*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx32u(n) = float32_denormal_to_zero(op1.avx32u(n));
op2.avx32u(n) = float32_denormal_to_zero(op2.avx32u(n));
}
op1.avx32u(n) = float32_mul(op1.avx32u(n), op2.avx32u(n), status);
for (unsigned n=0; n < len; n++) {
sse_mulps(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -444,18 +434,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPD_VpdHpdWpdR(bxInstruction_c
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (2*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx64u(n) = float64_denormal_to_zero(op1.avx64u(n));
op2.avx64u(n) = float64_denormal_to_zero(op2.avx64u(n));
}
op1.avx64u(n) = float64_mul(op1.avx64u(n), op2.avx64u(n), status);
for (unsigned n=0; n < len; n++) {
sse_mulpd(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -669,18 +653,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPS_VpsHpsWpsR(bxInstruction_c
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (4*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx32u(n) = float32_denormal_to_zero(op1.avx32u(n));
op2.avx32u(n) = float32_denormal_to_zero(op2.avx32u(n));
}
op1.avx32u(n) = float32_sub(op1.avx32u(n), op2.avx32u(n), status);
for (unsigned n=0; n < len; n++) {
sse_subps(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -699,14 +677,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (2*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx64u(n) = float64_denormal_to_zero(op1.avx64u(n));
op2.avx64u(n) = float64_denormal_to_zero(op2.avx64u(n));
}
op1.avx64u(n) = float64_sub(op1.avx64u(n), op2.avx64u(n), status);
for (unsigned n=0; n < len; n++) {
sse_subpd(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -769,15 +741,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (4*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx32u(n) = float32_denormal_to_zero(op1.avx32u(n));
op2.avx32u(n) = float32_denormal_to_zero(op2.avx32u(n));
}
int rc = float32_compare(op1.avx32u(n), op2.avx32u(n), status);
op1.avx32u(n) = (rc == float_relation_less) ? op1.avx32u(n) : op2.avx32u(n);
for (unsigned n=0; n < len; n++) {
sse_minps(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -792,19 +757,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPD_VpdHpdWpdR(bxInstruction_c
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (2*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx64u(n) = float64_denormal_to_zero(op1.avx64u(n));
op2.avx64u(n) = float64_denormal_to_zero(op2.avx64u(n));
}
int rc = float64_compare(op1.avx64u(n), op2.avx64u(n), status);
op1.avx64u(n) = (rc == float_relation_less) ? op1.avx64u(n) : op2.avx64u(n);
for (unsigned n=0; n < len; n++) {
sse_minpd(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -871,14 +829,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (4*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx32u(n) = float32_denormal_to_zero(op1.avx32u(n));
op2.avx32u(n) = float32_denormal_to_zero(op2.avx32u(n));
}
op1.avx32u(n) = float32_div(op1.avx32u(n), op2.avx32u(n), status);
for (unsigned n=0; n < len; n++) {
sse_divps(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -893,18 +845,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPD_VpdHpdWpdR(bxInstruction_c
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (2*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx64u(n) = float64_denormal_to_zero(op1.avx64u(n));
op2.avx64u(n) = float64_denormal_to_zero(op2.avx64u(n));
}
op1.avx64u(n) = float64_div(op1.avx64u(n), op2.avx64u(n), status);
for (unsigned n=0; n < len; n++) {
sse_divpd(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -963,19 +909,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPS_VpsHpsWpsR(bxInstruction_c
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (4*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx32u(n) = float32_denormal_to_zero(op1.avx32u(n));
op2.avx32u(n) = float32_denormal_to_zero(op2.avx32u(n));
}
int rc = float32_compare(op1.avx32u(n), op2.avx32u(n), status);
op1.avx32u(n) = (rc == float_relation_greater) ? op1.avx32u(n) : op2.avx32u(n);
for (unsigned n=0; n < len; n++) {
sse_maxps(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -994,15 +933,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (2*len); n++) {
if (MXCSR.get_DAZ()) {
op1.avx64u(n) = float64_denormal_to_zero(op1.avx64u(n));
op2.avx64u(n) = float64_denormal_to_zero(op2.avx64u(n));
}
int rc = float64_compare(op1.avx64u(n), op2.avx64u(n), status);
op1.avx64u(n) = (rc == float_relation_greater) ? op1.avx64u(n) : op2.avx64u(n);
for (unsigned n=0; n < len; n++) {
sse_maxpd(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -1069,17 +1001,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (2*len); n+=2) {
if (MXCSR.get_DAZ()) {
op1.avx64u(n) = float64_denormal_to_zero(op1.avx64u(n));
op1.avx64u(n+1) = float64_denormal_to_zero(op1.avx64u(n+1));
op2.avx64u(n) = float64_denormal_to_zero(op2.avx64u(n));
op2.avx64u(n+1) = float64_denormal_to_zero(op2.avx64u(n+1));
}
op1.avx64u(n) = float64_add(op1.avx64u(n), op1.avx64u(n+1), status);
op1.avx64u(n+1) = float64_add(op2.avx64u(n), op2.avx64u(n+1), status);
for (unsigned n=0; n < len; n++) {
sse_haddpd(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -1098,24 +1021,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (4*len); n+=4) {
if (MXCSR.get_DAZ()) {
op1.avx32u(n) = float32_denormal_to_zero(op1.avx32u(n));
op1.avx32u(n+1) = float32_denormal_to_zero(op1.avx32u(n+1));
op1.avx32u(n+2) = float32_denormal_to_zero(op1.avx32u(n+2));
op1.avx32u(n+3) = float32_denormal_to_zero(op1.avx32u(n+3));
op2.avx32u(n) = float32_denormal_to_zero(op2.avx32u(n));
op2.avx32u(n+1) = float32_denormal_to_zero(op2.avx32u(n+1));
op2.avx32u(n+2) = float32_denormal_to_zero(op2.avx32u(n+2));
op2.avx32u(n+3) = float32_denormal_to_zero(op2.avx32u(n+3));
}
op1.avx32u(n) = float32_add(op1.avx32u(n), op1.avx32u(n+1), status);
op1.avx32u(n+1) = float32_add(op1.avx32u(n+2), op1.avx32u(n+3), status);
op1.avx32u(n+2) = float32_add(op2.avx32u(n), op2.avx32u(n+1), status);
op1.avx32u(n+3) = float32_add(op2.avx32u(n+2), op2.avx32u(n+3), status);
for (unsigned n=0; n < len; n++) {
sse_haddps(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -1134,17 +1041,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPD_VpdHpdWpdR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (2*len); n+=2) {
if (MXCSR.get_DAZ()) {
op1.avx64u(n) = float64_denormal_to_zero(op1.avx64u(n));
op1.avx64u(n+1) = float64_denormal_to_zero(op1.avx64u(n+1));
op2.avx64u(n) = float64_denormal_to_zero(op2.avx64u(n));
op2.avx64u(n+1) = float64_denormal_to_zero(op2.avx64u(n+1));
}
op1.avx64u(n) = float64_sub(op1.avx64u(n), op1.avx64u(n+1), status);
op1.avx64u(n+1) = float64_sub(op2.avx64u(n), op2.avx64u(n+1), status);
for (unsigned n=0; n < len; n++) {
sse_hsubpd(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -1163,24 +1061,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPS_VpsHpsWpsR(bxInstruction_c
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (4*len); n+=4) {
if (MXCSR.get_DAZ()) {
op1.avx32u(n) = float32_denormal_to_zero(op1.avx32u(n));
op1.avx32u(n+1) = float32_denormal_to_zero(op1.avx32u(n+1));
op1.avx32u(n+2) = float32_denormal_to_zero(op1.avx32u(n+2));
op1.avx32u(n+3) = float32_denormal_to_zero(op1.avx32u(n+3));
op2.avx32u(n) = float32_denormal_to_zero(op2.avx32u(n));
op2.avx32u(n+1) = float32_denormal_to_zero(op2.avx32u(n+1));
op2.avx32u(n+2) = float32_denormal_to_zero(op2.avx32u(n+2));
op2.avx32u(n+3) = float32_denormal_to_zero(op2.avx32u(n+3));
}
op1.avx32u(n) = float32_sub(op1.avx32u(n), op1.avx32u(n+1), status);
op1.avx32u(n+1) = float32_sub(op1.avx32u(n+2), op1.avx32u(n+3), status);
op1.avx32u(n+2) = float32_sub(op2.avx32u(n), op2.avx32u(n+1), status);
op1.avx32u(n+3) = float32_sub(op2.avx32u(n+2), op2.avx32u(n+3), status);
for (unsigned n=0; n < len; n++) {
sse_hsubps(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -1308,17 +1190,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPD_VpdHpdWpdR(bxInstruction
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (2*len); n+=2) {
if (MXCSR.get_DAZ()) {
op1.avx64u(n) = float64_denormal_to_zero(op1.avx64u(n));
op1.avx64u(n+1) = float64_denormal_to_zero(op1.avx64u(n+1));
op2.avx64u(n) = float64_denormal_to_zero(op2.avx64u(n));
op2.avx64u(n+1) = float64_denormal_to_zero(op2.avx64u(n+1));
}
op1.avx64u(n) = float64_sub(op1.avx64u(n), op2.avx64u(n), status);
op1.avx64u(n+1) = float64_add(op1.avx64u(n+1), op2.avx64u(n+1), status);
for (unsigned n=0; n < len; n++) {
sse_addsubpd(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);
@ -1337,17 +1210,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPS_VpsHpsWpsR(bxInstruction
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
for (unsigned n=0; n < (4*len); n+=2) {
if (MXCSR.get_DAZ()) {
op1.avx32u(n) = float32_denormal_to_zero(op1.avx32u(n));
op1.avx32u(n+1) = float32_denormal_to_zero(op1.avx32u(n+1));
op2.avx32u(n) = float32_denormal_to_zero(op2.avx32u(n));
op2.avx32u(n+1) = float32_denormal_to_zero(op2.avx32u(n+1));
}
op1.avx32u(n) = float32_sub(op1.avx32u(n), op2.avx32u(n), status);
op1.avx32u(n+1) = float32_add(op1.avx32u(n+1), op2.avx32u(n+1), status);
for (unsigned n=0; n < len; n++) {
sse_addsubps(&op1.avx128(n), &op2.avx128(n), status, MXCSR.get_DAZ());
}
check_exceptionsSSE(status.float_exception_flags);

310
bochs/cpu/bmi32.cc Normal file
View File

@ -0,0 +1,310 @@
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2011 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
/////////////////////////////////////////////////////////////////////////
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_AVX
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ANDN_GdBdEdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("ANDN_GdBdEd: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
Bit32u op2_32 = BX_READ_32BIT_REG(i->vvv());
op1_32 = op1_32 & ~op2_32;
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULX_GdBdEdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("MULX_GdBdEdR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = EDX;
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
Bit64u product_64 = ((Bit64u) op1_32) * ((Bit64u) op2_32);
BX_WRITE_32BIT_REGZ(i->vvv(), GET32L(product_64));
BX_WRITE_32BIT_REGZ(i->nnn(), GET32H(product_64));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSI_BdEdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("BLSI_BdEd: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
bx_bool tmpCF = (op1_32 == 0);
op1_32 = (-op1_32) & op1_32;
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
set_CF(tmpCF);
BX_WRITE_32BIT_REGZ(i->vvv(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSMSK_BdEdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("BLSMSK_BdEd: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
bx_bool tmpCF = (op1_32 == 0);
op1_32 = (op1_32-1) ^ op1_32;
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
set_CF(tmpCF);
BX_WRITE_32BIT_REGZ(i->vvv(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSR_BdEdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("BLSR_BdEd: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
bx_bool tmpCF = (op1_32 == 0);
op1_32 = (op1_32-1) & op1_32;
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
set_CF(tmpCF);
BX_WRITE_32BIT_REGZ(i->vvv(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RORX_GdEdIbR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("RORX_GdEdIb: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
unsigned count = i->Ib() & 0x1f;
if (count) {
op1_32 = (op1_32 >> count) | (op1_32 << (32 - count));
}
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRX_GdEdBdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("SHRX_GdEdBdR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x1f;
if (count)
op1_32 >>= count;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SARX_GdEdBdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("SARX_GdEdBdR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x1f;
if (count) {
/* count < 32, since only lower 5 bits used */
op1_32 = ((Bit32s) op1_32) >> count;
}
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLX_GdEdBdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("SHLX_GdEdBdR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x1f;
if (count)
op1_32 <<= count;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GdEdBdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("BEXTR_GdEdBdR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit16u control = BX_READ_16BIT_REG(i->vvv());
unsigned start = control & 0xff;
unsigned len = control >> 8;
Bit32u op1_32 = 0;
if (start < 32 && len > 0) {
op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 >>= start;
if (len < 32) {
Bit32u extract_mask = (1 << len) - 1;
op1_32 &= extract_mask;
}
}
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BZHI_GdEdBdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("BZHI_GdEdBdR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
unsigned control = BX_READ_16BIT_REG(i->vvv()) & 0xff;
bx_bool tmpCF = 0;
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
if (control < 32) {
Bit32u mask = (1 << control) - 1;
op1_32 &= mask;
}
else {
tmpCF = 1;
}
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
set_CF(tmpCF);
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXT_GdEdBdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("PEXT_GdEdBdR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->vvv());
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm()), result_32 = 0;
Bit32u wr_mask = 0x1;
for (; op2_32 != 0; op2_32 >>= 1)
{
if (op2_32 & 0x1) {
if (op1_32 & 0x1) result_32 |= wr_mask;
wr_mask <<= 1;
}
op1_32 >>= 1;
}
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PDEP_GdEdBdR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("PDEP_GdEdBdR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit32u op1_32 = BX_READ_32BIT_REG(i->vvv());
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm()), result_32 = 0;
Bit32u wr_mask = 0x1;
for (; op2_32 != 0; op2_32 >>= 1)
{
if (op2_32 & 0x1) {
if (op1_32 & 0x1) result_32 |= wr_mask;
op1_32 >>= 1;
}
wr_mask <<= 1;
}
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
BX_NEXT_INSTR(i);
}
#endif

318
bochs/cpu/bmi64.cc Normal file
View File

@ -0,0 +1,318 @@
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2011 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
/////////////////////////////////////////////////////////////////////////
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_X86_64 && BX_SUPPORT_AVX
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ANDN_GqBqEqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("ANDN_GqBqEq: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
Bit64u op2_64 = BX_READ_64BIT_REG(i->vvv());
op1_64 = op1_64 & ~op2_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_NEXT_INSTR(i);
}
extern void long_mul(Bit128u *product, Bit64u op1, Bit64u op2);
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULX_GqBqEqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("MULX_GqBqEqR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = RDX;
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
Bit128u product_128;
// product_128 = ((Bit128u) op1_64) * ((Bit128u) op2_64);
// product_64l = (Bit64u) (product_128 & 0xFFFFFFFFFFFFFFFF);
// product_64h = (Bit64u) (product_128 >> 64);
long_mul(&product_128,op1_64,op2_64);
BX_WRITE_64BIT_REG(i->vvv(), product_128.lo);
BX_WRITE_64BIT_REG(i->nnn(), product_128.hi);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSI_BqEqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("BLSI_BqEq: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
bx_bool tmpCF = (op1_64 == 0);
op1_64 = (-op1_64) & op1_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
set_CF(tmpCF);
BX_WRITE_64BIT_REG(i->vvv(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSMSK_BqEqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("BLSMSK_BqEq: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
bx_bool tmpCF = (op1_64 == 0);
op1_64 = (op1_64-1) ^ op1_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
set_CF(tmpCF);
BX_WRITE_64BIT_REG(i->vvv(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSR_BqEqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("BLSR_BqEq: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
bx_bool tmpCF = (op1_64 == 0);
op1_64 = (op1_64-1) & op1_64;
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
set_CF(tmpCF);
BX_WRITE_64BIT_REG(i->vvv(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RORX_GqEqIbR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("RORX_GqEqIb: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
unsigned count = i->Ib() & 0x3f;
if (count) {
op1_64 = (op1_64 >> count) | (op1_64 << (64 - count));
}
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRX_GqEqBqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("SHRX_GqEqBqR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x3f;
if (count)
op1_64 >>= count;
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SARX_GqEqBqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("SARX_GqEqBqR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x3f;
if (count) {
/* count < 64, since only lower 6 bits used */
op1_64 = ((Bit64s) op1_64) >> count;
}
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLX_GqEqBqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("SHLX_GqEqBqR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
unsigned count = BX_READ_32BIT_REG(i->vvv()) & 0x3f;
if (count)
op1_64 <<= count;
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GqEqBqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("BEXTR_GqEqBqR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit16u control = BX_READ_16BIT_REG(i->vvv());
unsigned start = control & 0xff;
unsigned len = control >> 8;
Bit64u op1_64 = 0;
if (start < 64 && len > 0) {
op1_64 = BX_READ_64BIT_REG(i->rm());
op1_64 >>= start;
if (len < 64) {
Bit64u extract_mask = (BX_CONST64(1) << len) - 1;
op1_64 &= extract_mask;
}
}
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BZHI_GqEqBqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("BZHI_GqEqBqR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
unsigned control = BX_READ_16BIT_REG(i->vvv()) & 0xff;
bx_bool tmpCF = 0;
Bit64u op1_64 = BX_READ_64BIT_REG(i->rm());
if (control < 64) {
Bit64u mask = (BX_CONST64(1) << control) - 1;
op1_64 &= mask;
}
else {
tmpCF = 1;
}
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
set_CF(tmpCF);
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXT_GqEqBqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("PEXT_GqEqBqR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->vvv());
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm()), result_64 = 0;
Bit64u wr_mask = 0x1;
for (; op2_64 != 0; op2_64 >>= 1)
{
if (op2_64 & 0x1) {
if (op1_64 & 0x1) result_64 |= wr_mask;
wr_mask <<= 1;
}
op1_64 >>= 1;
}
BX_WRITE_64BIT_REG(i->nnn(), result_64);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PDEP_GqEqBqR(bxInstruction_c *i)
{
if (!protected_mode()) {
BX_DEBUG(("PDEP_GqEqBqR: not recognized in real or virtual-8086 mode"));
exception(BX_UD_EXCEPTION, 0);
}
Bit64u op1_64 = BX_READ_64BIT_REG(i->vvv());
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm()), result_64 = 0;
Bit64u wr_mask = 0x1;
for (; op2_64 != 0; op2_64 >>= 1)
{
if (op2_64 & 0x1) {
if (op1_64 & 0x1) result_64 |= wr_mask;
op1_64 >>= 1;
}
wr_mask <<= 1;
}
BX_WRITE_64BIT_REG(i->nnn(), result_64);
BX_NEXT_INSTR(i);
}
#endif

188
bochs/cpu/cpu.h
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@ -1781,6 +1781,7 @@ public: // for now...
BX_SMF BX_INSF_TYPE LOAD_Wss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOAD_Wsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOAD_Ww(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOAD_Wb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#if BX_SUPPORT_AVX
BX_SMF BX_INSF_TYPE LOAD_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOAD_VectorQ(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2127,7 +2128,7 @@ public: // for now...
BX_SMF BX_INSF_TYPE MAXSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PUNPCKLBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PUNPCKLWD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE UNPCKLPS_VpsWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE UNPCKLPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PACKSSWB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PCMPGTB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PCMPGTW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2135,7 +2136,7 @@ public: // for now...
BX_SMF BX_INSF_TYPE PACKUSWB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PUNPCKHBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PUNPCKHWD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE UNPCKHPS_VpsWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE UNPCKHPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PACKSSDW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PUNPCKLQDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PUNPCKHQDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2384,19 +2385,21 @@ public: // for now...
#endif
#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
/* AVX */
BX_SMF BX_INSF_TYPE VZEROUPPER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VZEROALL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSS_VssWssR(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSD_VsdWsdR(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSS_VssHpsWssR(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSD_VsdHpdWsdR(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVAPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVAPS_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVUPS_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVAPS_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVUPS_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVLPD_VpdMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVHPD_VpdMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVLHPS_VpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVHLPS_VpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVLPD_VpdHpdMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVHPD_VpdHpdMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVLHPS_VpsHpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVHLPS_VpsHpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSHDUP_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSLDUP_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVDDUP_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2485,14 +2488,14 @@ public: // for now...
BX_SMF BX_INSF_TYPE VBROADCASTF128_VdqMdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VBLENDVPS_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VBLENDVPD_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VINSERTF128_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VINSERTF128_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF128_WdqVdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF128_WdqVdqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPERMILPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPERMILPS_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPERMILPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPERMILPD_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPERM2F128_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPERM2F128_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMASKMOVPS_VpsHpsMps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMASKMOVPD_VpdHpdMpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMASKMOVPS_MpsHpsVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2500,6 +2503,163 @@ public: // for now...
BX_SMF BX_INSF_TYPE VCVTPH2PS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VCVTPS2PH_WpsVpsIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* AVX */
/* AVX2 */
BX_SMF BX_INSF_TYPE VPCMPEQB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPCMPEQW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPCMPEQD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPCMPEQQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPCMPGTB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPCMPGTW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPCMPGTD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPCMPGTQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMINSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMINSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMINSD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMINUB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMINUW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMINUD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMAXSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMAXSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMAXSD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMAXUB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMAXUW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMAXUD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSIGNB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSIGNW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSIGND_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPADDB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPADDW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPADDD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPADDQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSUBB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSUBW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSUBD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSUBQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPABSB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPABSW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPABSD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSUBSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSUBSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSUBUSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSUBUSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPADDSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPADDSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPADDUSB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPADDUSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPAVGB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPAVGW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPHADDW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPHADDD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPHADDSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPHSUBW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPHSUBD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPHSUBSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSHUFHW_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSHUFLW_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPACKUSWB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPACKSSWB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPACKUSDW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPACKSSDW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPUNPCKLBW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPUNPCKHBW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPUNPCKLWD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPUNPCKHWD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMULLD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMULLW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMULHW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMULHUW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMULDQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMULUDQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMULHRSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMADDUBSW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMADDWD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMPSADBW_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPBLENDW_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSADBW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSHUFB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRLW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRLD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRLQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSLLW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSLLD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSLLQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRAW_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRAD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRLW_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRLD_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRLQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSLLW_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSLLD_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSLLQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRAW_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRAD_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRLDQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSLLDQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPALIGNR_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBW256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBD256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBQ256_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXWD256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXWQ256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXDQ256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBW256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBD256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBQ256_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXWD256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXWQ256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXDQ256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPERMD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPERMQ_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRAVD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSLLVD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSLLVQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRLVD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPSRLVQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPBROADCASTB_VdqWb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPBROADCASTW_VdqWw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPBROADCASTD_VdqWd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPBROADCASTQ_VdqWq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VGATHERDPS_VpsHps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VGATHERQPS_VpsHps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VGATHERDPD_VpdHpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VGATHERQPD_VpdHpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* AVX2 */
/* BMI */
BX_SMF BX_INSF_TYPE ANDN_GdBdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MULX_GdBdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BLSI_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BLSMSK_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BLSR_BdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RORX_GdEdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SHLX_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SHRX_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SARX_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BEXTR_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BZHI_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PEXT_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PDEP_GdEdBdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE ANDN_GqBqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MULX_GqBqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BLSI_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BLSMSK_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BLSR_BqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RORX_GqEqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SHLX_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SHRX_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SARX_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BEXTR_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BZHI_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PEXT_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PDEP_GqEqBqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* BMI */
#endif
BX_SMF BX_INSF_TYPE CMPXCHG8B(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2945,6 +3105,10 @@ public: // for now...
BX_SMF bx_address BxResolve64Base(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF bx_address BxResolve64BaseIndex(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
#if BX_SUPPORT_AVX
BX_SMF bx_address BxResolveGatherD(bxInstruction_c *, unsigned) BX_CPP_AttrRegparmN(2);
BX_SMF bx_address BxResolveGatherQ(bxInstruction_c *, unsigned) BX_CPP_AttrRegparmN(2);
#endif
// <TAG-CLASS-CPU-END>
#if BX_DEBUGGER
@ -4130,6 +4294,7 @@ enum {
#define BxOSizeGrp 0x0090 // Group encoding: 1001
#define BxPrefixVEX 0x00A0 // Group encoding: 1010
#define BxSplitVexW 0x00B0 // Group encoding: 1011
#define BxSplitVexW64 0x00C0 // Group encoding: 1100 - VexW ignored in 32-bit mode
// The BxImmediate2 mask specifies kind of second immediate data
// required by instruction.
@ -4141,6 +4306,7 @@ enum {
#define BxLockable 0x0400 // bit 10
#define BxArithDstRM 0x0800 // bit 11
#define BxVexW0 0x1000 // bit 12
#define BxVexW1 0x2000 // bit 13
#define BxTraceEnd 0x4000 // bit 14
@ -4166,6 +4332,8 @@ enum {
#define BxGroup13 BxGroupN
#define BxGroup14 BxGroupN
#define BxGroup15 BxSplitGroupN
#define BxGroup16 BxGroupN
#define BxGroup17 BxGroupN
#define BxGroupFP BxSplitGroupN

3
bochs/cpu/cpuid.h
View File

@ -95,7 +95,8 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPU_AVX2 (1 << 26) /* AVX2 instruction */
#define BX_CPU_AVX_F16C (1 << 27) /* AVX F16 convert instruction */
#define BX_CPU_AVX_FMA (1 << 28) /* AVX FMA instruction */
#define BX_CPU_BMI (1 << 29) /* BMI instruction */
#define BX_CPU_BMI1 (1 << 29) /* BMI1 instruction */
#define BX_CPU_BMI2 (1 << 30) /* BMI2 instruction */
// cpuid non-ISA features
#define BX_CPU_DEBUG_EXTENSIONS (1 << 0) /* Debug Extensions support */

24
bochs/cpu/fetchdecode.cc
View File

@ -1303,7 +1303,7 @@ BX_CPU_C::fetchDecode32(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
int vvv = -1;
#if BX_SUPPORT_AVX
int had_vex = 0;
bx_bool vex_w = 0;
bx_bool vex_w = 0, vex_l = 0;
#endif
os_32 = is_32 =
@ -1411,7 +1411,8 @@ fetch_b1:
}
vvv = 15 - ((vex >> 3) & 0xf);
i->setVL(BX_VL128 + ((vex >> 2) & 0x1));
vex_l = (vex >> 2) & 0x1;
i->setVL(BX_VL128 + vex_l);
sse_prefix = vex & 0x3;
if (remain != 0) {
@ -1622,7 +1623,7 @@ modrm_done:
if (had_vex < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
OpcodeInfoPtr = &BxOpcodeTableAVX[b1-256];
OpcodeInfoPtr = &BxOpcodeTableAVX[(b1-256) + 768*vex_l];
}
#endif
@ -1654,7 +1655,11 @@ modrm_done:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn + (mod_mem << 3)]);
break;
#if BX_SUPPORT_AVX
case BxSplitVexW:
case BxSplitVexW64: // VexW is ignored in 32-bit mode
BX_ASSERT(had_vex != 0);
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[0]);
break;
case BxSplitVexW: // VexW is a real opcode extension
BX_ASSERT(had_vex != 0);
if (vex_w)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
@ -1710,7 +1715,7 @@ modrm_done:
if (had_vex < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
OpcodeInfoPtr = &BxOpcodeTableAVX[b1-256];
OpcodeInfoPtr = &BxOpcodeTableAVX[(b1-256) + 768*vex_l];
}
#endif
@ -1869,15 +1874,12 @@ modrm_done:
if ((attr & BxVexW0) != 0 && vex_w) {
ia_opcode = BX_IA_ERROR;
}
if ((attr & BxVexW1) != 0 && !vex_w) {
ia_opcode = BX_IA_ERROR;
}
if ((op_flags & BX_VEX_NO_VVV) && i->vvv() != 0) {
ia_opcode = BX_IA_ERROR;
}
if (i->getVL() == BX_VEX_L128 && !(op_flags & BX_VEX_L128)) {
ia_opcode = BX_IA_ERROR;
}
if (i->getVL() == BX_VEX_L256 && !(op_flags & BX_VEX_L256)) {
ia_opcode = BX_IA_ERROR;
}
}
#endif

4
bochs/cpu/fetchdecode.h
View File

@ -61,9 +61,7 @@ BX_CPP_INLINE Bit64u FetchQWORD(const Bit8u *iptr)
#define BX_PREPARE_SSE (0x01)
#define BX_PREPARE_AVX (0x02)
#define BX_VEX_L128 (0x04) /* VEX.L128 allowed */
#define BX_VEX_L256 (0x08) /* VEX.L256 allowed */
#define BX_VEX_NO_VVV (0x10) /* no VEX.VVV allowed */
#define BX_VEX_NO_VVV (0x04) /* no VEX.VVV allowed */
struct bxIAOpcodeTable {
BxExecutePtr_tR execute1;

19
bochs/cpu/fetchdecode64.cc
View File

@ -1706,7 +1706,7 @@ BX_CPU_C::fetchDecode64(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
int vvv = -1;
#if BX_SUPPORT_AVX
int had_vex = 0;
bx_bool vex_w = 0;
bx_bool vex_w = 0, vex_l = 0;
#endif
i->ResolveModrm = 0;
@ -1858,7 +1858,8 @@ fetch_b1:
}
vvv = 15 - ((vex >> 3) & 0xf);
i->setVL(BX_VL128 + ((vex >> 2) & 0x1));
vex_l = (vex >> 2) & 0x1;
i->setVL(BX_VL128 + vex_l);
sse_prefix = vex & 0x3;
if (remain != 0) {
@ -2025,7 +2026,7 @@ modrm_done:
if (had_vex < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
OpcodeInfoPtr = &BxOpcodeTableAVX[b1-256];
OpcodeInfoPtr = &BxOpcodeTableAVX[(b1-256) + 768*vex_l];
}
#endif
@ -2058,6 +2059,7 @@ modrm_done:
break;
#if BX_SUPPORT_AVX
case BxSplitVexW:
case BxSplitVexW64:
BX_ASSERT(had_vex != 0);
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[vex_w]);
break;
@ -2106,7 +2108,7 @@ modrm_done:
if (had_vex < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
OpcodeInfoPtr = &BxOpcodeTableAVX[b1-256];
OpcodeInfoPtr = &BxOpcodeTableAVX[(b1-256) + 768*vex_l];
}
#endif
@ -2273,15 +2275,12 @@ modrm_done:
if ((attr & BxVexW0) != 0 && vex_w) {
ia_opcode = BX_IA_ERROR;
}
if ((attr & BxVexW1) != 0 && !vex_w) {
ia_opcode = BX_IA_ERROR;
}
if ((op_flags & BX_VEX_NO_VVV) && i->vvv() != 0) {
ia_opcode = BX_IA_ERROR;
}
if (i->getVL() == BX_VEX_L128 && !(op_flags & BX_VEX_L128)) {
ia_opcode = BX_IA_ERROR;
}
if (i->getVL() == BX_VEX_L256 && !(op_flags & BX_VEX_L256)) {
ia_opcode = BX_IA_ERROR;
}
}
#endif

2576
bochs/cpu/fetchdecode_avx.h
View File

File diff suppressed because it is too large Load Diff

34
bochs/cpu/generic_cpuid.cc
View File

@ -726,7 +726,7 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
}
#if BX_SUPPORT_AVX
static bx_bool avx_enabled = SIM->get_param_bool(BXPN_CPUID_AVX)->get();
static unsigned avx_enabled = SIM->get_param_num(BXPN_CPUID_AVX)->get();
if (avx_enabled) {
features_bitmask |= BX_CPU_AVX;
@ -734,6 +734,13 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
BX_PANIC(("PANIC: AVX emulation requires XSAVE support !"));
return;
}
if (! BX_SUPPORT_X86_64) {
BX_PANIC(("PANIC: AVX emulation requires x86-64 support !"));
return;
}
if (avx_enabled >= 2)
features_bitmask |= BX_CPU_AVX2;
}
static bx_bool avx_f16c_enabled = SIM->get_param_bool(BXPN_CPUID_AVX_F16CVT)->get();
@ -745,6 +752,19 @@ void bx_generic_cpuid_t::init_isa_extensions_bitmask(void)
features_bitmask |= BX_CPU_AVX_F16C;
}
static unsigned bmi_enabled = SIM->get_param_num(BXPN_CPUID_BMI)->get();
if (bmi_enabled) {
features_bitmask |= BX_CPU_BMI1;
if (! avx_enabled) {
BX_PANIC(("PANIC: Bit Manipulation Instructions (BMI) emulation requires AVX support !"));
return;
}
if (bmi_enabled >= 2)
features_bitmask |= BX_CPU_BMI2;
}
#endif
#if BX_SUPPORT_VMX
@ -1208,9 +1228,21 @@ Bit32u bx_generic_cpuid_t::get_ext3_cpuid_features(void) const
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_FSGSBASE))
features |= BX_CPUID_EXT3_FSGSBASE;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_BMI1))
features |= BX_CPUID_EXT3_BMI1;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_AVX2))
features |= BX_CPUID_EXT3_AVX2;
if (BX_CPUID_SUPPORT_CPU_EXTENSION(BX_CPU_SMEP))
features |= BX_CPUID_EXT3_SMEP;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_BMI2))
features |= BX_CPUID_EXT3_BMI2;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_INVPCID))
features |= BX_CPUID_EXT3_INVPCID;
return features;
}

796
bochs/cpu/ia_opcodes.h
View File

@ -873,8 +873,8 @@ bx_define_opcode(BX_IA_MAXPD_VpdWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPD_VpdWp
bx_define_opcode(BX_IA_MAXSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MAXSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_UNPCKHPD_VpdWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHQDQ_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_UNPCKLPD_VpdWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLQDQ_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PUNPCKHDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKHPS_VpsWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PUNPCKLDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKLPS_VpsWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PUNPCKHDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKHPS_VpsWpsR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PUNPCKLDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKLPS_VpsWpsR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVAPD_VpdWpd, &BX_CPU_C::MOVAPS_VpsWpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVAPD_WpdVpd, &BX_CPU_C::MOVAPS_WpsVpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_CPU_SSE2, BX_PREPARE_SSE) /* dstRM */
bx_define_opcode(BX_IA_MOVDQA_VdqWdq, &BX_CPU_C::MOVAPS_VpsWpsM, &BX_CPU_C::MOVAPS_VpsWpsR, BX_CPU_SSE2, BX_PREPARE_SSE)
@ -899,7 +899,7 @@ bx_define_opcode(BX_IA_POR_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ORPS_VpsWpsR,
bx_define_opcode(BX_IA_PXOR_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::XORPS_VpsWpsR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PUNPCKLBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLBW_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PUNPCKLWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLWD_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_UNPCKLPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKLPS_VpsWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_UNPCKLPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKLPS_VpsWpsR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PACKSSWB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKSSWB_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PCMPGTB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTB_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PCMPGTW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTW_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
@ -907,7 +907,7 @@ bx_define_opcode(BX_IA_PCMPGTD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTD_V
bx_define_opcode(BX_IA_PACKUSWB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKUSWB_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PUNPCKHBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHBW_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PUNPCKHWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHWD_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_UNPCKHPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKHPS_VpsWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_UNPCKHPS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::UNPCKHPS_VpsWpsR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PACKSSDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKSSDW_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PUNPCKLQDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKLQDQ_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PUNPCKHQDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PUNPCKHQDQ_VdqWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
@ -1368,301 +1368,497 @@ bx_define_opcode(BX_IA_INVVPID, &BX_CPU_C::INVVPID, &BX_CPU_C::BxError, BX_CPU_V
bx_define_opcode(BX_IA_GETSEC, &BX_CPU_C::GETSEC, &BX_CPU_C::GETSEC, BX_CPU_SMX, 0)
// SMX
// AVX
#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
bx_define_opcode(BX_IA_VZEROUPPER, NULL, &BX_CPU_C::VZEROUPPER, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVAPS_VpsWps, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVAPS_WpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
bx_define_opcode(BX_IA_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVAPD_WpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
bx_define_opcode(BX_IA_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVUPS_WpsVps, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
bx_define_opcode(BX_IA_VMOVUPD_VpdWpd, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVUPD_WpdVpd, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
bx_define_opcode(BX_IA_VMOVDQA_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVDQU_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVDQA_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVDQU_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
bx_define_opcode(BX_IA_VMOVSD_VsdWsd, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::VMOVSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVSS_VssWss, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::VMOVSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVSD_WsdVsd, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::VMOVSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128) /* dstRM */
bx_define_opcode(BX_IA_VMOVSS_WssVss, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::VMOVSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128) /* dstRM */
bx_define_opcode(BX_IA_VMOVLPD_VpdMq, &BX_CPU_C::VMOVLPD_VpdMq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVLPD_MqVsd, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVHPD_VpdMq, &BX_CPU_C::VMOVHPD_VpdMq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVHPD_MqVsd, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVNTPS_MpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVNTPD_MpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVNTDQ_MdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VUNPCKLPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VUCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCOMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVMSKPS_GdVRps, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPS_GdVRps, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVMSKPD_GdVRpd, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPD_GdVRpd, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSQRTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSQRTSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VRSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRSQRTSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VRSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRSQRTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VRCPSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRCPSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VRCPPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRCPPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VANDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VANDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VANDNPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VANDNPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VXORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VXORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPD2DQ_VqWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2DQ_VqWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTDQ2PD_VpdWq, &BX_CPU_C::LOAD_VectorQ, &BX_CPU_C::VCVTDQ2PD_VpdWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTPD2PS_VpsWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2PS_VpsWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2SS_VssWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2SD_VsdWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTDQ2PS_VpsWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTDQ2PS_VpsWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPS2DQ_VdqWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPS2DQ_VdqWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMULPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMULPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMULSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMULSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSUBSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSUBSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VDIVPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VDIVPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VDIVSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VDIVSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMAXPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMAXPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMAXSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMAXSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMINPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMINPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMINSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMINSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSHUFHW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSHUFLW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VHADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VHADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VHSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VHSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVQ_WqVq, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::MOVQ_VqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128) /* dstRM */
bx_define_opcode(BX_IA_VMOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VCMPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCMPPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCMPSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCMPSD_VsdHpdWsdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCMPSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCMPSS_VssHpsWssIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSHUFPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSHUFPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPSRLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRAW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLD_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRAD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAD_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLD_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLDQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLDQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VLDMXCSR, &BX_CPU_C::LDMXCSR, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VSTMXCSR, &BX_CPU_C::STMXCSR, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVLPS_VpsMq, &BX_CPU_C::VMOVLPD_VpdMq, &BX_CPU_C::VMOVHLPS_VpsWps, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVHPS_VpsMq, &BX_CPU_C::VMOVHPD_VpdMq, &BX_CPU_C::VMOVLHPS_VpsWps, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVLPS_MqVps, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVHPS_MqVps, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VUNPCKLPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VUNPCKHPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCOMISS_VpsWps, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTPS2PD_VpdWps, &BX_CPU_C::LOAD_VectorQ, &BX_CPU_C::VCVTPS2PD_VpdWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPUNPCKHDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKLDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPACKSSWB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKSSWB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPGTB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPGTB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPGTW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPGTW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPGTD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPGTD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPGTQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPGTQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPACKUSWB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKUSWB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKLBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPCKLBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKLWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPCKLWD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKHBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPCKHBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKHWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPCKHWD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPACKUSDW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKUSDW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKLQDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKHQDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPEQB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPEQW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPEQD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPEQQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::PINSRW_VdqEwIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULLW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULLW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBUSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBUSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBUSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBUSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDUSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDUSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDUSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDUSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPAVGB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PAVGB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPAVGW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PAVGW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRAW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRAD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULHUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULHUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULHW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULHW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPANDN_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPAND_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPOR_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPXOR_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VLDDQU_VdqMdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPSLLW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULUDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULUDQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMADDWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMADDWD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSADBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSADBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVDQU_VdqUdq, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSHUFB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSHUFB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHADDW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHADDW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHADDD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHADDD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHADDSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHADDSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMADDUBSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMADDUBSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHSUBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHSUBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHSUBD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHSUBD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHSUBSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHSUBSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSIGNB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSIGNB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSIGNW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSIGNW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSIGND_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSIGND_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULHRSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULHRSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VTESTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VTESTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPTEST_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPTEST_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VBROADCASTSS_VpsMss, &BX_CPU_C::VBROADCASTSS_VpsMss, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VBROADCASTSD_VpdMsd, &BX_CPU_C::VBROADCASTSD_VpdMsd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L256)
bx_define_opcode(BX_IA_VBROADCASTF128_VdqMdq, &BX_CPU_C::VBROADCASTF128_VdqMdq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L256)
bx_define_opcode(BX_IA_VPABSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PABSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPABSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PABSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPABSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PABSD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULDQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPACKSSDW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKSSDW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMASKMOVPS_VpsHpsMps, &BX_CPU_C::VMASKMOVPS_VpsHpsMps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMASKMOVPS_MpsHpsVps, &BX_CPU_C::VMASKMOVPS_MpsHpsVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPMOVSXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXBW_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXBD_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVSXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVSXBQ_VdqWwR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVSXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXWD_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVSXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXWQ_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVSXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXDQ_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXBW_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXBD_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVZXBQ_VdqWwR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXWD_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXWQ_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXDQ_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINSD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINUB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINUB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINUD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINUD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXSD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXUB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXUB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXUD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXUD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULLD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULLD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHMINPOSUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPERMILPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPERMILPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPERMILPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPERMILPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPERM2F128_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L256)
bx_define_opcode(BX_IA_VROUNDPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VROUNDSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VROUNDSD_VsdHpdWsdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VROUNDSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VROUNDSS_VssHpsWssIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VBLENDPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VBLENDPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPBLENDW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PBLENDW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPALIGNR_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PALIGNR_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, &BX_CPU_C::PEXTRB_EbdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_CPU_C::PEXTRW_EwdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VINSERTF128_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L256)
bx_define_opcode(BX_IA_VEXTRACTF128_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L256)
bx_define_opcode(BX_IA_VPINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqEbIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsWssIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VDPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDPPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VDPPD_VpdHpdWpdIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::DPPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::MPSADBW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VBLENDVPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VBLENDVPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPESTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPISTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPISTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESIMC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESENC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESENC_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESENCLAST_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESENCLAST_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESDEC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESDEC_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESDECLAST_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESDECLAST_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESKEYGENASSIST_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCLMULQDQ_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCLMULQDQ_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVD_VdqEd, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVD_VdqEdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPINSRD_VdqEdIb, &BX_CPU_C::PINSRD_VdqEdIbM, &BX_CPU_C::PINSRD_VdqEdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VCVTSI2SD_VsdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTSI2SD_VsdEdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSI2SS_VssEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTSI2SS_VssEdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTSI2SD_VsdEqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTSI2SS_VssEqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GqWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPINSRQ_VdqEqIb, &BX_CPU_C::PINSRD_VdqEdIbM, &BX_CPU_C::PINSRD_VdqEdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVQ_EqVq, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::MOVQ_EqVqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VCVTPH2PS_VpsWps, &BX_CPU_C::LOAD_VectorQ, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_CPU_AVX_F16C, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, BX_CPU_AVX_F16C, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
#endif
// AVX
bx_define_opcode(BX_IA_VZEROUPPER, NULL, &BX_CPU_C::VZEROUPPER, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VZEROALL, NULL, &BX_CPU_C::VZEROALL, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VLDMXCSR, &BX_CPU_C::LDMXCSR, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VSTMXCSR, &BX_CPU_C::STMXCSR, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVAPS_VpsWps, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVAPS_WpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV) /* dstRM */
bx_define_opcode(BX_IA_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVAPD_WpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV) /* dstRM */
bx_define_opcode(BX_IA_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVUPS_WpsVps, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV) /* dstRM */
bx_define_opcode(BX_IA_VMOVUPD_VpdWpd, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVUPD_WpdVpd, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV) /* dstRM */
bx_define_opcode(BX_IA_VMOVDQA_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVDQU_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVDQA_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVDQU_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV) /* dstRM */
bx_define_opcode(BX_IA_V128_VMOVSD_VsdHpdWsd, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVSS_VssHpsWss, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::VMOVSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVSD_WsdHpdVsd, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX) /* dstRM */
bx_define_opcode(BX_IA_V128_VMOVSS_WssHpsVss, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::VMOVSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX) /* dstRM */
bx_define_opcode(BX_IA_V128_VMOVLPS_VpsHpsMq, &BX_CPU_C::VMOVLPD_VpdHpdMq, &BX_CPU_C::VMOVHLPS_VpsHpsWps, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVHPS_VpsHpsMq, &BX_CPU_C::VMOVHPD_VpdHpdMq, &BX_CPU_C::VMOVLHPS_VpsHpsWps, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVLPS_MqVps, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VMOVHPS_MqVps, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VMOVLPD_MqVsd, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VMOVHPD_MqVsd, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VMOVLPD_VpdHpdMq, &BX_CPU_C::VMOVLPD_VpdHpdMq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVHPD_VpdHpdMq, &BX_CPU_C::VMOVHPD_VpdHpdMq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVNTPS_MpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVNTPD_MpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVNTDQ_MdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VLDDQU_VdqMdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCOMISS_VpsWps, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VUCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCOMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VSQRTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VSQRTSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VRSQRTSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRSQRTSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VRSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRSQRTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VRCPSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRCPSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VRCPPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRCPPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VANDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VANDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VANDNPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VANDNPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VXORPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VXORPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VADDSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VADDSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMULPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMULPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMULSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMULSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSUBSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSUBSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VDIVPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VDIVPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VDIVSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VDIVSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMAXPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMAXPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMAXSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMAXSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMINPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMINPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMINSD_VsdHpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdHpdWsdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMINSS_VssHpsWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssHpsWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VHADDPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VHADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VHSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VHSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCMPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCMPPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCMPSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCMPSD_VsdHpdWsdIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCMPSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCMPSS_VssHpsWssIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSHUFPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSHUFPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VADDSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VADDSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VROUNDPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VROUNDSD_VsdHpdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VROUNDSD_VsdHpdWsdIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VROUNDSS_VssHpsWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VROUNDSS_VssHpsWssIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VDPPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDPPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VDPPD_VpdHpdWpdIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::DPPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLQ_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRAW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSLLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSLLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSLLQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLQ_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRAW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSLLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLD_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRAD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRAD_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSLLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLD_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSLLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSRLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSRLDQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSLLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLDQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVMSKPS_GdVRps, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPS_GdVRps, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVMSKPD_GdVRpd, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPD_GdVRpd, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VUNPCKLPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VUNPCKLPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VUNPCKHPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPUNPCKLBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKLBW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPUNPCKLWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKLWD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPUNPCKHBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKHBW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPUNPCKHWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPUNPCKHWD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPCMPEQB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPCMPEQW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPCMPEQD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPCMPEQQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPEQQ_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPCMPGTB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPCMPGTW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPCMPGTD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPCMPGTQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPCMPGTQ_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSUBSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBSB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBSW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPADDSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDSB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPADDSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDSW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSUBUSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBUSB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSUBUSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBUSW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPADDUSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDUSB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPADDUSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDUSW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPAVGB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPAVGB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPAVGW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPAVGW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPANDN_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPAND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPXOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMULHRSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHRSW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMULLW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULLW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMULHW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULHUW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVDQU_VdqUdq, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSUBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPADDB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPADDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPADDD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSHUFB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSHUFB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPHADDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPHADDD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPHSUBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPHSUBD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPHADDSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHADDSW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPHSUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPHSUBSW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMADDWD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADDWD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMADDUBSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMADDUBSW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSIGNB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGNB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSIGNW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGNW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSIGND_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSIGND_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VTESTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VTESTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPTEST_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPTEST_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VBROADCASTSS_VpsMss, &BX_CPU_C::VBROADCASTSS_VpsMss, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VBROADCASTSD_VpdMsd, &BX_CPU_C::VBROADCASTSD_VpdMsd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VBROADCASTF128_VdqMdq, &BX_CPU_C::VBROADCASTF128_VdqMdq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPABSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPABSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPABSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPABSD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPACKSSWB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKSSWB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPACKUSWB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKUSWB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPACKUSDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKUSDW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPACKSSDW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPACKSSDW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMASKMOVPS_VpsHpsMps, &BX_CPU_C::VMASKMOVPS_VpsHpsMps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMASKMOVPS_MpsHpsVps, &BX_CPU_C::VMASKMOVPS_MpsHpsVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VPMOVSXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXBW_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXBD_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVSXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVSXBQ_VdqWwR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVSXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXWD_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVSXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXWQ_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVSXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXDQ_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXBW_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXBD_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVZXBQ_VdqWwR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXWD_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXWQ_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXDQ_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPMINSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMINSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMINUB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMINUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMAXSB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMAXSW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMAXUB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUB_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMAXUW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUW_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPHMINPOSUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPERMILPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsHpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VPERMILPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdHpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VPERMILPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPERMILPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VBLENDPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VBLENDPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPBLENDW_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPBLENDW_VdqHdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPALIGNR_VdqHdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsWssIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VPERM2F128_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqHdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VINSERTF128_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VEXTRACTF128_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VBLENDVPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPS_VpsHpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VBLENDVPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPD_VpdHpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VMPSADBW_VdqHdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPCMPESTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPCMPISTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPCMPISTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VAESIMC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VAESENC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESENC_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VAESENCLAST_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESENCLAST_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VAESDEC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESDEC_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VAESDECLAST_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESDECLAST_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VAESKEYGENASSIST_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPCLMULQDQ_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCLMULQDQ_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVD_VdqEd, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVD_VdqEdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqEbIb, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::PINSRW_VdqEwIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPINSRD_VdqEdIb, &BX_CPU_C::PINSRD_VdqEdIbM, &BX_CPU_C::PINSRD_VdqEdIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPINSRQ_VdqEqIb, &BX_CPU_C::PINSRD_VdqEdIbM, &BX_CPU_C::PINSRD_VdqEdIbR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, &BX_CPU_C::PEXTRB_EbdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_CPU_C::PEXTRW_EwdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VPEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTPS2PD_VpdWps, &BX_CPU_C::LOAD_VectorQ, &BX_CPU_C::VCVTPS2PD_VpdWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPD2DQ_VqWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2DQ_VqWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTDQ2PD_VpdWq, &BX_CPU_C::LOAD_VectorQ, &BX_CPU_C::VCVTDQ2PD_VpdWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTPD2PS_VpsWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2PS_VpsWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2SS_VssWsdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2SD_VsdWssR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTDQ2PS_VpsWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTDQ2PS_VpsWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPS2DQ_VdqWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPS2DQ_VdqWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTSI2SD_VsdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTSI2SD_VsdEdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTSI2SS_VssEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTSI2SS_VssEdR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTSI2SD_VsdEqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTSI2SS_VssEqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GqWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VMOVQ_WqVq, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::MOVQ_VqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV) /* dstRM */
bx_define_opcode(BX_IA_VMOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V128_VMOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVQ_EqVq, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::MOVQ_EqVqR, BX_CPU_AVX, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTPH2PS_VpsWps, &BX_CPU_C::LOAD_VectorQ, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_CPU_AVX_F16C, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, BX_CPU_AVX_F16C, BX_PREPARE_AVX | BX_VEX_NO_VVV)
// AVX
// AVX2
bx_define_opcode(BX_IA_V256_VPCMPEQB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPCMPEQW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPCMPEQD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPCMPEQQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPEQQ_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPCMPGTB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPCMPGTW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPCMPGTD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPCMPGTQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCMPGTQ_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMINSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMINSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMINSD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINSD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMINUB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMINUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMINUD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMINUD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMAXSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMAXSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMAXSD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXSD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMAXUB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMAXUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMAXUD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMAXUD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSIGNB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGNB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSIGNW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGNW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSIGND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSIGND_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPANDN_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsHpsWpsR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPAND_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsHpsWpsR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsHpsWpsR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPXOR_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsHpsWpsR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSUBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSUBQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBQ_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPADDB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPADDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPABSB_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSB_VdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VPABSW_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSW_VdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VPABSD_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPABSD_VdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VPSUBSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBSB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBSW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPADDSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDSB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPADDSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDSW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSUBUSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBUSB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSUBUSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBUSW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPADDUSB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDUSB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPADDUSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPADDUSW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPAVGB_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPAVGB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPAVGW_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPAVGW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPHADDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPHADDD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPHSUBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPHSUBD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPHADDSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHADDSW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPHSUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPHSUBSW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFHW_VdqWdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFLW_VdqWdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VPACKSSWB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKSSWB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPACKUSWB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKUSWB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPACKUSDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKUSDW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPACKSSDW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPACKSSDW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPUNPCKLBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKLBW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPUNPCKLWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKLWD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPUNPCKHBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKHBW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPUNPCKHWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPUNPCKHWD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMULLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULLW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMULHW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHUW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMULDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULDQ_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMULUDQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULUDQ_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMULHRSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMULHRSW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMADDUBSW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDUBSW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMADDWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDWD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMPSADBW_VdqHdqWdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPBLENDVB_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPBLENDW_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDW_VdqHdqWdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSHUFB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSHUFB_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VPSRLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSRLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSRLQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLQ_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSRAW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSRAD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSLLW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLW_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSLLD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSLLQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLQ_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSRLW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLW_UdqIb, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSRAW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAW_UdqIb, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSLLW_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLW_UdqIb, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSRLD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLD_UdqIb, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSRAD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAD_UdqIb, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSLLD_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLD_UdqIb, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSRLQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLQ_UdqIb, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSLLQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLQ_UdqIb, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSRLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLDQ_UdqIb, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSLLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLDQ_UdqIb, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPALIGNR_VdqHdqWdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VPMOVSXBW256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXBW256_VdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVSXBD256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXBD256_VdqWqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVSXBQ256_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVSXBQ256_VdqWdR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVSXWD256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXWD256_VdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVSXWQ256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXWQ256_VdqWqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVSXDQ256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXDQ256_VdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXBW256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXBW256_VdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXBD256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXBD256_VdqWqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXBQ256_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVZXBQ256_VdqWdR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXWD256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXWD256_VdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXWQ256_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXWQ256_VdqWqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPMOVZXDQ256_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXDQ256_VdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VPERM2I128_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqHdqWdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VINSERTI128_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VEXTRACTI128_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_V256_VBROADCASTI128_VdqMdq, &BX_CPU_C::VBROADCASTF128_VdqMdq, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPBROADCASTB_VdqWb, &BX_CPU_C::LOAD_Wb, &BX_CPU_C::VPBROADCASTB_VdqWb, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPBROADCASTW_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::VPBROADCASTW_VdqWw, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPBROADCASTD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPBROADCASTD_VdqWd, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPBROADCASTQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWq, BX_CPU_AVX2, BX_PREPARE_AVX | BX_VEX_NO_VVV)
bx_define_opcode(BX_IA_VPBLENDD_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsHpsWpsIbR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMASKMOVD_VdqHdqMdq, &BX_CPU_C::VMASKMOVPS_VpsHpsMps, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMASKMOVQ_VdqHdqMdq, &BX_CPU_C::VMASKMOVPD_VpdHpdMpd, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMASKMOVD_MdqHdqVdq, &BX_CPU_C::VMASKMOVPS_MpsHpsVps, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMASKMOVQ_MdqHdqVdq, &BX_CPU_C::VMASKMOVPD_MpdHpdVpd, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPERMQ_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMQ_VdqWdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPERMD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPERMPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPERMPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMQ_VdqWdqIbR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VPSRAVD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRAVD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VPSLLVD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLVD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VPSLLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLVQ_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VPSRLVD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLVD_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VPSRLVQ_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSRLVQ_VdqHdqWdqR, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VGATHERDPS_VpsHps, &BX_CPU_C::VGATHERDPS_VpsHps, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VGATHERQPS_VpsHps, &BX_CPU_C::VGATHERQPS_VpsHps, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VGATHERDPD_VpdHpd, &BX_CPU_C::VGATHERDPD_VpdHpd, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VGATHERQPD_VpdHpd, &BX_CPU_C::VGATHERQPD_VpdHpd, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VGATHERDD_VdqHdq, &BX_CPU_C::VGATHERDPS_VpsHps, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VGATHERQD_VdqHdq, &BX_CPU_C::VGATHERQPS_VpsHps, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VGATHERDQ_VdqHdq, &BX_CPU_C::VGATHERDPD_VpdHpd, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VGATHERQQ_VdqHdq, &BX_CPU_C::VGATHERQPD_VpdHpd, &BX_CPU_C::BxError, BX_CPU_AVX2, BX_PREPARE_AVX)
// AVX2
// BMI1
bx_define_opcode(BX_IA_ANDN_GdBdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::ANDN_GdBdEdR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_BLSI_BdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::BLSI_BdEdR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_BLSMSK_BdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::BLSMSK_BdEdR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_BLSR_BdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::BLSR_BdEdR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_BEXTR_GdEdBd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::BEXTR_GdEdBdR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_ANDN_GqBqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ANDN_GqBqEqR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_BLSI_BqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::BLSI_BqEqR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_BLSMSK_BqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::BLSMSK_BqEqR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_BLSR_BqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::BLSR_BqEqR, BX_CPU_BMI1, 0)
bx_define_opcode(BX_IA_BEXTR_GqEqBq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::BEXTR_GqEqBqR, BX_CPU_BMI1, 0)
// BMI1
// BMI2
bx_define_opcode(BX_IA_MULX_GdBdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::MULX_GdBdEdR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_RORX_GdEdIb, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::RORX_GdEdIbR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_SHLX_GdEdBd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::SHLX_GdEdBdR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_SHRX_GdEdBd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::SHRX_GdEdBdR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_SARX_GdEdBd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::SARX_GdEdBdR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_BZHI_GdEdBd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::BZHI_GdEdBdR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_PEXT_GdEdBd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::PEXT_GdEdBdR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_PDEP_GdEdBd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::PDEP_GdEdBdR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_MULX_GqBqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::MULX_GqBqEqR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_RORX_GqEqIb, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::RORX_GqEqIbR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_SHLX_GqEqBq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::SHLX_GqEqBqR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_SHRX_GqEqBq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::SHRX_GqEqBqR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_SARX_GqEqBq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::SARX_GqEqBqR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_BZHI_GqEqBq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::BZHI_GqEqBqR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_PEXT_GqEqBq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::PEXT_GqEqBqR, BX_CPU_BMI2, 0)
bx_define_opcode(BX_IA_PDEP_GqEqBq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::PDEP_GqEqBqR, BX_CPU_BMI2, 0)
// BMI2
#endif

11
bochs/cpu/load.cc
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@ -56,6 +56,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Eq(bxInstruction_c *i)
}
#endif
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wb(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16u val_8 = read_virtual_byte(i->seg(), eaddr);
BX_WRITE_XMM_REG_LO_BYTE(BX_TMP_REGISTER, val_8);
return BX_CPU_CALL_METHOD(i->execute2, (i));
#endif
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Ww(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6

1351
bochs/cpu/simd_int.h Normal file
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File diff suppressed because it is too large Load Diff

342
bochs/cpu/simd_pfp.h Normal file
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@ -0,0 +1,342 @@
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
//
/////////////////////////////////////////////////////////////////////////
#ifndef BX_SIMD_PFP_FUNCTIONS_H
#define BX_SIMD_PFP_FUNCTIONS_H
// arithmetic add/sub/mul/div
BX_CPP_INLINE void sse_addps(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm32u(0) = float32_denormal_to_zero(op1->xmm32u(0));
op1->xmm32u(1) = float32_denormal_to_zero(op1->xmm32u(1));
op1->xmm32u(2) = float32_denormal_to_zero(op1->xmm32u(2));
op1->xmm32u(3) = float32_denormal_to_zero(op1->xmm32u(3));
op2->xmm32u(0) = float32_denormal_to_zero(op2->xmm32u(0));
op2->xmm32u(1) = float32_denormal_to_zero(op2->xmm32u(1));
op2->xmm32u(2) = float32_denormal_to_zero(op2->xmm32u(2));
op2->xmm32u(3) = float32_denormal_to_zero(op2->xmm32u(3));
}
op1->xmm32u(0) = float32_add(op1->xmm32u(0), op2->xmm32u(0), status);
op1->xmm32u(1) = float32_add(op1->xmm32u(1), op2->xmm32u(1), status);
op1->xmm32u(2) = float32_add(op1->xmm32u(2), op2->xmm32u(2), status);
op1->xmm32u(3) = float32_add(op1->xmm32u(3), op2->xmm32u(3), status);
}
BX_CPP_INLINE void sse_addpd(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm64u(0) = float64_denormal_to_zero(op1->xmm64u(0));
op1->xmm64u(1) = float64_denormal_to_zero(op1->xmm64u(1));
op2->xmm64u(0) = float64_denormal_to_zero(op2->xmm64u(0));
op2->xmm64u(1) = float64_denormal_to_zero(op2->xmm64u(1));
}
op1->xmm64u(0) = float64_add(op1->xmm64u(0), op2->xmm64u(0), status);
op1->xmm64u(1) = float64_add(op1->xmm64u(1), op2->xmm64u(1), status);
}
BX_CPP_INLINE void sse_subps(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm32u(0) = float32_denormal_to_zero(op1->xmm32u(0));
op1->xmm32u(1) = float32_denormal_to_zero(op1->xmm32u(1));
op1->xmm32u(2) = float32_denormal_to_zero(op1->xmm32u(2));
op1->xmm32u(3) = float32_denormal_to_zero(op1->xmm32u(3));
op2->xmm32u(0) = float32_denormal_to_zero(op2->xmm32u(0));
op2->xmm32u(1) = float32_denormal_to_zero(op2->xmm32u(1));
op2->xmm32u(2) = float32_denormal_to_zero(op2->xmm32u(2));
op2->xmm32u(3) = float32_denormal_to_zero(op2->xmm32u(3));
}
op1->xmm32u(0) = float32_sub(op1->xmm32u(0), op2->xmm32u(0), status);
op1->xmm32u(1) = float32_sub(op1->xmm32u(1), op2->xmm32u(1), status);
op1->xmm32u(2) = float32_sub(op1->xmm32u(2), op2->xmm32u(2), status);
op1->xmm32u(3) = float32_sub(op1->xmm32u(3), op2->xmm32u(3), status);
}
BX_CPP_INLINE void sse_subpd(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm64u(0) = float64_denormal_to_zero(op1->xmm64u(0));
op1->xmm64u(1) = float64_denormal_to_zero(op1->xmm64u(1));
op2->xmm64u(0) = float64_denormal_to_zero(op2->xmm64u(0));
op2->xmm64u(1) = float64_denormal_to_zero(op2->xmm64u(1));
}
op1->xmm64u(0) = float64_sub(op1->xmm64u(0), op2->xmm64u(0), status);
op1->xmm64u(1) = float64_sub(op1->xmm64u(1), op2->xmm64u(1), status);
}
BX_CPP_INLINE void sse_mulps(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm32u(0) = float32_denormal_to_zero(op1->xmm32u(0));
op1->xmm32u(1) = float32_denormal_to_zero(op1->xmm32u(1));
op1->xmm32u(2) = float32_denormal_to_zero(op1->xmm32u(2));
op1->xmm32u(3) = float32_denormal_to_zero(op1->xmm32u(3));
op2->xmm32u(0) = float32_denormal_to_zero(op2->xmm32u(0));
op2->xmm32u(1) = float32_denormal_to_zero(op2->xmm32u(1));
op2->xmm32u(2) = float32_denormal_to_zero(op2->xmm32u(2));
op2->xmm32u(3) = float32_denormal_to_zero(op2->xmm32u(3));
}
op1->xmm32u(0) = float32_mul(op1->xmm32u(0), op2->xmm32u(0), status);
op1->xmm32u(1) = float32_mul(op1->xmm32u(1), op2->xmm32u(1), status);
op1->xmm32u(2) = float32_mul(op1->xmm32u(2), op2->xmm32u(2), status);
op1->xmm32u(3) = float32_mul(op1->xmm32u(3), op2->xmm32u(3), status);
}
BX_CPP_INLINE void sse_mulpd(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm64u(0) = float64_denormal_to_zero(op1->xmm64u(0));
op1->xmm64u(1) = float64_denormal_to_zero(op1->xmm64u(1));
op2->xmm64u(0) = float64_denormal_to_zero(op2->xmm64u(0));
op2->xmm64u(1) = float64_denormal_to_zero(op2->xmm64u(1));
}
op1->xmm64u(0) = float64_mul(op1->xmm64u(0), op2->xmm64u(0), status);
op1->xmm64u(1) = float64_mul(op1->xmm64u(1), op2->xmm64u(1), status);
}
BX_CPP_INLINE void sse_divps(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm32u(0) = float32_denormal_to_zero(op1->xmm32u(0));
op1->xmm32u(1) = float32_denormal_to_zero(op1->xmm32u(1));
op1->xmm32u(2) = float32_denormal_to_zero(op1->xmm32u(2));
op1->xmm32u(3) = float32_denormal_to_zero(op1->xmm32u(3));
op2->xmm32u(0) = float32_denormal_to_zero(op2->xmm32u(0));
op2->xmm32u(1) = float32_denormal_to_zero(op2->xmm32u(1));
op2->xmm32u(2) = float32_denormal_to_zero(op2->xmm32u(2));
op2->xmm32u(3) = float32_denormal_to_zero(op2->xmm32u(3));
}
op1->xmm32u(0) = float32_div(op1->xmm32u(0), op2->xmm32u(0), status);
op1->xmm32u(1) = float32_div(op1->xmm32u(1), op2->xmm32u(1), status);
op1->xmm32u(2) = float32_div(op1->xmm32u(2), op2->xmm32u(2), status);
op1->xmm32u(3) = float32_div(op1->xmm32u(3), op2->xmm32u(3), status);
}
BX_CPP_INLINE void sse_divpd(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm64u(0) = float64_denormal_to_zero(op1->xmm64u(0));
op1->xmm64u(1) = float64_denormal_to_zero(op1->xmm64u(1));
op2->xmm64u(0) = float64_denormal_to_zero(op2->xmm64u(0));
op2->xmm64u(1) = float64_denormal_to_zero(op2->xmm64u(1));
}
op1->xmm64u(0) = float64_div(op1->xmm64u(0), op2->xmm64u(0), status);
op1->xmm64u(1) = float64_div(op1->xmm64u(1), op2->xmm64u(1), status);
}
BX_CPP_INLINE void sse_addsubps(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm32u(0) = float32_denormal_to_zero(op1->xmm32u(0));
op1->xmm32u(1) = float32_denormal_to_zero(op1->xmm32u(1));
op1->xmm32u(2) = float32_denormal_to_zero(op1->xmm32u(2));
op1->xmm32u(3) = float32_denormal_to_zero(op1->xmm32u(3));
op2->xmm32u(0) = float32_denormal_to_zero(op2->xmm32u(0));
op2->xmm32u(1) = float32_denormal_to_zero(op2->xmm32u(1));
op2->xmm32u(2) = float32_denormal_to_zero(op2->xmm32u(2));
op2->xmm32u(3) = float32_denormal_to_zero(op2->xmm32u(3));
}
op1->xmm32u(0) = float32_sub(op1->xmm32u(0), op2->xmm32u(0), status);
op1->xmm32u(1) = float32_add(op1->xmm32u(1), op2->xmm32u(1), status);
op1->xmm32u(2) = float32_sub(op1->xmm32u(2), op2->xmm32u(2), status);
op1->xmm32u(3) = float32_add(op1->xmm32u(3), op2->xmm32u(3), status);
}
BX_CPP_INLINE void sse_addsubpd(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm64u(0) = float64_denormal_to_zero(op1->xmm64u(0));
op1->xmm64u(1) = float64_denormal_to_zero(op1->xmm64u(1));
op2->xmm64u(0) = float64_denormal_to_zero(op2->xmm64u(0));
op2->xmm64u(1) = float64_denormal_to_zero(op2->xmm64u(1));
}
op1->xmm64u(0) = float64_sub(op1->xmm64u(0), op2->xmm64u(0), status);
op1->xmm64u(1) = float64_add(op1->xmm64u(1), op2->xmm64u(1), status);
}
// horizontal arithmetic add/sub
BX_CPP_INLINE void sse_haddps(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm32u(0) = float32_denormal_to_zero(op1->xmm32u(0));
op1->xmm32u(1) = float32_denormal_to_zero(op1->xmm32u(1));
op1->xmm32u(2) = float32_denormal_to_zero(op1->xmm32u(2));
op1->xmm32u(3) = float32_denormal_to_zero(op1->xmm32u(3));
op2->xmm32u(0) = float32_denormal_to_zero(op2->xmm32u(0));
op2->xmm32u(1) = float32_denormal_to_zero(op2->xmm32u(1));
op2->xmm32u(2) = float32_denormal_to_zero(op2->xmm32u(2));
op2->xmm32u(3) = float32_denormal_to_zero(op2->xmm32u(3));
}
op1->xmm32u(0) = float32_add(op1->xmm32u(0), op1->xmm32u(1), status);
op1->xmm32u(1) = float32_add(op1->xmm32u(2), op1->xmm32u(3), status);
op1->xmm32u(2) = float32_add(op2->xmm32u(0), op2->xmm32u(1), status);
op1->xmm32u(3) = float32_add(op2->xmm32u(2), op2->xmm32u(3), status);
}
BX_CPP_INLINE void sse_haddpd(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm64u(0) = float64_denormal_to_zero(op1->xmm64u(0));
op1->xmm64u(1) = float64_denormal_to_zero(op1->xmm64u(1));
op2->xmm64u(0) = float64_denormal_to_zero(op2->xmm64u(0));
op2->xmm64u(1) = float64_denormal_to_zero(op2->xmm64u(1));
}
op1->xmm64u(0) = float64_add(op1->xmm64u(0), op1->xmm64u(1), status);
op1->xmm64u(1) = float64_add(op2->xmm64u(0), op2->xmm64u(1), status);
}
BX_CPP_INLINE void sse_hsubps(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm32u(0) = float32_denormal_to_zero(op1->xmm32u(0));
op1->xmm32u(1) = float32_denormal_to_zero(op1->xmm32u(1));
op1->xmm32u(2) = float32_denormal_to_zero(op1->xmm32u(2));
op1->xmm32u(3) = float32_denormal_to_zero(op1->xmm32u(3));
op2->xmm32u(0) = float32_denormal_to_zero(op2->xmm32u(0));
op2->xmm32u(1) = float32_denormal_to_zero(op2->xmm32u(1));
op2->xmm32u(2) = float32_denormal_to_zero(op2->xmm32u(2));
op2->xmm32u(3) = float32_denormal_to_zero(op2->xmm32u(3));
}
op1->xmm32u(0) = float32_sub(op1->xmm32u(0), op1->xmm32u(1), status);
op1->xmm32u(1) = float32_sub(op1->xmm32u(2), op1->xmm32u(3), status);
op1->xmm32u(2) = float32_sub(op2->xmm32u(0), op2->xmm32u(1), status);
op1->xmm32u(3) = float32_sub(op2->xmm32u(2), op2->xmm32u(3), status);
}
BX_CPP_INLINE void sse_hsubpd(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm64u(0) = float64_denormal_to_zero(op1->xmm64u(0));
op1->xmm64u(1) = float64_denormal_to_zero(op1->xmm64u(1));
op2->xmm64u(0) = float64_denormal_to_zero(op2->xmm64u(0));
op2->xmm64u(1) = float64_denormal_to_zero(op2->xmm64u(1));
}
op1->xmm64u(0) = float64_sub(op1->xmm64u(0), op1->xmm64u(1), status);
op1->xmm64u(1) = float64_sub(op2->xmm64u(0), op2->xmm64u(1), status);
}
// min/max
BX_CPP_INLINE void sse_minps(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm32u(0) = float32_denormal_to_zero(op1->xmm32u(0));
op1->xmm32u(1) = float32_denormal_to_zero(op1->xmm32u(1));
op1->xmm32u(2) = float32_denormal_to_zero(op1->xmm32u(2));
op1->xmm32u(3) = float32_denormal_to_zero(op1->xmm32u(3));
op2->xmm32u(0) = float32_denormal_to_zero(op2->xmm32u(0));
op2->xmm32u(1) = float32_denormal_to_zero(op2->xmm32u(1));
op2->xmm32u(2) = float32_denormal_to_zero(op2->xmm32u(2));
op2->xmm32u(3) = float32_denormal_to_zero(op2->xmm32u(3));
}
int rc = float32_compare(op1->xmm32u(0), op2->xmm32u(0), status);
op1->xmm32u(0) = (rc == float_relation_less) ? op1->xmm32u(0) : op2->xmm32u(0);
rc = float32_compare(op1->xmm32u(1), op2->xmm32u(1), status);
op1->xmm32u(1) = (rc == float_relation_less) ? op1->xmm32u(1) : op2->xmm32u(1);
rc = float32_compare(op1->xmm32u(2), op2->xmm32u(2), status);
op1->xmm32u(2) = (rc == float_relation_less) ? op1->xmm32u(2) : op2->xmm32u(2);
rc = float32_compare(op1->xmm32u(3), op2->xmm32u(3), status);
op1->xmm32u(3) = (rc == float_relation_less) ? op1->xmm32u(3) : op2->xmm32u(3);
}
BX_CPP_INLINE void sse_minpd(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm64u(0) = float64_denormal_to_zero(op1->xmm64u(0));
op1->xmm64u(1) = float64_denormal_to_zero(op1->xmm64u(1));
op2->xmm64u(0) = float64_denormal_to_zero(op2->xmm64u(0));
op2->xmm64u(1) = float64_denormal_to_zero(op2->xmm64u(1));
}
int rc = float64_compare(op1->xmm64u(0), op2->xmm64u(0), status);
op1->xmm64u(0) = (rc == float_relation_less) ? op1->xmm64u(0) : op2->xmm64u(0);
rc = float64_compare(op1->xmm64u(1), op2->xmm64u(1), status);
op1->xmm64u(1) = (rc == float_relation_less) ? op1->xmm64u(1) : op2->xmm64u(1);
}
BX_CPP_INLINE void sse_maxps(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm32u(0) = float32_denormal_to_zero(op1->xmm32u(0));
op1->xmm32u(1) = float32_denormal_to_zero(op1->xmm32u(1));
op1->xmm32u(2) = float32_denormal_to_zero(op1->xmm32u(2));
op1->xmm32u(3) = float32_denormal_to_zero(op1->xmm32u(3));
op2->xmm32u(0) = float32_denormal_to_zero(op2->xmm32u(0));
op2->xmm32u(1) = float32_denormal_to_zero(op2->xmm32u(1));
op2->xmm32u(2) = float32_denormal_to_zero(op2->xmm32u(2));
op2->xmm32u(3) = float32_denormal_to_zero(op2->xmm32u(3));
}
int rc = float32_compare(op1->xmm32u(0), op2->xmm32u(0), status);
op1->xmm32u(0) = (rc == float_relation_greater) ? op1->xmm32u(0) : op2->xmm32u(0);
rc = float32_compare(op1->xmm32u(1), op2->xmm32u(1), status);
op1->xmm32u(1) = (rc == float_relation_greater) ? op1->xmm32u(1) : op2->xmm32u(1);
rc = float32_compare(op1->xmm32u(2), op2->xmm32u(2), status);
op1->xmm32u(2) = (rc == float_relation_greater) ? op1->xmm32u(2) : op2->xmm32u(2);
rc = float32_compare(op1->xmm32u(3), op2->xmm32u(3), status);
op1->xmm32u(3) = (rc == float_relation_greater) ? op1->xmm32u(3) : op2->xmm32u(3);
}
BX_CPP_INLINE void sse_maxpd(BxPackedXmmRegister *op1, BxPackedXmmRegister *op2, float_status_t &status, bx_bool mxcsr_daz)
{
if (mxcsr_daz) {
op1->xmm64u(0) = float64_denormal_to_zero(op1->xmm64u(0));
op1->xmm64u(1) = float64_denormal_to_zero(op1->xmm64u(1));
op2->xmm64u(0) = float64_denormal_to_zero(op2->xmm64u(0));
op2->xmm64u(1) = float64_denormal_to_zero(op2->xmm64u(1));
}
int rc = float64_compare(op1->xmm64u(0), op2->xmm64u(0), status);
op1->xmm64u(0) = (rc == float_relation_greater) ? op1->xmm64u(0) : op2->xmm64u(0);
rc = float64_compare(op1->xmm64u(1), op2->xmm64u(1), status);
op1->xmm64u(1) = (rc == float_relation_greater) ? op1->xmm64u(1) : op2->xmm64u(1);
}
#endif

2283
bochs/cpu/sse.cc
View File

File diff suppressed because it is too large Load Diff

94
bochs/cpu/sse_move.cc
View File

@ -28,6 +28,8 @@
#if BX_CPU_LEVEL >= 6
#include "simd_int.h"
void BX_CPU_C::print_state_SSE(void)
{
BX_DEBUG(("MXCSR: 0x%08x\n", BX_MXCSR_REGISTER));
@ -535,14 +537,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDDUP_VpdWqR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op;
Bit64u val64 = BX_READ_XMM_REG_LO_QWORD(i->rm());
op.xmm64u(0) = val64;
op.xmm64u(1) = val64;
BX_WRITE_XMM_REG(i->nnn(), op);
sse_pbroadcastq(&BX_XMM_REG(i->nnn()), BX_READ_XMM_REG_LO_QWORD(i->rm()));
#endif
BX_NEXT_INSTR(i);
@ -658,15 +653,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MASKMOVDQU_VdqUdq(bxInstruction_c
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
Bit32u val32 = 0;
if(op.xmm32u(0) & 0x80000000) val32 |= 0x1;
if(op.xmm32u(1) & 0x80000000) val32 |= 0x2;
if(op.xmm32u(2) & 0x80000000) val32 |= 0x4;
if(op.xmm32u(3) & 0x80000000) val32 |= 0x8;
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
Bit32u mask = sse_pmovmskd(&BX_XMM_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
#endif
BX_NEXT_INSTR(i);
@ -676,13 +664,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPD_GdVRpd(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
Bit32u val32 = 0;
if(op.xmm32u(1) & 0x80000000) val32 |= 0x1;
if(op.xmm32u(3) & 0x80000000) val32 |= 0x2;
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
Bit32u mask = sse_pmovmskq(&BX_XMM_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
#endif
BX_NEXT_INSTR(i);
@ -807,27 +790,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ2DQ_VdqQq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVMSKB_GdUdq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
Bit32u result = 0;
if(op.xmmubyte(0x0) & 0x80) result |= 0x0001;
if(op.xmmubyte(0x1) & 0x80) result |= 0x0002;
if(op.xmmubyte(0x2) & 0x80) result |= 0x0004;
if(op.xmmubyte(0x3) & 0x80) result |= 0x0008;
if(op.xmmubyte(0x4) & 0x80) result |= 0x0010;
if(op.xmmubyte(0x5) & 0x80) result |= 0x0020;
if(op.xmmubyte(0x6) & 0x80) result |= 0x0040;
if(op.xmmubyte(0x7) & 0x80) result |= 0x0080;
if(op.xmmubyte(0x8) & 0x80) result |= 0x0100;
if(op.xmmubyte(0x9) & 0x80) result |= 0x0200;
if(op.xmmubyte(0xA) & 0x80) result |= 0x0400;
if(op.xmmubyte(0xB) & 0x80) result |= 0x0800;
if(op.xmmubyte(0xC) & 0x80) result |= 0x1000;
if(op.xmmubyte(0xD) & 0x80) result |= 0x2000;
if(op.xmmubyte(0xE) & 0x80) result |= 0x4000;
if(op.xmmubyte(0xF) & 0x80) result |= 0x8000;
BX_WRITE_32BIT_REGZ(i->nnn(), result);
Bit32u mask = sse_pmovmskb(&BX_XMM_REG(i->rm()));
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
#endif
BX_NEXT_INSTR(i);
@ -1057,45 +1021,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXDQ_VdqWqR(bxInstruction_c *i
/* 66 0F 3A 0F */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm()), result;
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm());
unsigned shift = i->Ib() * 8;
sse_palignr(&op2, &op1, i->Ib());
if(shift == 0) {
result = op2;
}
else if(shift < 64) {
result.xmm64u(0) = (op2.xmm64u(0) >> shift) | (op2.xmm64u(1) << (64-shift));
result.xmm64u(1) = (op2.xmm64u(1) >> shift) | (op1.xmm64u(0) << (64-shift));
}
else if(shift == 64) {
result.xmm64u(0) = op2.xmm64u(1);
result.xmm64u(1) = op1.xmm64u(0);
}
else if(shift < 128) {
shift -= 64;
result.xmm64u(0) = (op2.xmm64u(1) >> shift) | (op1.xmm64u(0) << (64-shift));
result.xmm64u(1) = (op1.xmm64u(0) >> shift) | (op1.xmm64u(1) << (64-shift));
}
else if(shift == 128) {
result = op1;
}
else if(shift < 192) {
shift -= 128;
result.xmm64u(0) = (op1.xmm64u(0) >> shift) | (op1.xmm64u(1) << (64-shift));
result.xmm64u(1) = (op1.xmm64u(1) >> shift);
}
else if(shift < 256) {
result.xmm64u(0) = op1.xmm64u(1) >> (shift - 192);
result.xmm64u(1) = 0;
}
else {
result.xmm64u(0) = 0;
result.xmm64u(1) = 0;
}
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
BX_WRITE_XMM_REG(i->nnn(), op2);
BX_NEXT_INSTR(i);
}

324
bochs/cpu/sse_pfp.cc
View File

@ -31,6 +31,8 @@
#include "fpu/softfloat-compare.h"
#include "fpu/softfloat-specialize.h"
#include "simd_pfp.h"
void BX_CPU_C::check_exceptionsSSE(int exceptions_flags)
{
exceptions_flags &= MXCSR_EXCEPTIONS;
@ -1121,25 +1123,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDPS_VpsWpsR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ()) {
op1.xmm32u(0) = float32_denormal_to_zero(op1.xmm32u(0));
op1.xmm32u(1) = float32_denormal_to_zero(op1.xmm32u(1));
op1.xmm32u(2) = float32_denormal_to_zero(op1.xmm32u(2));
op1.xmm32u(3) = float32_denormal_to_zero(op1.xmm32u(3));
op2.xmm32u(0) = float32_denormal_to_zero(op2.xmm32u(0));
op2.xmm32u(1) = float32_denormal_to_zero(op2.xmm32u(1));
op2.xmm32u(2) = float32_denormal_to_zero(op2.xmm32u(2));
op2.xmm32u(3) = float32_denormal_to_zero(op2.xmm32u(3));
}
op1.xmm32u(0) = float32_add(op1.xmm32u(0), op2.xmm32u(0), status);
op1.xmm32u(1) = float32_add(op1.xmm32u(1), op2.xmm32u(1), status);
op1.xmm32u(2) = float32_add(op1.xmm32u(2), op2.xmm32u(2), status);
op1.xmm32u(3) = float32_add(op1.xmm32u(3), op2.xmm32u(3), status);
sse_addps(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1158,19 +1144,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDPD_VpdWpdR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ())
{
op1.xmm64u(0) = float64_denormal_to_zero(op1.xmm64u(0));
op1.xmm64u(1) = float64_denormal_to_zero(op1.xmm64u(1));
op2.xmm64u(0) = float64_denormal_to_zero(op2.xmm64u(0));
op2.xmm64u(1) = float64_denormal_to_zero(op2.xmm64u(1));
}
op1.xmm64u(0) = float64_add(op1.xmm64u(0), op2.xmm64u(0), status);
op1.xmm64u(1) = float64_add(op1.xmm64u(1), op2.xmm64u(1), status);
sse_addpd(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1243,25 +1219,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULPS_VpsWpsR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ()) {
op1.xmm32u(0) = float32_denormal_to_zero(op1.xmm32u(0));
op1.xmm32u(1) = float32_denormal_to_zero(op1.xmm32u(1));
op1.xmm32u(2) = float32_denormal_to_zero(op1.xmm32u(2));
op1.xmm32u(3) = float32_denormal_to_zero(op1.xmm32u(3));
op2.xmm32u(0) = float32_denormal_to_zero(op2.xmm32u(0));
op2.xmm32u(1) = float32_denormal_to_zero(op2.xmm32u(1));
op2.xmm32u(2) = float32_denormal_to_zero(op2.xmm32u(2));
op2.xmm32u(3) = float32_denormal_to_zero(op2.xmm32u(3));
}
op1.xmm32u(0) = float32_mul(op1.xmm32u(0), op2.xmm32u(0), status);
op1.xmm32u(1) = float32_mul(op1.xmm32u(1), op2.xmm32u(1), status);
op1.xmm32u(2) = float32_mul(op1.xmm32u(2), op2.xmm32u(2), status);
op1.xmm32u(3) = float32_mul(op1.xmm32u(3), op2.xmm32u(3), status);
sse_mulps(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1280,19 +1240,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULPD_VpdWpdR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ())
{
op1.xmm64u(0) = float64_denormal_to_zero(op1.xmm64u(0));
op1.xmm64u(1) = float64_denormal_to_zero(op1.xmm64u(1));
op2.xmm64u(0) = float64_denormal_to_zero(op2.xmm64u(0));
op2.xmm64u(1) = float64_denormal_to_zero(op2.xmm64u(1));
}
op1.xmm64u(0) = float64_mul(op1.xmm64u(0), op2.xmm64u(0), status);
op1.xmm64u(1) = float64_mul(op1.xmm64u(1), op2.xmm64u(1), status);
sse_mulpd(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1365,25 +1315,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBPS_VpsWpsR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ()) {
op1.xmm32u(0) = float32_denormal_to_zero(op1.xmm32u(0));
op1.xmm32u(1) = float32_denormal_to_zero(op1.xmm32u(1));
op1.xmm32u(2) = float32_denormal_to_zero(op1.xmm32u(2));
op1.xmm32u(3) = float32_denormal_to_zero(op1.xmm32u(3));
op2.xmm32u(0) = float32_denormal_to_zero(op2.xmm32u(0));
op2.xmm32u(1) = float32_denormal_to_zero(op2.xmm32u(1));
op2.xmm32u(2) = float32_denormal_to_zero(op2.xmm32u(2));
op2.xmm32u(3) = float32_denormal_to_zero(op2.xmm32u(3));
}
op1.xmm32u(0) = float32_sub(op1.xmm32u(0), op2.xmm32u(0), status);
op1.xmm32u(1) = float32_sub(op1.xmm32u(1), op2.xmm32u(1), status);
op1.xmm32u(2) = float32_sub(op1.xmm32u(2), op2.xmm32u(2), status);
op1.xmm32u(3) = float32_sub(op1.xmm32u(3), op2.xmm32u(3), status);
sse_subps(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1402,19 +1336,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBPD_VpdWpdR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ())
{
op1.xmm64u(0) = float64_denormal_to_zero(op1.xmm64u(0));
op1.xmm64u(1) = float64_denormal_to_zero(op1.xmm64u(1));
op2.xmm64u(0) = float64_denormal_to_zero(op2.xmm64u(0));
op2.xmm64u(1) = float64_denormal_to_zero(op2.xmm64u(1));
}
op1.xmm64u(0) = float64_sub(op1.xmm64u(0), op2.xmm64u(0), status);
op1.xmm64u(1) = float64_sub(op1.xmm64u(1), op2.xmm64u(1), status);
sse_subpd(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1487,30 +1411,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MINPS_VpsWpsR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
int rc;
if (MXCSR.get_DAZ()) {
op1.xmm32u(0) = float32_denormal_to_zero(op1.xmm32u(0));
op1.xmm32u(1) = float32_denormal_to_zero(op1.xmm32u(1));
op1.xmm32u(2) = float32_denormal_to_zero(op1.xmm32u(2));
op1.xmm32u(3) = float32_denormal_to_zero(op1.xmm32u(3));
op2.xmm32u(0) = float32_denormal_to_zero(op2.xmm32u(0));
op2.xmm32u(1) = float32_denormal_to_zero(op2.xmm32u(1));
op2.xmm32u(2) = float32_denormal_to_zero(op2.xmm32u(2));
op2.xmm32u(3) = float32_denormal_to_zero(op2.xmm32u(3));
}
rc = float32_compare(op1.xmm32u(0), op2.xmm32u(0), status);
op1.xmm32u(0) = (rc == float_relation_less) ? op1.xmm32u(0) : op2.xmm32u(0);
rc = float32_compare(op1.xmm32u(1), op2.xmm32u(1), status);
op1.xmm32u(1) = (rc == float_relation_less) ? op1.xmm32u(1) : op2.xmm32u(1);
rc = float32_compare(op1.xmm32u(2), op2.xmm32u(2), status);
op1.xmm32u(2) = (rc == float_relation_less) ? op1.xmm32u(2) : op2.xmm32u(2);
rc = float32_compare(op1.xmm32u(3), op2.xmm32u(3), status);
op1.xmm32u(3) = (rc == float_relation_less) ? op1.xmm32u(3) : op2.xmm32u(3);
sse_minps(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1529,22 +1432,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MINPD_VpdWpdR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
int rc;
if (MXCSR.get_DAZ())
{
op1.xmm64u(0) = float64_denormal_to_zero(op1.xmm64u(0));
op1.xmm64u(1) = float64_denormal_to_zero(op1.xmm64u(1));
op2.xmm64u(0) = float64_denormal_to_zero(op2.xmm64u(0));
op2.xmm64u(1) = float64_denormal_to_zero(op2.xmm64u(1));
}
rc = float64_compare(op1.xmm64u(0), op2.xmm64u(0), status);
op1.xmm64u(0) = (rc == float_relation_less) ? op1.xmm64u(0) : op2.xmm64u(0);
rc = float64_compare(op1.xmm64u(1), op2.xmm64u(1), status);
op1.xmm64u(1) = (rc == float_relation_less) ? op1.xmm64u(1) : op2.xmm64u(1);
sse_minpd(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1619,25 +1509,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVPS_VpsWpsR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ()) {
op1.xmm32u(0) = float32_denormal_to_zero(op1.xmm32u(0));
op1.xmm32u(1) = float32_denormal_to_zero(op1.xmm32u(1));
op1.xmm32u(2) = float32_denormal_to_zero(op1.xmm32u(2));
op1.xmm32u(3) = float32_denormal_to_zero(op1.xmm32u(3));
op2.xmm32u(0) = float32_denormal_to_zero(op2.xmm32u(0));
op2.xmm32u(1) = float32_denormal_to_zero(op2.xmm32u(1));
op2.xmm32u(2) = float32_denormal_to_zero(op2.xmm32u(2));
op2.xmm32u(3) = float32_denormal_to_zero(op2.xmm32u(3));
}
op1.xmm32u(0) = float32_div(op1.xmm32u(0), op2.xmm32u(0), status);
op1.xmm32u(1) = float32_div(op1.xmm32u(1), op2.xmm32u(1), status);
op1.xmm32u(2) = float32_div(op1.xmm32u(2), op2.xmm32u(2), status);
op1.xmm32u(3) = float32_div(op1.xmm32u(3), op2.xmm32u(3), status);
sse_divps(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1656,19 +1530,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVPD_VpdWpdR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ())
{
op1.xmm64u(0) = float64_denormal_to_zero(op1.xmm64u(0));
op1.xmm64u(1) = float64_denormal_to_zero(op1.xmm64u(1));
op2.xmm64u(0) = float64_denormal_to_zero(op2.xmm64u(0));
op2.xmm64u(1) = float64_denormal_to_zero(op2.xmm64u(1));
}
op1.xmm64u(0) = float64_div(op1.xmm64u(0), op2.xmm64u(0), status);
op1.xmm64u(1) = float64_div(op1.xmm64u(1), op2.xmm64u(1), status);
sse_divpd(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1741,30 +1605,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXPS_VpsWpsR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
int rc;
if (MXCSR.get_DAZ()) {
op1.xmm32u(0) = float32_denormal_to_zero(op1.xmm32u(0));
op1.xmm32u(1) = float32_denormal_to_zero(op1.xmm32u(1));
op1.xmm32u(2) = float32_denormal_to_zero(op1.xmm32u(2));
op1.xmm32u(3) = float32_denormal_to_zero(op1.xmm32u(3));
op2.xmm32u(0) = float32_denormal_to_zero(op2.xmm32u(0));
op2.xmm32u(1) = float32_denormal_to_zero(op2.xmm32u(1));
op2.xmm32u(2) = float32_denormal_to_zero(op2.xmm32u(2));
op2.xmm32u(3) = float32_denormal_to_zero(op2.xmm32u(3));
}
rc = float32_compare(op1.xmm32u(0), op2.xmm32u(0), status);
op1.xmm32u(0) = (rc == float_relation_greater) ? op1.xmm32u(0) : op2.xmm32u(0);
rc = float32_compare(op1.xmm32u(1), op2.xmm32u(1), status);
op1.xmm32u(1) = (rc == float_relation_greater) ? op1.xmm32u(1) : op2.xmm32u(1);
rc = float32_compare(op1.xmm32u(2), op2.xmm32u(2), status);
op1.xmm32u(2) = (rc == float_relation_greater) ? op1.xmm32u(2) : op2.xmm32u(2);
rc = float32_compare(op1.xmm32u(3), op2.xmm32u(3), status);
op1.xmm32u(3) = (rc == float_relation_greater) ? op1.xmm32u(3) : op2.xmm32u(3);
sse_maxps(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1783,22 +1626,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXPD_VpdWpdR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
int rc;
if (MXCSR.get_DAZ())
{
op1.xmm64u(0) = float64_denormal_to_zero(op1.xmm64u(0));
op1.xmm64u(1) = float64_denormal_to_zero(op1.xmm64u(1));
op2.xmm64u(0) = float64_denormal_to_zero(op2.xmm64u(0));
op2.xmm64u(1) = float64_denormal_to_zero(op2.xmm64u(1));
}
rc = float64_compare(op1.xmm64u(0), op2.xmm64u(0), status);
op1.xmm64u(0) = (rc == float_relation_greater) ? op1.xmm64u(0) : op2.xmm64u(0);
rc = float64_compare(op1.xmm64u(1), op2.xmm64u(1), status);
op1.xmm64u(1) = (rc == float_relation_greater) ? op1.xmm64u(1) : op2.xmm64u(1);
sse_maxpd(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1873,19 +1703,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::HADDPD_VpdWpdR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ())
{
op1.xmm64u(0) = float64_denormal_to_zero(op1.xmm64u(0));
op1.xmm64u(1) = float64_denormal_to_zero(op1.xmm64u(1));
op2.xmm64u(0) = float64_denormal_to_zero(op2.xmm64u(0));
op2.xmm64u(1) = float64_denormal_to_zero(op2.xmm64u(1));
}
op1.xmm64u(0) = float64_add(op1.xmm64u(0), op1.xmm64u(1), status);
op1.xmm64u(1) = float64_add(op2.xmm64u(0), op2.xmm64u(1), status);
sse_haddpd(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1904,25 +1724,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::HADDPS_VpsWpsR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ()) {
op1.xmm32u(0) = float32_denormal_to_zero(op1.xmm32u(0));
op1.xmm32u(1) = float32_denormal_to_zero(op1.xmm32u(1));
op1.xmm32u(2) = float32_denormal_to_zero(op1.xmm32u(2));
op1.xmm32u(3) = float32_denormal_to_zero(op1.xmm32u(3));
op2.xmm32u(0) = float32_denormal_to_zero(op2.xmm32u(0));
op2.xmm32u(1) = float32_denormal_to_zero(op2.xmm32u(1));
op2.xmm32u(2) = float32_denormal_to_zero(op2.xmm32u(2));
op2.xmm32u(3) = float32_denormal_to_zero(op2.xmm32u(3));
}
op1.xmm32u(0) = float32_add(op1.xmm32u(0), op1.xmm32u(1), status);
op1.xmm32u(1) = float32_add(op1.xmm32u(2), op1.xmm32u(3), status);
op1.xmm32u(2) = float32_add(op2.xmm32u(0), op2.xmm32u(1), status);
op1.xmm32u(3) = float32_add(op2.xmm32u(2), op2.xmm32u(3), status);
sse_haddps(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1941,19 +1745,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::HSUBPD_VpdWpdR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ())
{
op1.xmm64u(0) = float64_denormal_to_zero(op1.xmm64u(0));
op1.xmm64u(1) = float64_denormal_to_zero(op1.xmm64u(1));
op2.xmm64u(0) = float64_denormal_to_zero(op2.xmm64u(0));
op2.xmm64u(1) = float64_denormal_to_zero(op2.xmm64u(1));
}
op1.xmm64u(0) = float64_sub(op1.xmm64u(0), op1.xmm64u(1), status);
op1.xmm64u(1) = float64_sub(op2.xmm64u(0), op2.xmm64u(1), status);
sse_hsubpd(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -1972,25 +1766,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::HSUBPS_VpsWpsR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ()) {
op1.xmm32u(0) = float32_denormal_to_zero(op1.xmm32u(0));
op1.xmm32u(1) = float32_denormal_to_zero(op1.xmm32u(1));
op1.xmm32u(2) = float32_denormal_to_zero(op1.xmm32u(2));
op1.xmm32u(3) = float32_denormal_to_zero(op1.xmm32u(3));
op2.xmm32u(0) = float32_denormal_to_zero(op2.xmm32u(0));
op2.xmm32u(1) = float32_denormal_to_zero(op2.xmm32u(1));
op2.xmm32u(2) = float32_denormal_to_zero(op2.xmm32u(2));
op2.xmm32u(3) = float32_denormal_to_zero(op2.xmm32u(3));
}
op1.xmm32u(0) = float32_sub(op1.xmm32u(0), op1.xmm32u(1), status);
op1.xmm32u(1) = float32_sub(op1.xmm32u(2), op1.xmm32u(3), status);
op1.xmm32u(2) = float32_sub(op2.xmm32u(0), op2.xmm32u(1), status);
op1.xmm32u(3) = float32_sub(op2.xmm32u(2), op2.xmm32u(3), status);
sse_hsubps(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -2143,19 +1921,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSUBPD_VpdWpdR(bxInstruction_c *
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ())
{
op1.xmm64u(0) = float64_denormal_to_zero(op1.xmm64u(0));
op1.xmm64u(1) = float64_denormal_to_zero(op1.xmm64u(1));
op2.xmm64u(0) = float64_denormal_to_zero(op2.xmm64u(0));
op2.xmm64u(1) = float64_denormal_to_zero(op2.xmm64u(1));
}
op1.xmm64u(0) = float64_sub(op1.xmm64u(0), op2.xmm64u(0), status);
op1.xmm64u(1) = float64_add(op1.xmm64u(1), op2.xmm64u(1), status);
sse_addsubpd(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif
@ -2174,25 +1942,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSUBPS_VpsWpsR(bxInstruction_c *
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
if (MXCSR.get_DAZ()) {
op1.xmm32u(0) = float32_denormal_to_zero(op1.xmm32u(0));
op1.xmm32u(1) = float32_denormal_to_zero(op1.xmm32u(1));
op1.xmm32u(2) = float32_denormal_to_zero(op1.xmm32u(2));
op1.xmm32u(3) = float32_denormal_to_zero(op1.xmm32u(3));
op2.xmm32u(0) = float32_denormal_to_zero(op2.xmm32u(0));
op2.xmm32u(1) = float32_denormal_to_zero(op2.xmm32u(1));
op2.xmm32u(2) = float32_denormal_to_zero(op2.xmm32u(2));
op2.xmm32u(3) = float32_denormal_to_zero(op2.xmm32u(3));
}
op1.xmm32u(0) = float32_sub(op1.xmm32u(0), op2.xmm32u(0), status);
op1.xmm32u(1) = float32_add(op1.xmm32u(1), op2.xmm32u(1), status);
op1.xmm32u(2) = float32_sub(op1.xmm32u(2), op2.xmm32u(2), status);
op1.xmm32u(3) = float32_add(op1.xmm32u(3), op2.xmm32u(3), status);
sse_addsubps(&op1, &op2, status, MXCSR.get_DAZ());
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
#endif

2
bochs/cpu/todo
View File

@ -47,6 +47,6 @@ TODO (know issues in CPU model):
- Dual-monitor treatment of SMIs and SMM not implemented yet
- VMENTER to not-active state not supported yet
[!] SMX, SVM, XOP, AVX2
[!] SMX, FMA, SVM, XOP, TBM
[!] TODO: Convert CPUDB to plugins and search for them in runtime

10
bochs/cpu/xmm.h
View File

@ -143,6 +143,10 @@ typedef union bx_avx_reg_t {
#define BX_READ_XMM_REG_LO_WORD(index) \
((BX_READ_XMM_REG(index)).xmm16u(0))
/* read only low 8 bit of the register */
#define BX_READ_XMM_REG_LO_BYTE(index) \
((BX_READ_XMM_REG(index)).xmmubyte(0))
/* short names for above macroses */
#define BX_XMM_REG_HI_QWORD BX_READ_XMM_REG_HI_QWORD
#define BX_XMM_REG_LO_QWORD BX_READ_XMM_REG_LO_QWORD
@ -166,6 +170,10 @@ typedef union bx_avx_reg_t {
#define BX_WRITE_XMM_REG_LO_WORD(index, reg16) \
{ (BX_XMM_REG(index)).xmm16u(0) = (reg16); }
/* store only low 8 bit of the register, rest of the register unchanged */
#define BX_WRITE_XMM_REG_LO_BYTE(index, reg8) \
{ (BX_XMM_REG(index)).xmmubyte(0) = (reg8); }
/* store XMM register */
#define BX_WRITE_XMM_REG(index, reg) \
{ (BX_XMM_REG(index)) = (reg); }
@ -175,6 +183,8 @@ typedef union bx_avx_reg_t {
/* read AVX register */
#define BX_READ_AVX_REG(index) (BX_CPU_THIS_PTR vmm[index])
#define BX_AVX_REG BX_READ_AVX_REG
/* read AVX register */
#define BX_READ_AVX_REG_LINE(index, line) \
((BX_READ_AVX_REG(index)).avx128(line))

9
bochs/disasm/dis_groups.cc
View File

@ -227,6 +227,15 @@ void disassembler::Gy(const x86_insn *insn)
else Gd(insn);
}
// vex encoded general purpose register
void disassembler::By(const x86_insn *insn)
{
if (insn->os_64)
dis_sprintf("%s", general_64bit_regname[insn->vex_vvv]);
else
dis_sprintf("%s", general_32bit_regname[insn->vex_vvv]);
}
// immediate
void disassembler::I1(const x86_insn *insn)
{

2
bochs/disasm/dis_tables.h
View File

@ -102,6 +102,8 @@
#define Gq &disassembler::Gq
#define Gy &disassembler::Gy
#define By &disassembler::By
#define I1 &disassembler::I1
#define Ib &disassembler::Ib
#define Iw &disassembler::Iw

38
bochs/disasm/dis_tables_avx.inc
View File

@ -447,6 +447,32 @@ static BxDisasmOpcodeTable_t BxDisasmGrpVexW_0f388e[2] = {
/* 1 */ { GRPSSE66(Ia_vmaskmovq_Mdq_Hdq_Vdq) }
};
static BxDisasmOpcodeTable_t BxDisasmGroupAVX_0f38f5[4] = {
/* -- */ { 0, &Ia_bzhi_Gy_Ey_By },
/* 66 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_pext_Gy_By_Ey },
/* F2 */ { 0, &Ia_pdep_Gy_By_Ey }
};
static BxDisasmOpcodeTable_t BxDisasmGroupAVX_0f38f7[4] = {
/* -- */ { 0, &Ia_bextr_Gy_Ey_By },
/* 66 */ { 0, &Ia_shlx_Gy_Ey_By },
/* F3 */ { 0, &Ia_sarx_Gy_Ey_By },
/* F2 */ { 0, &Ia_shrx_Gy_Ey_By }
};
/* Group17 */
static BxDisasmOpcodeTable_t BxDisasmGroupAVXG17[8] = {
/* 0 */ { 0, &Ia_Invalid },
/* 1 */ { 0, &Ia_blsr_By_Ey },
/* 2 */ { 0, &Ia_blsmsk_By_Ey },
/* 3 */ { 0, &Ia_blsi_By_Ey },
/* 4 */ { 0, &Ia_Invalid },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { 0, &Ia_Invalid },
/* 7 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
// 256 entries for VEX-encoded 0x0F opcodes
/* 00 */ { 0, &Ia_Invalid },
@ -949,12 +975,12 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* EF */ { 0, &Ia_Invalid },
/* F0 */ { 0, &Ia_Invalid },
/* F1 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_andn_Gy_By_Ey },
/* F3 */ { GRPN(AVXG17) },
/* F4 */ { 0, &Ia_Invalid },
/* F5 */ { 0, &Ia_Invalid },
/* F6 */ { 0, &Ia_Invalid },
/* F7 */ { 0, &Ia_Invalid },
/* F5 */ { GRPAVX(0f38f5) },
/* F6 */ { GRPSSEF3(Ia_mulx_By_Gy_Ey) },
/* F7 */ { GRPAVX(0f38f7) },
/* F8 */ { 0, &Ia_Invalid },
/* F9 */ { 0, &Ia_Invalid },
/* FA */ { 0, &Ia_Invalid },
@ -1205,7 +1231,7 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* ED */ { 0, &Ia_Invalid },
/* EE */ { 0, &Ia_Invalid },
/* EF */ { 0, &Ia_Invalid },
/* F0 */ { 0, &Ia_Invalid },
/* F0 */ { 0, &Ia_rorx_Gy_Ey_Ib },
/* F1 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid },

8
bochs/disasm/disasm.h
View File

@ -68,7 +68,8 @@
#define IA_AVX2 (1 << 26) /* AVX2 instruction */
#define IA_AVX_F16C (1 << 27) /* AVX F16 convert instruction */
#define IA_AVX_FMA (1 << 28) /* AVX FMA instruction */
#define IA_BMI (1 << 29) /* BMI instruction */
#define IA_BMI1 (1 << 29) /* BMI1 instruction */
#define IA_BMI2 (1 << 30) /* BMI2 instruction */
/* general purpose bit register */
enum {
@ -469,6 +470,9 @@ public:
void Gq(const x86_insn *insn);
void Gy(const x86_insn *insn);
// vex encoded general purpose register
void By(const x86_insn *insn);
// immediate
void I1(const x86_insn *insn);
void Ib(const x86_insn *insn);
@ -530,7 +534,7 @@ public:
void Wps(const x86_insn *insn);
void Wpd(const x86_insn *insn);
// vex override xmm/ymm register
// vex encoded xmm/ymm register
void Hdq(const x86_insn *insn);
void Hps(const x86_insn *insn);
void Hpd(const x86_insn *insn);

13
bochs/disasm/opcodes.inc
View File

@ -84,6 +84,7 @@ Ia_andl_Ed_Gd = { "and", "andl", Ed, Gd, XX, XX, 0 },
Ia_andl_Ed_Id = { "and", "andl", Ed, Id, XX, XX, 0 },
Ia_andl_Ed_sIb = { "and", "andl", Ed, sIbd, XX, XX, 0 },
Ia_andl_Gd_Ed = { "and", "andl", Gd, Ed, XX, XX, 0 },
Ia_andn_Gy_By_Ey = { "andn", "andn", Gy, By, Ey, XX, IA_BMI1 },
Ia_andnpd_Vpd_Wpd = { "andnpd", "andnpd", Vpd, Wpd, XX, XX, IA_SSE2 },
Ia_andnps_Vps_Wps = { "andnps", "andnps", Vps, Wps, XX, XX, IA_SSE },
Ia_andpd_Vpd_Wpd = { "andpd", "andpd", Vpd, Wpd, XX, XX, IA_SSE2 },
@ -99,10 +100,14 @@ Ia_andw_Ew_Iw = { "and", "andw", Ew, Iw, XX, XX, 0 },
Ia_andw_Ew_sIb = { "and", "andw", Ew, sIbw, XX, XX, 0 },
Ia_andw_Gw_Ew = { "and", "andw", Gw, Ew, XX, XX, 0 },
Ia_arpl_Ew_Gw = { "arpl", "arpl", Ew, Gw, XX, XX, 0 },
Ia_bextr_Gy_Ey_By = { "bextr", "bextr", Gy, Ey, By, XX, IA_BMI1 },
Ia_blendpd_Vpd_Wpd_Ib = { "blendpd", "blendpd", Vpd, Wpd, Ib, XX, IA_SSE4_1 },
Ia_blendps_Vps_Wps_Ib = { "blendps", "blendps", Vps, Wps, Ib, XX, IA_SSE4_1 },
Ia_blendvpd_Vpd_Wpd = { "blendvpd", "blendvpd", Vpd, Wpd, XX, XX, IA_SSE4_1 },
Ia_blendvps_Vps_Wps = { "blendvps", "blendvps", Vps, Wps, XX, XX, IA_SSE4_1 },
Ia_blsi_By_Ey = { "blsi", "blsi", By, Gy, XX, XX, IA_BMI1 },
Ia_blsmsk_By_Ey = { "blsmsk", "blsmsk", By, Gy, XX, XX, IA_BMI1 },
Ia_blsr_By_Ey = { "blsr", "blsr", By, Gy, XX, XX, IA_BMI1 },
Ia_boundl_Gd_Ma = { "bound", "boundl", Gd, Ma, XX, XX, 0 },
Ia_boundw_Gw_Ma = { "bound", "boundw", Gw, Ma, XX, XX, 0 },
Ia_bsfl_Gd_Ed = { "bsf", "bsfl", Gd, Ed, XX, XX, 0 },
@ -137,6 +142,7 @@ Ia_btsw_Ew_Gw = { "bts", "btsw", Ew, Gw, XX, XX, 0 },
Ia_btsw_Ew_Ib = { "bts", "btsw", Ew, Ib, XX, XX, 0 },
Ia_btw_Ew_Gw = { "bt", "btw", Ew, Gw, XX, XX, 0 },
Ia_btw_Ew_Ib = { "bt", "btw", Ew, Ib, XX, XX, 0 },
Ia_bzhi_Gy_Ey_By = { "bzhi", "bzhi", Gy, Ey, By, XX, IA_BMI2 },
Ia_call_Ed = { "call", "call", Ed, XX, XX, XX, 0 },
Ia_call_Eq = { "call", "call", Eq, XX, XX, XX, 0 },
Ia_call_Ew = { "call", "call", Ew, XX, XX, XX, 0 },
@ -715,6 +721,7 @@ Ia_mulsd_Vsd_Wsd = { "mulsd", "mulsd", Vsd, Wsd, XX, XX, IA_SSE2 },
Ia_mulss_Vss_Wss = { "mulss", "mulss", Vss, Wss, XX, XX, IA_SSE },
Ia_multibyte_nop = { "multibyte nop", "multibyte nop", XX, XX, XX, XX, 0 },
Ia_mulw_AX_Ew = { "mul", "mulw", AX_Reg, Ew, XX, XX, 0 },
Ia_mulx_By_Gy_Ey = { "mulx", "mulx", By, Gy, Ey, XX, IA_BMI2 },
Ia_mwait = { "mwait", "mwait", XX, XX, XX, XX, IA_MONITOR_MWAIT },
Ia_negb_Eb = { "neg", "negb", Eb, XX, XX, XX, 0 },
Ia_negl_Ed = { "neg", "negl", Ed, XX, XX, XX, 0 },
@ -816,6 +823,8 @@ Ia_pcmpgtw_Pq_Qq = { "pcmpgtw", "pcmpgtw", Pq, Qq, XX, XX, IA_MMX },
Ia_pcmpgtw_Vdq_Wdq = { "pcmpgtw", "pcmpgtw", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_pcmpistri_Vdq_Wdq_Ib = { "pcmpistri", "pcmpistri", Vdq, Wdq, Ib, XX, IA_SSE4_2 },
Ia_pcmpistrm_Vdq_Wdq_Ib = { "pcmpistrm", "pcmpistrm", Vdq, Wdq, Ib, XX, IA_SSE4_2 },
Ia_pdep_Gy_By_Ey = { "pdep", "pdep", Gy, By, Ey, XX, IA_BMI2 },
Ia_pext_Gy_By_Ey = { "pext", "pext", Gy, By, Ey, XX, IA_BMI2 },
Ia_pextrb_Ebd_Vdq_Ib = { "pextrb", "pextrb", Ebd, Vdq, Ib, XX, IA_SSE4_1 },
Ia_pextrd_Ed_Vdq_Ib = { "pextrd", "pextrd", Ed, Vdq, Ib, XX, IA_SSE4_1 },
Ia_pextrq_Eq_Vdq_Ib = { "pextrq", "pextrq", Eq, Vdq, Ib, XX, IA_SSE4_1 },
@ -1125,6 +1134,7 @@ Ia_rorq_Eq_Ib = { "ror", "rorq", Eq, Ib, XX, XX, 0 },
Ia_rorw_Ew_CL = { "ror", "rorw", Ew, CL_Reg, XX, XX, 0 },
Ia_rorw_Ew_I1 = { "ror", "rorw", Ew, I1, XX, XX, 0 },
Ia_rorw_Ew_Ib = { "ror", "rorw", Ew, Ib, XX, XX, 0 },
Ia_rorx_Gy_Ey_Ib = { "rorx", "rorx", Gy, Ey, Ib, XX, IA_BMI2 },
Ia_roundpd_Vpd_Wpd_Ib = { "roundpd", "roundpd", Vpd, Wpd, Ib, XX, IA_SSE4_1 },
Ia_roundps_Vps_Wps_Ib = { "roundps", "roundps", Vps, Wps, Ib, XX, IA_SSE4_1 },
Ia_roundsd_Vsd_Wsd_Ib = { "roundsd", "roundsd", Vsd, Wsd, Ib, XX, IA_SSE4_1 },
@ -1146,6 +1156,7 @@ Ia_sarq_Eq_Ib = { "sar", "sarq", Eq, Ib, XX, XX, 0 },
Ia_sarw_Ew_CL = { "sar", "sarw", Ew, CL_Reg, XX, XX, 0 },
Ia_sarw_Ew_I1 = { "sar", "sarw", Ew, I1, XX, XX, 0 },
Ia_sarw_Ew_Ib = { "sar", "sarw", Ew, Ib, XX, XX, 0 },
Ia_sarx_Gy_Ey_By = { "sarx", "sarx", Gy, Ey, By, XX, IA_BMI2 },
Ia_sbbb_AL_Ib = { "sbb", "sbbb", AL_Reg, Ib, XX, XX, 0 },
Ia_sbbb_Eb_Gb = { "sbb", "sbbb", Eb, Gb, XX, XX, 0 },
Ia_sbbb_Eb_Ib = { "sbb", "sbbb", Eb, Ib, XX, XX, 0 },
@ -1205,6 +1216,7 @@ Ia_shlq_Eq_Ib = { "shl", "shlq", Eq, Ib, XX, XX, 0 },
Ia_shlw_Ew_CL = { "shl", "shlw", Ew, CL_Reg, XX, XX, 0 },
Ia_shlw_Ew_I1 = { "shl", "shlw", Ew, I1, XX, XX, 0 },
Ia_shlw_Ew_Ib = { "shl", "shlw", Ew, Ib, XX, XX, 0 },
Ia_shlx_Gy_Ey_By = { "shlx", "shlx", Gy, Ey, By, XX, IA_BMI2 },
Ia_shrb_Eb_CL = { "shr", "shrb", Eb, CL_Reg, XX, XX, 0 },
Ia_shrb_Eb_I1 = { "shr", "shrb", Eb, I1, XX, XX, 0 },
Ia_shrb_Eb_Ib = { "shr", "shrb", Eb, Ib, XX, XX, 0 },
@ -1223,6 +1235,7 @@ Ia_shrq_Eq_Ib = { "shr", "shrq", Eq, Ib, XX, XX, 0 },
Ia_shrw_Ew_CL = { "shr", "shrw", Ew, CL_Reg, XX, XX, 0 },
Ia_shrw_Ew_I1 = { "shr", "shrw", Ew, I1, XX, XX, 0 },
Ia_shrw_Ew_Ib = { "shr", "shrw", Ew, Ib, XX, XX, 0 },
Ia_shrx_Gy_Ey_By = { "shrx", "shrx", Gy, Ey, By, XX, IA_BMI2 },
Ia_shufpd_Vpd_Wpd_Ib = { "shufpd", "shufpd", Vpd, Wpd, Ib, XX, IA_SSE2 },
Ia_shufps_Vps_Wps_Ib = { "shufps", "shufps", Vps, Wps, Ib, XX, IA_SSE },
Ia_sidt = { "sidt", "sidt", Ms, XX, XX, XX, 0 },

7
bochs/doc/docbook/user/user.dbk
View File

@ -3058,7 +3058,7 @@ This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
</para>
<para><command>avx</command></para>
<para>
Select AVX instruction set support.
Select AVX/AVX2 instruction set support.
This option exists only if Bochs compiled with --enable-avx option.
</para>
<para><command>avx_f16c</command></para>
@ -3066,6 +3066,11 @@ This option exists only if Bochs compiled with --enable-avx option.
Select AVX float16 convert instructions support.
This option exists only if Bochs compiled with --enable-avx option.
</para>
<para><command>bmi</command></para>
<para>
Select BMI1/BMI2 instructions support.
This option exists only if Bochs compiled with --enable-avx option.
</para>
<para><command>1g_pages</command></para>
<para>
Enable 1G page size support in long mode.

7
bochs/doc/man/bochsrc.5
View File

@ -235,7 +235,7 @@ This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
avx:
Select AVX instruction set support.
Select AVX/AVX2 instruction set support.
This option exists only if Bochs compiled with --enable-avx option.
avx_f16c:
@ -243,6 +243,11 @@ avx_f16c:
Select AVX float16 convert instructions support.
This option exists only if Bochs compiled with --enable-avx option.
bmi:
Select BMI1/BMI2 instructions support.
This option exists only if Bochs compiled with --enable-avx option.
1g_pages:
Enable 1G page size support in long mode.

7
bochs/main.cc
View File

@ -1053,7 +1053,7 @@ void bx_init_hardware()
bx_bool xsave_enabled = SIM->get_param_bool(BXPN_CPUID_XSAVE)->get();
bx_bool xsaveopt_enabled = SIM->get_param_bool(BXPN_CPUID_XSAVEOPT)->get();
#if BX_SUPPORT_AVX
bx_bool avx_enabled = SIM->get_param_bool(BXPN_CPUID_AVX)->get();
unsigned avx_enabled = SIM->get_param_num(BXPN_CPUID_AVX)->get();
#endif
#if BX_SUPPORT_X86_64
bx_bool xlarge_pages_enabled = SIM->get_param_bool(BXPN_CPUID_1G_PAGES)->get();
@ -1088,7 +1088,10 @@ void bx_init_hardware()
BX_INFO((" MWAIT support: %s", mwait_enabled?"yes":"no"));
#endif
#if BX_SUPPORT_AVX
BX_INFO((" AVX support: %s", avx_enabled?"yes":"no"));
if (avx_enabled)
BX_INFO((" AVX support: %d", avx_enabled));
else
BX_INFO((" AVX support: no"));
#endif
#if BX_SUPPORT_VMX
BX_INFO((" VMX support: %d", BX_SUPPORT_VMX));

1
bochs/param_names.h
View File

@ -56,6 +56,7 @@
#define BXPN_CPUID_XSAVEOPT "cpuid.xsaveopt"
#define BXPN_CPUID_AVX "cpuid.avx"
#define BXPN_CPUID_AVX_F16CVT "cpuid.avx_f16c"
#define BXPN_CPUID_BMI "cpuid.bmi"
#define BXPN_CPUID_APIC "cpuid.apic"
#define BXPN_CPUID_MWAIT "cpuid.mwait"
#define BXPN_CPUID_MWAIT_IS_NOP "cpuid.mwait_is_nop"