- Fixed compilation issue with cpu-level=5
- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors - CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported - Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
This commit is contained in:
Stanislav Shwartsman
parent
fb9da23f9b
commit
dfd769a102
@ -166,7 +166,6 @@
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// access to 64 bit MSR registers
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#define MSR_FSBASE (BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base)
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#define MSR_GSBASE (BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base)
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#define MSR_STAR (BX_CPU_THIS_PTR msr.star)
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#define MSR_LSTAR (BX_CPU_THIS_PTR msr.lstar)
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#define MSR_CSTAR (BX_CPU_THIS_PTR msr.cstar)
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#define MSR_FMASK (BX_CPU_THIS_PTR msr.fmask)
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@ -379,8 +378,6 @@ enum {
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#endif
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#define BX_MSR_EFER 0xc0000080
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#if BX_SUPPORT_X86_64
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#define BX_MSR_STAR 0xc0000081
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#define BX_MSR_LSTAR 0xc0000082
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#define BX_MSR_CSTAR 0xc0000083
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@ -389,7 +386,6 @@ enum {
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#define BX_MSR_GSBASE 0xc0000101
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#define BX_MSR_KERNELGSBASE 0xc0000102
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#define BX_MSR_TSC_AUX 0xc0000103
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#endif
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#define BX_MODE_IA32_REAL 0x0 // CR0.PE=0 |
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#define BX_MODE_IA32_V8086 0x1 // CR0.PE=1, EFLAGS.VM=1 | EFER.LMA=0
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@ -595,8 +591,13 @@ typedef struct
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bx_phy_address apicbase;
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#endif
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#if BX_SUPPORT_X86_64
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#define MSR_STAR (BX_CPU_THIS_PTR msr.star)
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// SYSCALL/SYSRET instruction msr's
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#if BX_CPU_LEVEL >= 5
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Bit64u star;
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#endif
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#if BX_SUPPORT_X86_64
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Bit64u lstar;
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Bit64u cstar;
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Bit32u fmask;
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@ -907,7 +908,9 @@ public: // for now...
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#if BX_CPU_LEVEL >= 5
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bx_efer_t efer;
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Bit32u efer_suppmask;
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#endif
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#if BX_CPU_LEVEL >= 6
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xcr0_t xcr0;
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Bit32u xcr0_suppmask;
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#endif
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@ -36,6 +36,7 @@ RANLIB = @RANLIB@
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BX_INCDIRS = -I.. -I../.. -I$(srcdir)/../.. -I../../@INSTRUMENT_DIR@ -I$(srcdir)/../../@INSTRUMENT_DIR@
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CPUDB_OBJS = pentium_mmx.o \
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amd_k6_2_chomper.o \
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p2_klamath.o \
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p3_katmai.o \
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p4_willamette.o \
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@ -172,3 +173,12 @@ pentium_mmx.o: pentium_mmx.@CPP_SUFFIX@ ../../bochs.h ../../config.h ../../osdep
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../apic.h ../i387.h ../../fpu/softfloat.h ../../fpu/tag_w.h \
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../../fpu/status_w.h ../../fpu/control_w.h ../xmm.h ../vmx.h \
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pentium_mmx.h
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amd_k6_2_chomper.o: amd_k6_2_chomper.@CPP_SUFFIX@ ../../bochs.h ../../config.h ../../osdep.h \
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../../bx_debug/debug.h ../../config.h ../../osdep.h \
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../../gui/siminterface.h ../../cpudb.h ../../gui/paramtree.h \
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../../memory/memory.h ../../pc_system.h ../../gui/gui.h \
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../../instrument/stubs/instrument.h ../cpu.h ../cpuid.h ../crregs.h \
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../descriptor.h ../instr.h ../ia_opcodes.h ../lazy_flags.h ../icache.h \
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../apic.h ../i387.h ../../fpu/softfloat.h ../../fpu/tag_w.h \
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../../fpu/status_w.h ../../fpu/control_w.h ../xmm.h ../vmx.h \
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amd_k6_2_chomper.h
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350
bochs/cpu/cpudb/amd_k6_2_chomper.cc
Normal file
350
bochs/cpu/cpudb/amd_k6_2_chomper.cc
Normal file
@ -0,0 +1,350 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2011 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#include "bochs.h"
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#include "cpu.h"
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#include "amd_k6_2_chomper.h"
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#define LOG_THIS cpu->
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#if BX_CPU_LEVEL == 5
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amd_k6_2_chomper_t::amd_k6_2_chomper_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
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{
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if (BX_SUPPORT_X86_64)
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BX_PANIC(("x86-64 should be disabled for AMD K6-2 configuration"));
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if (BX_CPU_LEVEL != 5)
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BX_PANIC(("AMD K6-2 configuration should be compiled with BX_CPU_LEVEL=5"));
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BX_INFO(("WARNING: 3DNow! is not implemented yet !"));
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}
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void amd_k6_2_chomper_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const
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{
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switch(function) {
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case 0x8FFFFFFF:
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get_cpuid_hidden_level(leaf);
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return;
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case 0x80000000:
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get_ext_cpuid_leaf_0(leaf);
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return;
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case 0x80000001:
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get_ext_cpuid_leaf_1(leaf);
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return;
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case 0x80000002:
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case 0x80000003:
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case 0x80000004:
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get_ext_cpuid_brand_string_leaf(function, leaf);
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return;
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case 0x80000005:
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get_ext_cpuid_leaf_5(leaf);
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return;
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case 0x00000000:
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get_std_cpuid_leaf_0(leaf);
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return;
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case 0x00000001:
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get_std_cpuid_leaf_1(leaf);
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return;
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default:
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get_reserved_leaf(leaf);
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return;
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}
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}
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Bit32u amd_k6_2_chomper_t::get_isa_extensions_bitmask(void) const
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{
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return BX_CPU_X87 |
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BX_CPU_486 |
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BX_CPU_PENTIUM |
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BX_CPU_MMX |
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BX_CPU_SYSCALL_SYSRET |
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BX_CPU_3DNOW;
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}
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Bit32u amd_k6_2_chomper_t::get_cpu_extensions_bitmask(void) const
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{
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return BX_CPU_DEBUG_EXTENSIONS |
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BX_CPU_VME |
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#if BX_PHY_ADDRESS_LONG
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BX_CPU_PSE36 |
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#endif
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BX_CPU_PSE;
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}
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// leaf 0x00000000 //
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void amd_k6_2_chomper_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf) const
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{
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static const char* vendor_string = "AuthenticAMD";
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// EAX: highest std function understood by CPUID
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// EBX: vendor ID string
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// EDX: vendor ID string
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// ECX: vendor ID string
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leaf->eax = 0x1;
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// CPUID vendor string (e.g. GenuineIntel, AuthenticAMD, CentaurHauls, ...)
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memcpy(&(leaf->ebx), vendor_string, 4);
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memcpy(&(leaf->edx), vendor_string + 4, 4);
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memcpy(&(leaf->ecx), vendor_string + 8, 4);
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#ifdef BX_BIG_ENDIAN
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leaf->ebx = bx_bswap32(leaf->ebx);
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leaf->ecx = bx_bswap32(leaf->ecx);
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leaf->edx = bx_bswap32(leaf->edx);
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#endif
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}
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// leaf 0x00000001 //
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void amd_k6_2_chomper_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) const
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{
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// EAX: CPU Version Information
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// [3:0] Stepping ID
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// [7:4] Model: starts at 1
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// [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
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// [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
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// [19:16] Extended Model
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// [27:20] Extended Family
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leaf->eax = 0x00000580;
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leaf->ebx = 0;
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leaf->ecx = 0;
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// EDX: Standard Feature Flags
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// * [0:0] FPU on chip
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// * [1:1] VME: Virtual-8086 Mode enhancements
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// * [2:2] DE: Debug Extensions (I/O breakpoints)
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// * [3:3] PSE: Page Size Extensions
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// * [4:4] TSC: Time Stamp Counter
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// * [5:5] MSR: RDMSR and WRMSR support
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// [6:6] PAE: Physical Address Extensions
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// * [7:7] MCE: Machine Check Exception
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// * [8:8] CXS: CMPXCHG8B instruction
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// [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// [11:11] SYSENTER/SYSEXIT support
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// [12:12] MTRR: Memory Type Range Reg
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// [13:13] PGE/PTE Global Bit
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// [14:14] MCA: Machine Check Architecture
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// [15:15] CMOV: Cond Mov/Cmp Instructions
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// [16:16] PAT: Page Attribute Table
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// [17:17] PSE-36: Physical Address Extensions
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// [18:18] PSN: Processor Serial Number
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// [19:19] CLFLUSH: CLFLUSH Instruction support
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// [20:20] Reserved
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// [21:21] DS: Debug Store
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// [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
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// * [23:23] MMX Technology
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// [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// [25:25] SSE: SSE Extensions
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// [26:26] SSE2: SSE2 Extensions
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// [27:27] Self Snoop
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// [28:28] Hyper Threading Technology
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// [29:29] TM: Thermal Monitor
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// [30:30] Reserved
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// [31:31] PBE: Pending Break Enable
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leaf->edx = BX_CPUID_STD_X87 |
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BX_CPUID_STD_VME |
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BX_CPUID_STD_DEBUG_EXTENSIONS |
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BX_CPUID_STD_PSE |
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BX_CPUID_STD_TSC |
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BX_CPUID_STD_MSR |
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BX_CPUID_STD_MCE |
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BX_CPUID_STD_CMPXCHG8B |
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#if BX_PHY_ADDRESS_LONG
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BX_CPUID_STD_PSE36 |
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#endif
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BX_CPUID_STD_MMX;
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#if BX_SUPPORT_APIC
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// if MSR_APICBASE APIC Global Enable bit has been cleared,
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// the CPUID feature flag for the APIC is set to 0.
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if (cpu->msr.apicbase & 0x800)
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leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
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#endif
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}
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// leaf 0x80000000 //
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void amd_k6_2_chomper_t::get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const
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{
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// EAX: highest extended function understood by CPUID
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// EBX: reserved
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// EDX: reserved
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// ECX: reserved
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leaf->eax = 0x80000005;
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leaf->ebx = 0;
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leaf->ecx = 0;
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leaf->edx = 0;
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}
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// leaf 0x80000001 //
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void amd_k6_2_chomper_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
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{
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// EAX: CPU Version Information (same as 0x00000001.EAX)
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leaf->eax = 0x00000680;
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leaf->ebx = 0;
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leaf->ecx = 0;
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// EDX:
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// Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD
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// * [0:0] FPU on chip
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// * [1:1] VME: Virtual-8086 Mode enhancements
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// * [2:2] DE: Debug Extensions (I/O breakpoints)
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// * [3:3] PSE: Page Size Extensions
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// * [4:4] TSC: Time Stamp Counter
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// * [5:5] MSR: RDMSR and WRMSR support
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// [6:6] PAE: Physical Address Extensions
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// * [7:7] MCE: Machine Check Exception
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// * [8:8] CXS: CMPXCHG8B instruction
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// * [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// * [11:11] SYSCALL/SYSRET support
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// [12:12] MTRR: Memory Type Range Reg
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// [13:13] PGE/PTE Global Bit
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// [14:14] MCA: Machine Check Architecture
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// [15:15] CMOV: Cond Mov/Cmp Instructions
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// [16:16] PAT: Page Attribute Table
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// [17:17] PSE-36: Physical Address Extensions
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// [18:18] Reserved
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// [19:19] Reserved
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// [20:20] No-Execute page protection
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// [21:21] Reserved
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// [22:22] MMXExt: AMD Extensions to MMX Technology
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// * [23:23] MMX Technology
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// [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// [25:25] FFXSR: Fast FXSAVE/FXRSTOR
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// [26:26] 1G paging support
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// [27:27] Support RDTSCP Instruction
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// [28:28] Reserved
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// [29:29] Long Mode
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// [30:30] AMD 3DNow! Extensions
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// * [31:31] AMD 3DNow! Instructions
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leaf->edx = BX_CPUID_STD_X87 |
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BX_CPUID_STD_VME |
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BX_CPUID_STD_DEBUG_EXTENSIONS |
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BX_CPUID_STD_PSE |
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BX_CPUID_STD_TSC |
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BX_CPUID_STD_MSR |
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BX_CPUID_STD_MCE |
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BX_CPUID_STD_CMPXCHG8B |
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BX_CPUID_STD2_SYSCALL_SYSRET |
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#if BX_PHY_ADDRESS_LONG
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BX_CPUID_STD_PSE36 |
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#endif
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BX_CPUID_STD_MMX |
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BX_CPUID_STD2_3DNOW;
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#if BX_SUPPORT_APIC
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// if MSR_APICBASE APIC Global Enable bit has been cleared,
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// the CPUID feature flag for the APIC is set to 0.
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if (cpu->msr.apicbase & 0x800)
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leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
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#endif
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}
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// leaf 0x80000002 //
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// leaf 0x80000003 //
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// leaf 0x80000004 //
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void amd_k6_2_chomper_t::get_ext_cpuid_brand_string_leaf(Bit32u function, cpuid_function_t *leaf) const
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{
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// CPUID function 0x80000002-0x80000004 - Processor Name String Identifier
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static const char* brand_string = "AMD-K6(tm) 3D processor\0\0\0\0\0\0\0\0\0\0\0\0\0";
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switch(function) {
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case 0x80000002:
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memcpy(&(leaf->eax), brand_string , 4);
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memcpy(&(leaf->ebx), brand_string + 4, 4);
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memcpy(&(leaf->ecx), brand_string + 8, 4);
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memcpy(&(leaf->edx), brand_string + 12, 4);
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break;
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case 0x80000003:
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memcpy(&(leaf->eax), brand_string + 16, 4);
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memcpy(&(leaf->ebx), brand_string + 20, 4);
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leaf->ecx = 0;
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leaf->edx = 0;
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break;
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case 0x80000004:
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leaf->eax = 0;
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leaf->ebx = 0;
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leaf->ecx = 0;
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leaf->edx = 0;
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break;
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default:
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break;
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}
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#ifdef BX_BIG_ENDIAN
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leaf->eax = bx_bswap32(leaf->eax);
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leaf->ebx = bx_bswap32(leaf->ebx);
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leaf->ecx = bx_bswap32(leaf->ecx);
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leaf->edx = bx_bswap32(leaf->edx);
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#endif
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}
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|
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// leaf 0x80000005 //
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void amd_k6_2_chomper_t::get_ext_cpuid_leaf_5(cpuid_function_t *leaf) const
|
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{
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// CPUID function 0x800000005 - L1 Cache and TLB Identifiers
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leaf->eax = 0x00000000;
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leaf->ebx = 0x02800140;
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leaf->ecx = 0x20020220;
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leaf->edx = 0x20020220;
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}
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// leaf 0x8FFFFFFF //
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void amd_k6_2_chomper_t::get_cpuid_hidden_level(cpuid_function_t *leaf) const
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{
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static const char* magic_string = "NexGenerationAMD";
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memcpy(&(leaf->eax), magic_string , 4);
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memcpy(&(leaf->ebx), magic_string + 4, 4);
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memcpy(&(leaf->ecx), magic_string + 8, 4);
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memcpy(&(leaf->edx), magic_string + 12, 4);
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#ifdef BX_BIG_ENDIAN
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leaf->eax = bx_bswap32(leaf->eax);
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leaf->ebx = bx_bswap32(leaf->ebx);
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leaf->ecx = bx_bswap32(leaf->ecx);
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leaf->edx = bx_bswap32(leaf->edx);
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#endif
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}
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|
||||
void amd_k6_2_chomper_t::dump_cpuid(void) const
|
||||
{
|
||||
struct cpuid_function_t leaf;
|
||||
unsigned n;
|
||||
|
||||
for (n=0; n<=1; n++) {
|
||||
get_cpuid_leaf(n, 0x00000000, &leaf);
|
||||
BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx));
|
||||
}
|
||||
|
||||
for (n=0x80000000; n<=0x80000005; n++) {
|
||||
get_cpuid_leaf(n, 0x00000000, &leaf);
|
||||
BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx));
|
||||
}
|
||||
}
|
||||
|
||||
bx_cpuid_t *create_amd_k6_2_chomper_cpuid(BX_CPU_C *cpu) { return new amd_k6_2_chomper_t(cpu); }
|
||||
|
||||
#endif
|
||||
62
bochs/cpu/cpudb/amd_k6_2_chomper.h
Normal file
62
bochs/cpu/cpudb/amd_k6_2_chomper.h
Normal file
@ -0,0 +1,62 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id$
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2011 Stanislav Shwartsman
|
||||
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
|
||||
//
|
||||
// This library is free software; you can redistribute it and/or
|
||||
// modify it under the terms of the GNU Lesser General Public
|
||||
// License as published by the Free Software Foundation; either
|
||||
// version 2 of the License, or (at your option) any later version.
|
||||
//
|
||||
// This library is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
// Lesser General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU Lesser General Public
|
||||
// License along with this library; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef BX_amd_k6_2_chomper_CPUID_DEFINITIONS_H
|
||||
#define BX_amd_k6_2_chomper_CPUID_DEFINITIONS_H
|
||||
|
||||
#if BX_CPU_LEVEL >= 5 && BX_SUPPORT_X86_64 == 0
|
||||
|
||||
#include "cpu/cpuid.h"
|
||||
|
||||
class amd_k6_2_chomper_t : public bx_cpuid_t {
|
||||
public:
|
||||
amd_k6_2_chomper_t(BX_CPU_C *cpu);
|
||||
virtual ~amd_k6_2_chomper_t() {}
|
||||
|
||||
// return CPU name
|
||||
virtual const char *get_name(void) const { return "amd_k6_2_chomper"; }
|
||||
|
||||
virtual Bit32u get_isa_extensions_bitmask(void) const;
|
||||
virtual Bit32u get_cpu_extensions_bitmask(void) const;
|
||||
|
||||
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;
|
||||
|
||||
virtual void dump_cpuid(void) const;
|
||||
|
||||
private:
|
||||
void get_std_cpuid_leaf_0(cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_1(cpuid_function_t *leaf) const;
|
||||
|
||||
void get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const;
|
||||
void get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const;
|
||||
void get_ext_cpuid_brand_string_leaf(Bit32u function, cpuid_function_t *leaf) const;
|
||||
void get_ext_cpuid_leaf_5(cpuid_function_t *leaf) const;
|
||||
|
||||
void get_cpuid_hidden_level(cpuid_function_t *leaf) const;
|
||||
};
|
||||
|
||||
extern bx_cpuid_t *create_amd_k6_2_chomper_cpuid(BX_CPU_C *cpu);
|
||||
|
||||
#endif // BX_CPU_LEVEL >= 5 && BX_SUPPORT_X86_64 == 0
|
||||
|
||||
#endif
|
||||
64
bochs/cpu/cpudb/amd_k6_2_chomper.txt
Normal file
64
bochs/cpu/cpudb/amd_k6_2_chomper.txt
Normal file
@ -0,0 +1,64 @@
|
||||
CPU-Z TXT Report
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Binaries
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
CPU-Z version 1.53.1
|
||||
|
||||
Processors
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Number of processors 1
|
||||
Number of threads 1
|
||||
|
||||
APICs
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Processor 0
|
||||
-- Core 0
|
||||
-- Thread 0 0
|
||||
|
||||
Processors Information
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Processor 1 ID = 0
|
||||
Number of cores 1 (max 1)
|
||||
Number of threads 1 (max 1)
|
||||
Name AMD K6-2
|
||||
Codename Chomper
|
||||
Specification AMD-K6(tm) 3D processor
|
||||
Package Socket 7 (321)
|
||||
CPUID 5.8.0
|
||||
Extended CPUID 6.8
|
||||
Core Stepping
|
||||
Technology 0.25 um
|
||||
Core Speed 267.3 MHz
|
||||
Instructions sets MMX, 3DNow!
|
||||
L1 Data cache 32 KBytes, 2-way set associative, 32-byte line size
|
||||
L1 Instruction cache 32 KBytes, 2-way set associative, 32-byte line size
|
||||
FID/VID Control no
|
||||
|
||||
|
||||
|
||||
Thread dumps
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
CPU Thread 0
|
||||
APIC ID 0
|
||||
Topology Processor ID 0, Core ID 0, Thread ID 0
|
||||
Type 02000802h
|
||||
Max CPUID level 00000001h
|
||||
Max CPUID ext. level 80000005h
|
||||
Cache descriptor Level 1, I, 32 KB, 1 thread(s)
|
||||
Cache descriptor Level 1, D, 32 KB, 1 thread(s)
|
||||
|
||||
CPUID
|
||||
0x00000000 0x00000001 0x68747541 0x444D4163 0x69746E65
|
||||
0x00000001 0x00000580 0x00000000 0x00000000 0x008001BF
|
||||
0x80000000 0x80000005 0x00000000 0x00000000 0x00000000
|
||||
0x80000001 0x00000680 0x00000000 0x00000000 0x808009BF
|
||||
0x80000002 0x2D444D41 0x7428364B 0x3320296D 0x72702044
|
||||
0x80000003 0x7365636F 0x00726F73 0x00000000 0x00000000
|
||||
0x80000004 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x80000005 0x00000000 0x02800140 0x20020220 0x20020220
|
||||
@ -196,8 +196,8 @@ struct bx_dr7_t {
|
||||
struct bx_efer_t {
|
||||
Bit32u val32; // 32bit value of register
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
IMPLEMENT_CRREG_ACCESSORS(SCE, 0);
|
||||
#if BX_SUPPORT_X86_64
|
||||
IMPLEMENT_CRREG_ACCESSORS(LME, 8);
|
||||
IMPLEMENT_CRREG_ACCESSORS(LMA, 10);
|
||||
#endif
|
||||
|
||||
@ -213,13 +213,13 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)
|
||||
|
||||
val64 = BX_CPU_THIS_PTR efer.get32();
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
case BX_MSR_STAR:
|
||||
val64 = MSR_STAR;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
case BX_MSR_LSTAR:
|
||||
val64 = MSR_LSTAR;
|
||||
break;
|
||||
@ -589,13 +589,13 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
|
||||
case BX_MSR_EFER:
|
||||
if (! SetEFER(val_64)) return 0;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
case BX_MSR_STAR:
|
||||
MSR_STAR = val_64;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
case BX_MSR_LSTAR:
|
||||
if (! IsCanonical(val_64)) {
|
||||
BX_ERROR(("WRMSR: attempt to write non-canonical value to MSR_LSTAR !"));
|
||||
|
||||
@ -979,7 +979,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i)
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; /* 4k granularity */
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1;
|
||||
#if BX_SUPPORT_X86_64
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 32-bit code */
|
||||
#endif
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; /* available for use by system */
|
||||
|
||||
updateFetchModeMask(/* CS reloaded */);
|
||||
@ -1001,7 +1003,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i)
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 1; /* 4k granularity */
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 1; /* 32 bit stack */
|
||||
#if BX_SUPPORT_X86_64
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.l = 0;
|
||||
#endif
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0; /* available for use by system */
|
||||
|
||||
BX_CPU_THIS_PTR clear_VM();
|
||||
@ -1116,7 +1120,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSRET(bxInstruction_c *i)
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 1; /* 4k granularity */
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 1;
|
||||
#if BX_SUPPORT_X86_64
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 32-bit code */
|
||||
#endif
|
||||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0; /* available for use by system */
|
||||
|
||||
updateFetchModeMask(/* CS reloaded */);
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
bx_define_cpudb(bx_generic)
|
||||
#if BX_CPU_LEVEL == 5
|
||||
bx_define_cpudb(pentium_mmx)
|
||||
bx_define_cpudb(amd_k6_2_chomper)
|
||||
#elif BX_CPU_LEVEL >= 6
|
||||
#if BX_SUPPORT_X86_64 == 0
|
||||
bx_define_cpudb(p2_klamath)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user