mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
11,991 Commits 11 Branches 185 Tags 48 MiB
b228d22303
Commit Graph

3498 Commits

Author SHA1 Message Date
Stanislav Shwartsman
9f18573740 Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only) 2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
b9b45f0d0d convert some defines to typed consts 2015-05-10 19:54:57 +00:00
Stanislav Shwartsman
0d79c5f986 Implemented Page Modification Logging VMX feature 2015-05-06 19:55:44 +00:00
Stanislav Shwartsman
2185d21eb7 fixed comments for PML acronym 2015-05-05 19:52:05 +00:00
Stanislav Shwartsman
a197977682 fixed typo 2015-05-05 19:37:01 +00:00
Stanislav Shwartsman
c9fba73a69 added defines about new VMX bits and controls related to Page Miss Logging (PML) EPT feature 2015-05-05 19:35:39 +00:00
Stanislav Shwartsman
16ab385e1d added cpuid/creg bits definition announced in recent 054 update of Intel SDM 2015-05-05 19:28:25 +00:00
Stanislav Shwartsman
5edd53186e optimize for target with no x86-64 support 2015-05-04 19:58:01 +00:00
Stanislav Shwartsman
28fc5083af remove the victim cache code to resolve assert in proc_ctrl.cc 2015-05-04 19:47:52 +00:00
Stanislav Shwartsman
4c34b97db1 fixed comment 2015-05-03 19:44:24 +00:00
Stanislav Shwartsman
5ef56d6d79 rename fpu function 2015-05-02 20:08:36 +00:00
Stanislav Shwartsman
4c7a05621c reorg of code managing MXCSR to softfloat status conversion 2015-05-02 19:54:48 +00:00
Stanislav Shwartsman
9be2f07d54 fix compilation err when SVM is enabled 2015-04-21 08:20:28 +00:00
Stanislav Shwartsman
e72f66ce49 added BX_CPP_AttrRegparmN to xmm/ymmz/zmm read methods matching cpu.h 2015-04-19 20:47:55 +00:00
Stanislav Shwartsman
239b1ae684 added missed vmexit reason to debug print 2015-04-18 19:25:58 +00:00
Stanislav Shwartsman
080ceb8293 don't crash when running on 386 with no FPU model 2015-03-27 21:39:24 +00:00
Stanislav Shwartsman
c360ddf60c correctly report memory type for EPT page table accesses 
TODO: support memory type for guest physical access under EPT
TODO: support memory type for SVM nested paging 
TODO: check what happens when PAT is not enabled in CPU configuration
 2015-03-23 20:27:36 +00:00
Stanislav Shwartsman
05635a9534 call correctly resolve_memtype function 2015-03-21 20:28:22 +00:00
Stanislav Shwartsman
56323b2806 bugfixes 2015-03-21 20:15:57 +00:00
Stanislav Shwartsman
a55c5e4eb8 correctly report memory type for page table accesses in x86 mode (not in EPT or SVM nested paging yet) 
TODO: support memory type with EPT / nested paging
TODO: check what happens when PAT is not enabled in CPU configuration
 2015-03-21 20:08:58 +00:00
Stanislav Shwartsman
e79185b0a0 refactor memtype methods 2015-03-02 20:51:59 +00:00
Stanislav Shwartsman
36f7bf0ba6 fixed ept memtype printout 2015-03-01 21:04:34 +00:00
Stanislav Shwartsman
8134dc67af supporting memory type provided by page tables with PCD,PWT and PAT bits 
TODO: support memory type with EPT
TODO: support memory type for intermediate page table accesses
TODO: check what happens when PAT is not enabled in CPU configuration
 2015-03-01 20:55:23 +00:00
Stanislav Shwartsman
9932384df3 fixed visual studio warning 2015-03-01 19:44:06 +00:00
Stanislav Shwartsman
53041981f7 supply PAT required memory type bits through new combined access interface 2015-02-28 14:06:04 +00:00
Stanislav Shwartsman
25b02dac4b code reorg before PAT memory type support 2015-02-28 14:01:11 +00:00
Stanislav Shwartsman
b74036d2d8 another try to fix the weird compilation error 2015-02-26 20:34:24 +00:00
Stanislav Shwartsman
4e859202a1 attemp to fix compilation issue 2015-02-25 19:43:47 +00:00
Stanislav Shwartsman
1e1c893041 introduce new 64bit packed register type and implement pat/mtrr and mmx registers through it 2015-02-23 21:17:33 +00:00
Stanislav Shwartsman
2bad0d0d12 fixed link error with debugger enabled, small speed optimization 2015-02-23 19:55:55 +00:00
Stanislav Shwartsman
2448c0cf74 fixed complation err 2015-02-23 17:55:09 +00:00
Stanislav Shwartsman
6c6b670551 fixed typo causing compilation error 2015-02-22 21:33:26 +00:00
Stanislav Shwartsman
0917d12e8b memory type report for physical accesses and RMW acccesses. todo: consider also pat 2015-02-22 21:26:26 +00:00
Stanislav Shwartsman
7a3e340e6d implement memory type calculation by mtrr. todo: memory type from page tables 2015-02-20 21:50:59 +00:00
Stanislav Shwartsman
e16c6eb30c preparations and interface definition for memory type support 2015-02-19 20:23:08 +00:00
Stanislav Shwartsman
a74e855185 added Broadwell ULT CPUID definition to CPUDB 2015-02-12 21:28:24 +00:00
Stanislav Shwartsman
901b7be1a8 code reorg 2015-02-12 20:18:35 +00:00
Stanislav Shwartsman
40312cec2d added pentium cpudb files 2015-02-11 21:44:24 +00:00
Stanislav Shwartsman
b60d7d3154 Cleanup of CPUDB modules, moved common functionality into bx_cpuid_t base class 
Added Pentium (P54C) AKA Pentium with no MMX to CPUDB
 2015-02-11 21:31:17 +00:00
Stanislav Shwartsman
adaca4a6f5 more correct limit4g fix 2015-02-08 06:37:59 +00:00
Stanislav Shwartsman
e80e911166 fixed compilation on cpu level < 6 2015-01-29 18:41:28 +00:00
Stanislav Shwartsman
d6631f767d correct alignment checking (on linear address and not on effective address) 2015-01-28 16:49:46 +00:00
Stanislav Shwartsman
51808f775d 4G optimization is active only when seg.base == 0 2015-01-27 15:47:02 +00:00
Stanislav Shwartsman
17c89d1c78 masked load-store optimization for avx-512 2015-01-26 20:52:03 +00:00
Stanislav Shwartsman
ee3841ef07 fixed more compilation problems and code cleanup 2015-01-26 20:01:25 +00:00
Stanislav Shwartsman
3a4bd2da51 fixed debug message 2015-01-26 19:16:51 +00:00
Stanislav Shwartsman
9a70727814 fixed fault priority for memory accesses requiring alignment 2015-01-26 19:09:58 +00:00
Stanislav Shwartsman
74da7a7092 fixed compilation err 2015-01-26 15:34:52 +00:00
Stanislav Shwartsman
b5a603c8c7 fixed %d->%u format found by cppcheck (patch by Maxim Derbasov) 2015-01-25 21:24:13 +00:00
Stanislav Shwartsman
ea390d58dc added new files, removed old files, remove obsolete assert 2015-01-25 20:58:04 +00:00
Stanislav Shwartsman
5e6955c5e7 Major rewrite of memory access methods to avoid massive code duplication and enable inlining of memory access methods 2015-01-25 20:55:10 +00:00
Stanislav Shwartsman
271f06026d fixed compilation err with SVM without VMX 2015-01-16 06:15:47 +00:00
Stanislav Shwartsman
63c3ed3f70 update (c) and fix instrumentation stub 2015-01-11 20:50:26 +00:00
Stanislav Shwartsman
3b237df41d Added far branch origin to bx_instr_far_branch instrumentation callback by user request 
Updated instrumentation examples
Fixed code duplication
 2015-01-11 20:45:39 +00:00
Stanislav Shwartsman
6fd2d32180 fixed exception error code for debugger and instrumentation 2014-12-18 19:45:03 +00:00
Volker Ruppert
2ec57b8a6b Fixed some more C++11 warnings. 2014-12-18 17:52:40 +00:00
Stanislav Shwartsman
fea4d47830 fixed spelling in comments 2014-12-16 20:11:08 +00:00
Stanislav Shwartsman
6700a3f5e6 fix cpuid patch merged 2014-12-16 06:52:24 +00:00
Stanislav Shwartsman
03dab0b0c9 remove debug prints from param tree dump in xml format, small code reorg 2014-11-30 21:26:33 +00:00
Stanislav Shwartsman
f01891faa2 fixed compilation err with perfmon disabled 2014-11-07 13:15:54 +00:00
Stanislav Shwartsman
9219c2c20b fixed format for debug printing x87 numbers 2014-11-05 18:29:35 +00:00
Stanislav Shwartsman
6e254743c1 Added missing sanity check. 
The sanity check would help to detect real Bochs crash issue under Win x64 with MSDEV
configure script under Mingw env decided that SIZEOF_INT_P == 4 which is terribly wrong for 64-bit host.
 2014-11-04 19:00:20 +00:00
Stanislav Shwartsman
9feed6d777 fixed bug in write_new_stack_qword 2014-11-03 14:34:20 +00:00
Volker Ruppert
b7c8323633 Fixed panic in case x86-64 support is not present (Bochs 2.6.7 P4-SMP release 
binaries are already fixed).
Usual updates after release (version strings, release tag).
 2014-11-02 14:14:36 +00:00
Stanislav Shwartsman
987e2ad223 Added definitions from recently published Intel Architecture 
Instruction Set Extensions Programming Reference rev22.
Implemented CLWB instruction
 2014-11-01 13:12:24 +00:00
Stanislav Shwartsman
45ddcf2e02 compilation fix 2014-11-01 11:51:03 +00:00
Stanislav Shwartsman
5f4e7f8b49 fixed compilation when APIC if snot enabled 2014-11-01 10:25:42 +00:00
Stanislav Shwartsman
618bc234ab changes in comments 2014-10-24 11:18:52 +00:00
Stanislav Shwartsman
f11b9a7f58 CPUID: "Yonah" and "Atom N-270" should report max virtual address as 32-bit in leaf 0x80000008 2014-10-22 19:53:23 +00:00
Stanislav Shwartsman
cb18f1e0a1 more use of the clearflagsOSZAPC 2014-10-22 18:24:33 +00:00
Stanislav Shwartsman
1c027b17d7 some lazy flags handling optimizations 2014-10-22 17:49:12 +00:00
Stanislav Shwartsman
25ad64f75a rename one more mem access handler 2014-10-21 19:11:21 +00:00
Stanislav Shwartsman
1de7a35031 update (c) 2014-10-20 21:10:52 +00:00
Stanislav Shwartsman
ea91354b3b code reorg : take laddr calculation out of 64-bit memory handlers. this creates generic linear address memory handlers which now could be used elsewhere 2014-10-20 21:08:29 +00:00
Stanislav Shwartsman
2c4b17ebff fixed compilation err without x86-64 compiled in 2014-10-16 06:29:58 +00:00
Stanislav Shwartsman
54a009ccf9 update CHANGES. added BX_INFO prints related to Perfmon usage 2014-10-15 19:04:28 +00:00
Stanislav Shwartsman
6252632e31 Fixed segmentation fault that could happen under rare conditions with handlers chaining speedups enabled. 
I saw that issue under gcc 4.9.0. for some reason gcc 4.9.0 didn't optimize next handler call in all fpu opcode handlers.
As result, instead of finishing the handler and jumping to next one, the next handler is called blowing up stack.
After some long period stack overflow might occur.

The fix simply limit the max chaining depth to 1000 traces (should be enough)
The same fix should be able to address the stack overflow problem when compiling with -O0 and handlers chaining speedup enabled.
 2014-10-15 18:00:04 +00:00
Stanislav Shwartsman
d82e51f947 added comment to RDPMC instr 2014-10-15 15:28:13 +00:00
Stanislav Shwartsman
841117c721 added more perfmon MSR defines into cpu.h 2014-10-15 15:21:38 +00:00
Stanislav Shwartsman
caab07e580 move common code (extended topology leaf) into base cpuid class to save code duplication 2014-10-15 14:25:08 +00:00
Stanislav Shwartsman
f8267ec3a7 rework in CPUID code (fixed code duplication). Re-enable perfmon reporting in CPUID because Win8/Win10 installation doesn't want to start without perfmon reported. TODO: implement basic perfmon support (at least only fixed counters) because win7-64 doesn't install with perfmon reported but not implemented 2014-10-15 08:04:38 +00:00
Stanislav Shwartsman
8d1e3b2ac1 Added statistics collection infrastructure in Bochs and 
implemented important CPU statistics which were used for Bochs CPU model performance analysis.
old statistics code from paging.cc and cpu.cc is replaced with new infrastructure.

In order to enale statitics collection in Bochs CPU:

- Enable statistics @ compilation time in cpu/cpustats.h
- Dump statistics periodically by adding -dumpstats N into Bochs command line
 2014-10-14 15:59:10 +00:00
Stanislav Shwartsman
1ef6c3139c removed duplication in XCHG instruction handlers 2014-10-12 19:31:14 +00:00
Stanislav Shwartsman
24cb334304 fixed large code duplication in write_new_stack methods 2014-10-12 18:59:10 +00:00
Stanislav Shwartsman
3db00a7e52 fixed CMPXHG16B implementation 2014-10-02 18:53:41 +00:00
Stanislav Shwartsman
4ab9f62a20 bugfix: register supported cpu extensions for trinity cpu model 2014-09-26 19:24:11 +00:00
Stanislav Shwartsman
6ebbb886c4 implemented VPMULTISHIFTQB VBMI instruction 2014-09-26 13:19:45 +00:00
Stanislav Shwartsman
e2e6f5a62b Update CPUID defines after recently published 
Intel Architecture Instruction Set Extensions Programming Reference rev-021

Enable AVX-512 with all implemented extensions in generic CPUID when simd=AVX512 is supplied
implemented AVX512_IFMA532 instructions
implemented AVX512_VBMI instructions

still missing: VPMULTISHIFTQB - VBMI instruction (coming soon)
 2014-09-26 12:14:53 +00:00
Stanislav Shwartsman
86bb2f97cc fixed shoft128right macro is softfloat 2014-09-19 16:01:46 +00:00
Stanislav Shwartsman
694069bd36 fixed cmpxchg16b bug (SF titcket #523 in patches tracker) 2014-09-14 18:13:08 +00:00
Stanislav Shwartsman
29efae3be3 adjust (c) in several files 2014-08-31 20:05:25 +00:00
Stanislav Shwartsman
5413b5c31b don't forget to initialize (clear) cpu features bitmask in the beginning ... 2014-08-31 19:48:58 +00:00
Stanislav Shwartsman
5eb781e45f cleanup after cpu features interface rework 2014-08-31 19:22:41 +00:00
Stanislav Shwartsman
b6147d9de8 fixed debugger enabled code 2014-08-31 18:48:04 +00:00
Stanislav Shwartsman
9f57e70d5f Rewritten handling of supported CPUID features to be able to handle large amount of CPU extensions 
Now enable support for up to 128 CPU extensions and could easily extend it more
Also reduce memory footprint for bx_ia_opcodes.h arrays
 2014-08-31 18:39:18 +00:00
Stanislav Shwartsman
8e632c1bbe fixed bug in vrsqt14* implementation 2014-08-16 18:15:02 +00:00
Stanislav Shwartsman
e1bcc8cb1e bugfix with denormal arguments in avx-512 14-bit reciprocal 2014-08-15 19:00:12 +00:00
Stanislav Shwartsman
7e1a31af5e fixed denormal arg handling in VGENTMANT* 2014-08-15 10:27:56 +00:00
Stanislav Shwartsman
c064a09348 regen dependencies in makefile for cpu objects 2014-08-14 19:53:57 +00:00
Stanislav Shwartsman
7ae5a1c6b3 fixed NaN handling for VRANGE* instructions 2014-08-14 19:42:34 +00:00
Stanislav Shwartsman
128137b421 avx512 bugfixes 2014-08-13 18:34:42 +00:00
Stanislav Shwartsman
fb526a0670 implemented (not yet 100% correct) VREDUCE* AVX512 opcode 2014-08-08 19:12:18 +00:00
Stanislav Shwartsman
4b03966176 Implemented VDBPSADBW AVX512BW instruction 
The only missing AVX512BW/AVX512DQ opcodes are now:

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-08-05 20:18:42 +00:00
Stanislav Shwartsman
4455d9100b simplify code a little more 2014-08-05 19:20:15 +00:00
Stanislav Shwartsman
5b0d0519d5 fixed typo in prev checkin 2014-08-05 19:03:17 +00:00
Stanislav Shwartsman
2231ffb242 simplify legacy (sse and avx) sad calculation in simd_int.h 2014-08-05 19:01:01 +00:00
Stanislav Shwartsman
5e80c1f419 fixed vrange* abs comparisons in softfloat 2014-08-04 21:24:38 +00:00
Stanislav Shwartsman
63a4130311 changed polarity of is_min bit in range operation to better match vrange* instructions immediate encoding 2014-08-04 21:08:00 +00:00
Stanislav Shwartsman
fefa61a7cb Implemented VRANGE* AVX512DQ instructions 
The only missing AVX512BW/AVX512DQ opcodes are now:

"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-08-04 20:30:46 +00:00
Stanislav Shwartsman
524a73f48c prepare softfloat functions for vrange* instructions implementation 2014-08-04 19:44:25 +00:00
Stanislav Shwartsman
23a8601ab8 fixed code duplication in floating point compare functions 2014-08-03 19:53:02 +00:00
Stanislav Shwartsman
b7f62cdf47 Implemented VPALIGNR AVX512BW instructions 
The only missing AVX512BW/AVX512DQ opcodes are now:

"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-26 18:59:01 +00:00
Stanislav Shwartsman
b70ed32ea5 support fault suppression for recently added avx512bw ops 2014-07-25 21:45:09 +00:00
Stanislav Shwartsman
d8d4d2f0c1 Implemented VPSRLVW/VPSRAVW/VPSLLVW AVX512BW instructions 
The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-25 21:15:48 +00:00
Stanislav Shwartsman
7ad7383fd2 implement 256-wide SHUFF/SHUFI ops 2014-07-25 20:08:08 +00:00
Volker Ruppert
59eac1f196 Moved AVX/EVEX stuff to a new cpu subfolder and updated build system 
TODO: update MVSC workspace files
 2014-07-25 08:35:06 +00:00
Stanislav Shwartsman
9cc7b67369 bugfix 2014-07-22 20:49:58 +00:00
Stanislav Shwartsman
c4c8652a3b Implemented VPMOV?2? and VPMIN* AVX512 instructions 
The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F38.W1 10 VPSRLVW"
"512.66.0F38.W1 11 VPSRAVW"
"512.66.0F38.W1 12 VPSLLVW"

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-22 20:36:55 +00:00
Stanislav Shwartsman
ad7ef68876 Implemented VMULLQ AVX512DQ instruction 
The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F38.W1 10 VPSRLVW"
"512.66.0F38.W1 11 VPSRAVW"
"512.66.0F38.W1 12 VPSLLVW"

"512.F3.0F38.W0 28 VPMOVM2B
 512.F3.0F38.W1 28 VPMOVM2W"
"512.F3.0F38.W0 29 VPMOVB2M
 512.F3.0F38.W1 29 VPMOVW2M"

"512.F3.0F38.W0 38 VPMOVM2D
 512.F3.0F38.W1 38 VPMOVM2Q"
"512.F3.0F38.W0 39 VPMOVD2M
 512.F3.0F38.W1 39 VPMOVQ2M"

"NDS.512.66.0F38.WIG 38 VPMINSB"
"NDS.512.66.0F38.WIG 3A VPMINUW"

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-21 19:08:44 +00:00
Stanislav Shwartsman
009629f4d9 Implemented VEXTRACT* AVX512DQ instructions 
The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F38.W1 10 VPSRLVW"
"512.66.0F38.W1 11 VPSRAVW"
"512.66.0F38.W1 12 VPSLLVW"

"512.F3.0F38.W0 28 VPMOVM2B
 512.F3.0F38.W1 28 VPMOVM2W"
"512.F3.0F38.W0 29 VPMOVB2M
 512.F3.0F38.W1 29 VPMOVW2M"

"512.F3.0F38.W0 38 VPMOVM2D
 512.F3.0F38.W1 38 VPMOVM2Q"
"512.F3.0F38.W0 39 VPMOVD2M
 512.F3.0F38.W1 39 VPMOVQ2M"

"NDS.512.66.0F38.WIG 38 VPMINSB"
"NDS.512.66.0F38.WIG 3A VPMINUW"

"W1.NDS.512.66.0F38 40 VPMULLQ"

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
 2014-07-20 20:46:48 +00:00
Stanislav Shwartsman
8108da227d bugfix in canonical violation detection 2014-07-20 18:19:02 +00:00
Stanislav Shwartsman
65ffcf5dc8 avoid using access_write_linear when not strickly needed 2014-07-19 20:01:44 +00:00
Stanislav Shwartsman
8ef5dcaca3 implement more avx512bw opcodes 2014-07-19 19:01:17 +00:00
Stanislav Shwartsman
7083e94077 implemented VBROADCAST*32x2 AVX512DQ opcodes 2014-07-19 18:36:38 +00:00
Stanislav Shwartsman
ca2859f449 implemented more AVX512BW opcodes 2014-07-19 13:30:54 +00:00
Stanislav Shwartsman
caad957384 bugfix in softfloat uint64_to_float64 conversion 2014-07-18 20:30:48 +00:00
Stanislav Shwartsman
3e8a5b99fa bugfix for vpsrldq opcode decoding 2014-07-18 20:08:10 +00:00
Stanislav Shwartsman
7a133766a8 implemented more AVX512BW opcodes 2014-07-18 19:40:27 +00:00
Stanislav Shwartsman
a556eb21fa implemented more AVX512BW opcodes 2014-07-18 16:28:44 +00:00
Stanislav Shwartsman
47e7e4adde bugfix in VFPCLASSPD implementation 2014-07-18 16:01:11 +00:00
Stanislav Shwartsman
48c508012f semantic fix 2014-07-18 12:35:17 +00:00
Stanislav Shwartsman
a06fba41ab commit new added files 2014-07-18 11:16:22 +00:00
Stanislav Shwartsman
94864fb9bc Implement AVX512BW and AVX512DQ extensions published in recently published Intel Archtecture Extensions manual rev20. 
https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf

Most of the instructions are implemented, more on the way.

+ few bugfixes for legacy AVX-512 emulation

AVX-512: Fixed bug in VCMPPS masked instruction implementation with 512-bit data size
AVX-512: Fixed AVX-512 masked convert instructions with non-k0 mask (behaved as non masked versions)
AVX-512: Fixed missed #UD due to invalid EVEX prefix fields for several AVX-512 opcodes (VFIXUPIMMSS/SD, FMA)
 2014-07-18 11:14:25 +00:00
Stanislav Shwartsman
0f39ce58be fixed compilation warnings and errors with MSVCPP 2014-07-09 16:08:16 +00:00
Stanislav Shwartsman
6ee7f48985 bugfix for VMX_VM_EXEC_CTRL1_EXTERNAL_INTERRUPT_VMEXIT control handling 2014-07-08 19:15:54 +00:00
Stanislav Shwartsman
816f5cc2d7 fixed massive code duplication 2014-07-03 06:40:42 +00:00
Stanislav Shwartsman
1e46de78ad add proper alignment of XMM/YMM/ZMM registers within CPU class 2014-06-25 19:12:14 +00:00
Stanislav Shwartsman
8e750e27c8 following many users requests - allow sandy bridge configuration even when AVX is not compiled in, just disable AVX in it 2014-06-06 18:29:28 +00:00
Stanislav Shwartsman
0b2364501d fixed compilation err when 3dnow is ON 2014-06-01 10:46:17 +00:00
Stanislav Shwartsman
d19727d75b updated AMD feature names in cpuid.h (taken from latest AMD software dev manuals) 2014-05-05 20:11:14 +00:00
Stanislav Shwartsman
2fe0aaa472 added configure option for trace linking optimization and mention it in CHANGES 2014-05-01 18:30:23 +00:00
Stanislav Shwartsman
8fbf673295 fixed compilation errors with FPU off 2014-04-29 18:49:38 +00:00
Stanislav Shwartsman
be6d2668c7 fixed comments in the code 2014-04-24 18:02:40 +00:00
Stanislav Shwartsman
be368f54d1 remove redundant type conversions 2014-03-23 20:01:58 +00:00
Stanislav Shwartsman
c079702a4d Finish softfloat implementation of float32/64_scalef. This checkin completes AVX-512 implementation. 2014-03-21 20:18:03 +00:00
Stanislav Shwartsman
1e7b6ff2cd check if XMM reg is clear using dedicated function 2014-03-17 20:50:59 +00:00
Stanislav Shwartsman
ab6230a9a8 Implemented XSAVEC instruction emulation and XINUSE optimization in the XSAVEOPT instruction 2014-03-17 20:29:44 +00:00
Stanislav Shwartsman
d8fa7aa28a implemented INIT optimization for XSAVEOPT instruction 2014-03-16 21:56:30 +00:00
Stanislav Shwartsman
72b715e5f0 fixed XSAVE to match spec, implemented first look into XINUSE. TODO: use XINUSE to optimize XSAVEOPT as well 2014-03-16 21:03:13 +00:00
Stanislav Shwartsman
97d2965d58 continue xsave code rework 2014-03-16 20:37:47 +00:00
Stanislav Shwartsman
9d8d895b52 cpuid fixes 2014-03-15 20:19:30 +00:00
Stanislav Shwartsman
378e7e16eb fixed major code duplication in CPUDB classes 2014-03-15 19:24:42 +00:00
Stanislav Shwartsman
d18cabc7a9 add new CPUDB files 2014-03-15 18:31:33 +00:00
Stanislav Shwartsman
c87605722b CPUDB: added AMD Trinity to the database 2014-03-15 18:30:13 +00:00
Stanislav Shwartsman
d10fa93d89 fixed to VSCALEF instruction + one more step in the implementation in the softfloat 2014-03-14 20:26:50 +00:00
Stanislav Shwartsman
08f5383831 fix for x87 2014-03-09 22:06:13 +00:00
Stanislav Shwartsman
02e19de346 Added shape of implementation for last missing VSCALEF* AVX-512 instructons. 
The softfloat implementation is still missing (only corner cases are supported).
Extend softfloat floatNN_class methods to distinguish between SNaN and QNaN.
 2014-03-09 21:42:11 +00:00
Stanislav Shwartsman
211208dc30 zero masking is not allowed for all forms of vsib, including gather 2014-03-08 20:27:10 +00:00
Stanislav Shwartsman
48ab171b79 enumerate possible fetchdecode failures leading to #UD decoding. TODO: add this info to BX_IA_ERROR as immediate 2014-03-08 20:09:00 +00:00
Stanislav Shwartsman
069498eef6 zero masking is not allowed for mem destination instructions 2014-03-08 19:49:35 +00:00
Stanislav Shwartsman
bfe6ecabb8 xsave sse state using same interface as all other advanced states 2014-03-04 21:06:29 +00:00
Stanislav Shwartsman
39bb48cd69 added missing includes 2014-03-02 19:18:05 +00:00
Stanislav Shwartsman
c544e82c43 fixed code duplication in BEXTR implementations 2014-03-02 19:16:13 +00:00
Stanislav Shwartsman
bc5af269b7 Fix some more code duplication with sclaar_arith.h 
Do not clear IA32_FEATURE_CTRL MSR on soft reset (will clear the VMX lock bit)
On real HW XSAVE/XRSTOR which is not 4-byte aligned cause #AC(0) intead of #GP(0) when alignment check is enabled
 2014-03-02 16:40:13 +00:00
Stanislav Shwartsman
402b2c01c9 Implemented AVX-512 conflict detection instructions (VPCONFLICT, VPLZCNT, VPBROADCASTMB2Q, VPBROADCASTMW2D) 
Only missed AVX-512 opcodes are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD
 2014-02-27 21:12:02 +00:00
Stanislav Shwartsman
695d245116 Implemented VRNDSCALE AVX-512 instructions. 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD
 2014-02-27 18:27:57 +00:00
Stanislav Shwartsman
f282fc4e75 use names instead of magic numbers 2014-02-26 20:49:23 +00:00
Stanislav Shwartsman
2f906d844c fix vmexit reason descriptions 2014-02-25 19:56:10 +00:00
Stanislav Shwartsman
01af7f5346 Implemented VRSQRT14 AVX-512 instructions & optimized legacy SSE RSQRTSS/PS instructions handling 
//
// The table lookup was reverse-engineered from VRSQRT14SS instruction implementation available
// in the Intel Software Development Emulator rev6.20 (released February 13, 2014)
// http://software.intel.com/en-us/articles/intel-software-development-emulator/
//

// TODO: find better way to emulate these instructions, I am sure the HW doesn't have 64K entry lookup tables

Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
 2014-02-25 18:57:49 +00:00
Stanislav Shwartsman
47b56a2174 regen dependencies in Makefile 2014-02-24 21:36:11 +00:00
Stanislav Shwartsman
38bcc164a7 Implemented VRCP14 AVX-512 instructions. 
//
// The table lookup was reverse-engineered from VRCP14SS instruction implementation available
// in the Intel Software Development Emulator rev6.20 (released February 13, 2014)
// http://software.intel.com/en-us/articles/intel-software-development-emulator/
//

// TODO: find better way to emulate these instructions, I am sure the HW doesn't have 64K entry lookup table

Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
 2014-02-24 21:31:52 +00:00
Stanislav Shwartsman
648221d419 rewritten xsave/xrestor for more modular functionality. todo: replace walk through state using simple for loop 2014-02-22 21:00:47 +00:00
Stanislav Shwartsman
0a1b4f1c7e added template for missing avx-512 instructions 2014-02-17 20:21:58 +00:00
Stanislav Shwartsman
5ab2bb363c fix of compilation err 2014-02-17 16:19:43 +00:00
Stanislav Shwartsman
7775483d5e Implemented VCVTPS2PH AVX-512 instruction 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
 2014-02-15 19:21:08 +00:00
Stanislav Shwartsman
b572e80818 bugfix and code cleanup 2014-02-12 20:31:22 +00:00
Stanislav Shwartsman
09414f2f4b implemented access to opmask AVX-512 registers from debugger, fixed enhdbg buffer overflow with EVEX enabled 2014-02-11 20:51:18 +00:00
Stanislav Shwartsman
41f926628c fixed bug in LOAD_BROADCAST_MASK_Half_VectorD method 2014-02-11 20:13:42 +00:00
Stanislav Shwartsman
9d97013067 bugfixes in softfloat unsigned conversions 2014-02-11 18:03:51 +00:00
Stanislav Shwartsman
18e9f1e70e bugfix 2014-02-11 17:47:52 +00:00
Stanislav Shwartsman
b510cf794b complete compressed displ feature support, bugfixes in AVX-512 code 2014-02-11 16:10:31 +00:00
Stanislav Shwartsman
ca4d2b5e6f cover some more opcodes with compressed displ 2014-02-10 21:49:41 +00:00
Stanislav Shwartsman
d257bf3e7d cover some more opcodes with compressed displ 2014-02-10 21:34:26 +00:00
Stanislav Shwartsman
9613e4b402 implementation of AVX-512 compressed displacement feature which is required for AVX-512 emu correctness (first step). todo: fix rest of EVEX opcodes 2014-02-10 21:12:08 +00:00
Stanislav Shwartsman
37330682ad remove code duplication, prepare for 512-bit evrsion of cvtps2ph 2014-02-08 19:18:17 +00:00
Stanislav Shwartsman
550e6bd307 moved (c) to year 2014 for few files 2014-02-06 17:06:25 +00:00
Stanislav Shwartsman
aea9ae1976 added definitions (CPUID bit, VMX fields and VMXEXIT reasons, etc) from recently published Intel SDM rev049 2014-02-06 17:05:20 +00:00
Stanislav Shwartsman
7a6727da34 implemented AVX-512 version of VCVTPH2PS 2014-02-04 20:32:54 +00:00
Stanislav Shwartsman
f047fef2a6 fixed gcc warning 2014-02-03 21:12:24 +00:00
Stanislav Shwartsman
ea390abd3c bugfixes in new GETMANT* instrs 2014-02-03 21:10:44 +00:00
Stanislav Shwartsman
b33f93b9f3 Implemented VGETMANT* AVX-512 instructions 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
 2014-02-03 20:40:46 +00:00
Stanislav Shwartsman
ac06ee46ae Implemented VPMOVSX*/VPMOVZX* AVX-512 instructions 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 26 VGETMANTPS
512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
NDS.LIG.66.0F3A.W1 27 VGETMANTSD
 2014-02-02 19:56:08 +00:00
Stanislav Shwartsman
55e1d53a48 implement DPPS/DPPD ops using existing primitives; added some missing defs 2014-02-02 18:57:25 +00:00
Stanislav Shwartsman
ca1b496efc small optimization 2014-02-01 19:23:41 +00:00
Stanislav Shwartsman
ef130ca145 convert some defines to enum 2014-01-31 19:40:34 +00:00
Stanislav Shwartsman
6eb1c7d255 fixed swapped sources of VEXTRACTF* with mask 2014-01-30 21:46:25 +00:00
Stanislav Shwartsman
ccb003b0e1 fixed swapped sources of VEXTRACTF* 2014-01-30 20:48:41 +00:00
Stanislav Shwartsman
41e13703a3 Implemented VEXTRACT* AVX-512 instructions 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.WIG 21 VPMOVSXBD
512.66.0F38.WIG 22 VPMOVSXBQ
512.66.0F38.WIG 23 VPMOVSXWD
512.66.0F38.WIG 24 VPMOVSXWQ
512.66.0F38.W0  25 VPMOVSXDQ

512.66.0F38.WIG 31 VPMOVSZBD
512.66.0F38.WIG 32 VPMOVSZBQ
512.66.0F38.WIG 33 VPMOVSZWD
512.66.0F38.WIG 34 VPMOVSZWQ
512.66.0F38.W0  35 VPMOVSzDQ

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 26 VGETMANTPS
512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
NDS.LIG.66.0F3A.W1 27 VGETMANTSD
 2014-01-30 20:31:08 +00:00
Stanislav Shwartsman
d990911cea bugfix 2014-01-28 19:52:51 +00:00
Stanislav Shwartsman
63e99da4af Implemented VALIGN* AVX-512 instructions 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.WIG 21 VPMOVSXBD
512.66.0F38.WIG 22 VPMOVSXBQ
512.66.0F38.WIG 23 VPMOVSXWD
512.66.0F38.WIG 24 VPMOVSXWQ
512.66.0F38.W0  25 VPMOVSXDQ

512.66.0F38.WIG 31 VPMOVSZBD
512.66.0F38.WIG 32 VPMOVSZBQ
512.66.0F38.WIG 33 VPMOVSZWD
512.66.0F38.WIG 34 VPMOVSZWQ
512.66.0F38.W0  35 VPMOVSzDQ

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 19 VEXTRACTF32x4
512.66.0F3A.W1 1B VEXTRACTF64x4
512.66.0F3A.W0 39 VEXTRACTI32x4
512.66.0F3A.W1 3B VEXTRACTI64x4

512.66.0F3A.W0 26 VGETMANTPS
512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
NDS.LIG.66.0F3A.W1 27 VGETMANTSD
 2014-01-28 19:36:46 +00:00
Stanislav Shwartsman
36ba25847f Implemented last missed AVX-512 unsigned convert instructions 
The only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.WIG 21 VPMOVSXBD
512.66.0F38.WIG 22 VPMOVSXBQ
512.66.0F38.WIG 23 VPMOVSXWD
512.66.0F38.WIG 24 VPMOVSXWQ
512.66.0F38.W0  25 VPMOVSXDQ

512.66.0F38.WIG 31 VPMOVSZBD
512.66.0F38.WIG 32 VPMOVSZBQ
512.66.0F38.WIG 33 VPMOVSZWD
512.66.0F38.WIG 34 VPMOVSZWQ
512.66.0F38.W0  35 VPMOVSzDQ

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
 512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
 NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
 512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
 NDS.LIG.66.0F38.W1 4F VRSQRT14SD

NDS.512.66.0F3A.W0 03 VALIGND
NDS.512.66.0F3A.W1 03 VALIGNQ

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 19 VEXTRACTF32x4
512.66.0F3A.W1 1B VEXTRACTF64x4
512.66.0F3A.W0 39 VEXTRACTI32x4
512.66.0F3A.W1 3B VEXTRACTI64x4

512.66.0F3A.W0 26 VGETMANTPS
 512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
 NDS.LIG.66.0F3A.W1 27 VGETMANTSD
 2014-01-28 12:57:38 +00:00
Stanislav Shwartsman
15979a52b6 implemented avx-512 getexp instructions 2014-01-27 21:25:07 +00:00
Stanislav Shwartsman
3798ed66b5 new function for disasm. todo: support it independently of CPU 2014-01-26 20:01:50 +00:00
Stanislav Shwartsman
2379590dde do not compile AVX objects if AVX support is not enabled in configure 2014-01-26 19:20:44 +00:00
Stanislav Shwartsman
4d4d194c16 implemented missed vpmul* avx-512 opcodes 2014-01-24 20:04:36 +00:00
Stanislav Shwartsman
8d6c6a4545 added one more missed perm* avx-512 opcode 2014-01-24 19:42:08 +00:00
Stanislav Shwartsman
7beb85b850 implemented vperm* avx-512 opcodes 2014-01-24 19:23:19 +00:00
Stanislav Shwartsman
fd8ddd8069 downgrade VMEXIT message to BX_DEBUG 2014-01-24 18:58:57 +00:00
Stanislav Shwartsman
407681c98a implemented some more avx-512 opcodes 2014-01-24 12:02:47 +00:00
Stanislav Shwartsman
fa60a654c8 bugfix for avx-512 2014-01-23 19:59:39 +00:00
Stanislav Shwartsman
79c11cacbe fixed compilation err without avx 2014-01-23 17:08:30 +00:00
Stanislav Shwartsman
33889cd02e implemented avx-512 vpermq opcode 2014-01-22 21:21:32 +00:00
Stanislav Shwartsman
99f7107dd1 code reorg 2014-01-22 19:59:13 +00:00
Stanislav Shwartsman
a21f03e69b implemented few more avx-512 cvt opcodes 2014-01-21 21:00:40 +00:00
Stanislav Shwartsman
d591c1dd34 implemented few more avx-512 cvt opcodes 2014-01-21 20:31:10 +00:00
Stanislav Shwartsman
9e90d9d9ae bugfix in cvtpd2udq opcode decoding with kmask 2014-01-20 22:07:35 +00:00
Stanislav Shwartsman
2ed0e91dfe fixed writing half vector for avx-512 2014-01-20 21:52:48 +00:00
Stanislav Shwartsman
4705ed6bdd more fixes for uint conversions based on latest QEMU patches by Tom Musta 2014-01-20 21:22:29 +00:00
Stanislav Shwartsman
649075527e fixes for convert to unsigned functions 2014-01-20 20:50:28 +00:00
Stanislav Shwartsman
cc112767a2 bugfixes 2014-01-19 21:19:41 +00:00
Stanislav Shwartsman
ee8d500ec0 fix for float32/64_to_uint32 cvt functions in softfloat 2014-01-19 20:47:48 +00:00
Stanislav Shwartsman
086fefeb29 cleanups 2014-01-19 20:30:40 +00:00
Stanislav Shwartsman
a63280a6d1 implemented few more AVX-512 cvt opcodes 2014-01-19 20:23:14 +00:00
Stanislav Shwartsman
ba52890538 implemented few more AVX-512 floating point convert instructions 2014-01-18 20:10:05 +00:00
Stanislav Shwartsman
a1e397b5a2 fixed decoding bug in avx-512 instruction tables 2014-01-12 13:37:29 +00:00
Stanislav Shwartsman
ce8c520c09 fixed operands for new instructions 2014-01-12 13:20:41 +00:00
Stanislav Shwartsman
5cdcd7bef7 Implemented AVX-512 VPMOV* down-conversion stores 2014-01-12 13:08:16 +00:00
Stanislav Shwartsman
72c710947c code cleanups 2014-01-12 09:31:22 +00:00
Stanislav Shwartsman
af29c8bd60 infrastructure change for avx-512: before going to more new instructions modelling 2014-01-10 19:40:38 +00:00
Stanislav Shwartsman
58470763fa implement few more avx-512 opcodes 2013-12-31 23:51:25 +00:00
Stanislav Shwartsman
350e3544ae fixed #UD condition for multi-byte prefix opcodes VEX/EVEX/XOP 2013-12-28 12:57:21 +00:00
Stanislav Shwartsman
e902a83a60 fixed segfault in AVX emulation 2013-12-22 21:16:10 +00:00
Stanislav Shwartsman
ada455c4b9 just coding style 2013-12-22 20:48:26 +00:00
Stanislav Shwartsman
e200d04ad5 implemented two AVX512 unsigned CVT instructions 2013-12-22 19:53:03 +00:00
Stanislav Shwartsman
776cabf4fe move canonical check of high part of page split access to another function to fix code duplication 2013-12-21 21:56:55 +00:00
Stanislav Shwartsman
543b6c8254 compilation fix 2013-12-21 21:08:35 +00:00
Stanislav Shwartsman
979e10b725 added simd_int.h functions for future use 2013-12-21 20:46:27 +00:00
Stanislav Shwartsman
8c3309bac0 regen dependencies for CPU sources 2013-12-17 21:15:15 +00:00
Stanislav Shwartsman
e30e66e481 insertf64x4 decode fix 2013-12-17 21:00:19 +00:00
Stanislav Shwartsman
da0cec4300 implemented AVX-512 VINSERTF*/VINSERTI* opcodes 2013-12-17 20:38:19 +00:00
Volker Ruppert
58019a1649 Renamed "ltdl.h" to "ltdl-bochs.h" to avoid conflicts with the include file 
that is a part of the libtool package. Updated Makefile dependencies.
TODO: check if we can get rid of the ltdl*.* files (this would be possible if
the ltdl library is always available if libtool is present).
 2013-12-17 19:57:40 +00:00
Stanislav Shwartsman
fc2cc377f8 fixes for AVX-512 2013-12-17 19:16:08 +00:00
Stanislav Shwartsman
734d1c7af8 implemented VFIXUPIMM AVX-512 opcodes 2013-12-17 16:44:46 +00:00
Stanislav Shwartsman
cdbc8a3f6f remove accidentally committed code 2013-12-15 20:50:02 +00:00
Stanislav Shwartsman
18f6a67d9d bugfix 2013-12-15 20:33:24 +00:00
Stanislav Shwartsman
51d0161148 implement few AVX-512 unsigned convert instructions 2013-12-15 20:07:57 +00:00
Stanislav Shwartsman
d3107f9f25 remove statement with no effect 2013-12-15 19:58:15 +00:00
Stanislav Shwartsman
7f98bbaea0 fix for float32_to_uint32_round_to_zero 2013-12-15 19:45:23 +00:00
Stanislav Shwartsman
8707e0626d starting to implement some AVX512 convert opcodes 2013-12-15 19:20:03 +00:00
Stanislav Shwartsman
a9b4513b8a insert/extractps do not support EVEX.b 2013-12-14 12:48:26 +00:00
Stanislav Shwartsman
cbcf30e911 implement EVEX SAE (suppress all exceptions) contol, implement AVX512 INSTERT/EXTRACTPS opcodes 2013-12-14 12:45:06 +00:00
Stanislav Shwartsman
15756a31cd implemented EVEX MOVD/MOVQ opcodes, fixes in softfloat 2013-12-13 12:05:47 +00:00
Stanislav Shwartsman
374b8f615a softloat: implemented some more unsigned integer vs float conversions 2013-12-12 21:00:59 +00:00
Stanislav Shwartsman
9c179bade8 fixed evex.b validation condition 2013-12-10 21:48:17 +00:00
Stanislav Shwartsman
258a60f3fa Implemented AVX512 EXPAND/COMPRESS instructions 
Fixed memory access size for AVX shift instructions with shift count in memory
Do not allow to encode with EVEX.b instructions which do not support implicit broadcast 
softfloat: prepare float32/64 to uint32 conversion functions
 2013-12-10 21:09:46 +00:00
Stanislav Shwartsman
9a4d947a28 implemented avx-512 cvt*2si instructions 2013-12-09 20:52:39 +00:00
Stanislav Shwartsman
ccb1d86d6e code cleanups 2013-12-09 20:36:24 +00:00
Stanislav Shwartsman
d20c81417c Implemented VSHUFF32x4/64x2, VSHUFI32x4/64x2 AVX512 instructions 
Implemented AVX512 blend instructions
Do not allow setting of EVEX.b in reg form when no floating point exceptions could be generated by instruction
 2013-12-09 19:09:37 +00:00
Stanislav Shwartsman
4c78ca8c1c implemented mask load for most of the load+op instructions. all take care for instructions which do not support maksing of memory exceptions (shuffle and permutes) 2013-12-08 21:54:59 +00:00
Stanislav Shwartsman
8836d1aa2d added mask destination to disasm 2013-12-08 17:01:30 +00:00
Stanislav Shwartsman
0621f2a983 extend movddup/sldup/shdup to 512-bit vlen 2013-12-07 20:58:32 +00:00
Stanislav Shwartsman
d681bd868f fixed typo bug in xmm accessor definition 2013-12-07 20:48:41 +00:00
Stanislav Shwartsman
1e474ede51 fixed corrupted fetchdecode from svn rev12001 2013-12-07 20:30:27 +00:00
Stanislav Shwartsman
7ed017a56d implemented avx-512 gather/scatter 2013-12-07 20:15:56 +00:00
Stanislav Shwartsman
3154c3682e fixed decoding of RDRAND instructions 2013-12-07 07:17:04 +00:00
Stanislav Shwartsman
8c3d0aed7a added #UD condition for wrong EVEX.LL setting 2013-12-05 20:40:53 +00:00
Stanislav Shwartsman
ca2793ac76 Debugger: fixed param tree access to 64-bit variables (need to use get64() instead of get()) 
Debugger: if AVX-512 if not supported by current configuration do not print high256 of vector registers and zmm15..zmm31 in AVX command
Implement VBROADCASTF64x4, VBROADCASTF32x4, VBROADCASTFI64x4, VBROADCASTI32x4 AVX-512 instructions
Fetchdecode optimizations and bugfixes
 2013-12-05 19:17:16 +00:00
Stanislav Shwartsman
cfc8a0ad38 get rid of BX_MEM_NO_VVV decoding form (by splitting just two opcode groups using Split11B) 2013-12-04 20:15:22 +00:00
Stanislav Shwartsman
401caf168d Implemented VPERMILPS/PD AVX512 instructions 
Implemented VPTERNLOGD/Q AVX512 instructions
Implemented VPBROADCASTD/Q, VPBROADCASTPS/PD AVX512 instructions
Implemented VTEST* AVX512 instructions
Bugfixes in EVEX decoding tables
 2013-12-04 18:30:44 +00:00
Stanislav Shwartsman
a5153c348f fixed bugs in vcmp* avx512 opcodes 2013-12-03 22:16:22 +00:00
Stanislav Shwartsman
ccdd21a76b small diet to the avx-512 files - remove code duplication 2013-12-03 21:32:04 +00:00
Stanislav Shwartsman
18922fa1a3 added sanity check assert 2013-12-03 17:41:13 +00:00
Stanislav Shwartsman
6d9b16e0f7 Implemented VCMPPS/PD/SS/SD AVX512 instructions 
Implemented AVX512 shift/rotate instructions
 2013-12-03 15:44:23 +00:00
Stanislav Shwartsman
ba505677d2 bugfix for avx-512 masked load with mask all-zero 2013-12-02 20:46:26 +00:00
Stanislav Shwartsman
a85a9081b7 use shorter opcode names in the debug prints (skip the BX_IA_ prefix) 2013-12-02 20:06:59 +00:00
Stanislav Shwartsman
0683b00535 implemented more avx-512 opcodes 2013-12-02 19:16:48 +00:00
Stanislav Shwartsman
79456eb7e1 Implemented VPCMP* AVX512 instructions 
Implemented VMOVNTPS/PD/DQ AVX512 instructions
Implemented VMOVNTDQA AVX512 instruction
Bugfixes for AVX-512
 2013-12-02 18:05:18 +00:00
Stanislav Shwartsman
b78489628d make use of new accessor 2013-12-01 22:21:55 +00:00
Stanislav Shwartsman
287523e19a add dedicated 8bit low register accessor 2013-12-01 22:18:38 +00:00
Stanislav Shwartsman
4aa5199d0c added missing decoding for avx-512 fma flavor 2013-12-01 21:50:19 +00:00
Stanislav Shwartsman
4f158aef5f Fixed 8-bit opmask read 
Added opmask printout for AVX dump in dbg_main.cc
 2013-12-01 20:50:01 +00:00
Stanislav Shwartsman
c7b03eb00b implement avx-512 vpabsd/q instructions 2013-12-01 20:10:39 +00:00
Stanislav Shwartsman
2b83146ae2 more avx-512 instructions implemented 2013-12-01 19:39:18 +00:00
Stanislav Shwartsman
37d6403681 typo fix 2 2013-11-30 19:57:03 +00:00
Stanislav Shwartsman
32c91015a7 typo fix 2013-11-30 19:55:10 +00:00
Stanislav Shwartsman
fb2521a1fe implemented avx-512 vsqrt instructions 2013-11-30 19:33:08 +00:00
Stanislav Shwartsman
7db6c647b0 fixed memory access decoding in presence of evex prefix 2013-11-30 18:51:27 +00:00
Stanislav Shwartsman
ac82b38736 fixed typos causing compilation err 2013-11-30 18:39:22 +00:00
Stanislav Shwartsman
d082c6a0f9 implemented avx-512 masked load instructions 2013-11-30 18:37:25 +00:00
Stanislav Shwartsman
f76c85dca9 fixed 512-bit VL encoding in EVEX 2013-11-29 21:05:29 +00:00
Stanislav Shwartsman
b820b7af57 fixed zmm reg name in disasm 2013-11-29 20:52:34 +00:00
Stanislav Shwartsman
61deec2689 fixed zmm reg name in disasm 2013-11-29 20:48:31 +00:00
Stanislav Shwartsman
11f082af82 Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions 
Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions
Fix vector length values for AVX-512 (512-bit vector should have length 4)
support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions
move AVX512 load/store and register move operations into dedicated file avx512_move.cc
 2013-11-29 20:22:31 +00:00
Stanislav Shwartsman
031583dbd9 moved avx masked load/store operations to separate functions 2013-11-29 18:15:48 +00:00
Stanislav Shwartsman
21bb1363ac avx512 move functions introduced 2013-11-29 11:10:34 +00:00
Stanislav Shwartsman
1a735e9fdf bugfix for decoding segment prefix with EVEX 2013-11-28 21:28:50 +00:00
Stanislav Shwartsman
4680c22d0e implemented avx-512 masked register moves 2013-11-28 20:58:31 +00:00
Stanislav Shwartsman
b7f950aa5c more coding for avx512 2013-11-26 19:22:31 +00:00
Stanislav Shwartsman
1beeb33b51 implemented avx-512 fma instructions (in seperate file), fixes in avx-512 decoding tables 2013-11-25 20:42:24 +00:00
Stanislav Shwartsman
eb9778220d fixed decoding of 0f3a opcode map 2013-11-20 20:46:03 +00:00
Stanislav Shwartsman
b553591bb4 fixed compilation error under AVX 2013-11-20 17:33:57 +00:00
Stanislav Shwartsman
7f8429c643 fix code duplication in fetchdecode modules 2013-11-20 16:00:24 +00:00
Stanislav Shwartsman
9b22ba7edf softfloat: added float to uint64 conversion operations (based on QEMU patch by Tom Musta) 2013-11-10 19:08:12 +00:00
Stanislav Shwartsman
3be7e5884b added lock prefix used info into bx_Instriction_c and use it in disasm 2013-11-08 21:43:21 +00:00
Stanislav Shwartsman
4b03247287 fixed compilation error with vs2008 2013-10-25 05:36:10 +00:00
Stanislav Shwartsman
d9fc472ba7 Added VMEXIT instrumentation callback 
Fixed possible RSP corruption in SMP mode - the speculative_rsp variable might be not reset properly
 2013-10-23 21:18:19 +00:00
Stanislav Shwartsman
d52adaa0ee improve debug print to the log file which is printed in case of triple fault - tell VMX host/guest info 2013-10-20 16:41:34 +00:00
Stanislav Shwartsman
39f2f172b5 fixed PAUSE/NOP decoding bug in prev commit 2013-10-16 05:46:57 +00:00
Stanislav Shwartsman
8bcc8cf073 split PREFETCH opcode to Group16 for better disasm of bxInstruction_c 2013-10-15 21:21:28 +00:00
Stanislav Shwartsman
940c2a1c8e fixes for disasm 2013-10-15 17:19:18 +00:00
Stanislav Shwartsman
e1012f1165 add vmcs revision id interface to CPUID class 2013-10-14 18:35:56 +00:00
Stanislav Shwartsman
9fb7384e6b finish sse tables cleanup in disasm and fetchdecode 2013-10-11 20:09:51 +00:00
Stanislav Shwartsman
05d2bb2b9a fixed typo bug caused spurios #UD on SSE shift 2013-10-11 06:20:42 +00:00
Stanislav Shwartsman
5fc491e9b6 resolve aliases after actually decoding base instr 2013-10-11 05:58:30 +00:00
Stanislav Shwartsman
34025e469f resolve aliases after actually decoding base instr 2013-10-11 05:54:18 +00:00
Stanislav Shwartsman
582bf84bae apply same optimization to disasm as well 2013-10-10 21:00:26 +00:00
Stanislav Shwartsman
46e36b463b size-optimization for SSE opcode tables 2013-10-10 20:21:15 +00:00
Stanislav Shwartsman
2ec138f96e Apply patch from developers mailing list: 
bx_debug: allow expressions instead of numerals, where relevant
by Samium Gromoff

fix code duplication in fma handlers
 2013-10-09 20:04:05 +00:00
Stanislav Shwartsman
0b2e533a55 more avx512 instructions done 2013-10-09 19:45:36 +00:00
Stanislav Shwartsman
d6d1c707df implemented set of integer avx512 instructions 2013-10-08 19:44:52 +00:00
Stanislav Shwartsman
70230049fa opmask_ok support in fetchdecode32.cc 2013-10-08 18:40:10 +00:00
Stanislav Shwartsman
09254eb474 avx512 implementation fixes and next steps 2013-10-08 18:31:18 +00:00
Stanislav Shwartsman
8446685ba2 fixed FPU and MMX disasm 2013-10-07 20:55:43 +00:00
Stanislav Shwartsman
5724013e7d updates to AVX512 decoding and CPUID 2013-10-07 20:39:34 +00:00
Stanislav Shwartsman
cb0eee9456 disasm fixes 2013-10-07 19:02:53 +00:00
Stanislav Shwartsman
059769e2a6 disasm bug fixes 2013-10-06 20:42:13 +00:00
Stanislav Shwartsman
f0b917ca15 disasm fixes 2013-10-06 19:27:40 +00:00
Stanislav Shwartsman
e55611df21 disasm fixes 2013-10-06 19:04:52 +00:00
Stanislav Shwartsman
add8eea761 disasm bug fixes 2013-10-06 18:37:56 +00:00
Stanislav Shwartsman
f1f35a236c disasm: Id form in 32-bit should be sign-extended to 64-bit 2013-10-06 18:10:58 +00:00
Stanislav Shwartsman
a392612b03 fixed compilation err in cpu-level=3 config 2013-10-06 18:01:25 +00:00
Stanislav Shwartsman
e1512ccaf8 fixed warning under new MSDEV compiler 2013-10-05 19:35:00 +00:00
Stanislav Shwartsman
fd370a4d41 fixes in disasm, added example of using bxInstruction_c disasm into dbg_main.cc (commented out for now) 2013-10-05 19:32:09 +00:00
Stanislav Shwartsman
b1d703e47c fixed compilation with x86-64 off 2013-10-05 18:51:28 +00:00
Stanislav Shwartsman
67bce7af97 fixed memref disasm 2013-10-05 11:00:31 +00:00
Stanislav Shwartsman
d4bfbffdbb disasm fixes 2013-10-05 08:34:09 +00:00
Stanislav Shwartsman
c9a1f259cb fixed compilation error in new disasm module under SMP config 2013-10-04 18:14:54 +00:00
Stanislav Shwartsman
ba1249ed15 disasm fixes 2013-10-04 17:26:56 +00:00
Stanislav Shwartsman
85b0402668 fixes for disasm 2013-10-02 19:23:34 +00:00
Stanislav Shwartsman
8c60799e72 fix for new disasm interface 2013-10-01 20:17:21 +00:00
Stanislav Shwartsman
e592f81209 updates to internal disasm 2013-10-01 18:47:55 +00:00
Stanislav Shwartsman
147d788022 few fixes in new disasm module 2013-09-30 20:16:52 +00:00
Stanislav Shwartsman
fd383435f0 - Initial code for bx_Instruction_c disassembler which (together with Bochs decoder) will replace Bochs disasm module someday (very soon). 
The code already knows to disasm most of the opcodes with their operands.

- Split according to OSIZE opcodes RDFSBASE/WRFSBASE / RDGSBASE/WRGSBASE both for disasm and performance

- Minimize amount of opcode forms in ia_opcodes.h again.
  For example Udq means the same as Wdq but with no memory form.
 2013-09-30 19:01:42 +00:00
Stanislav Shwartsman
fa06b26c88 Make possible to deliver instruction name for disasm directly from bx_ia_opcode_name (some opcodes were renamed). 
Fixed bug in stack optimization in 64-bit mode (should result in some speedup)
ia_opcode.h - eliminate some OP_M cases when they actually meant "value of specific type in the memory"
example: "MOVBE Md, Gd" actually means "MOVBE Ed, Gd"which just not have reg/reg form.
 2013-09-26 18:54:32 +00:00
Stanislav Shwartsman
839b841c38 added register type to register source information in decoder 2013-09-24 09:50:25 +00:00
Stanislav Shwartsman
ff79cbd596 Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm) 
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.

Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
 2013-09-24 05:21:00 +00:00
Stanislav Shwartsman
f791802286 infrastructure change for several AVX handlers to support any VL and only 128/256 2013-09-21 20:40:57 +00:00
Stanislav Shwartsman
404b8b1475 move end of trace indication to separate 'flags' field of bx_ia_opcode. this saves a lot of code duplication and simplifies the decode tables. also on the way found missing SVM opcodes that missed 'end of trace' mark 2013-09-21 18:58:01 +00:00
Stanislav Shwartsman
047b17d415 fixed typo in makefile 2013-09-21 10:52:18 +00:00
Stanislav Shwartsman
cd55ace8c8 fixed compilation err, rename opcode and handler functions for PUSHA/POPA instructions 2013-09-21 10:03:49 +00:00