mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions

Browse Source 
Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions
Fix vector length values for AVX-512 (512-bit vector should have length 4)
support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions
move AVX512 load/store and register move operations into dedicated file avx512_move.cc
This commit is contained in:
Stanislav Shwartsman 2013-11-29 20:22:31 +00:00
parent 031583dbd9
commit 11f082af82
11 changed files with 443 additions and 233 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
bochs/cpu/Makefile.in
View File

@ -140,6 +140,7 @@ OBJS64 = \
tbm64.o \
xop.o \
avx512.o \
avx512_move.o \
avx512_pfp.o \
avx512_fma.o \
avx512_mask16.o \
@ -762,6 +763,12 @@ avx512.o: avx512.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debu
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h descriptor.h \
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h fpu/softfloat.h \
fpu/tag_w.h fpu/status_w.h fpu/control_w.h xmm.h vmx.h stack.h simd_int.h
avx512_move.o: avx512_move.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../config.h ../osdep.h ../gui/siminterface.h ../cpudb.h \
../gui/paramtree.h ../memory/memory.h ../pc_system.h ../gui/gui.h \
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h descriptor.h \
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h fpu/softfloat.h \
fpu/tag_w.h fpu/status_w.h fpu/control_w.h xmm.h vmx.h stack.h simd_int.h
avx512_pfp.o: avx512_pfp.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../config.h ../osdep.h ../gui/siminterface.h ../cpudb.h \
../gui/paramtree.h ../memory/memory.h ../pc_system.h ../gui/gui.h \

16
bochs/cpu/avx.cc
View File

@ -620,7 +620,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsHpsMps(bxInstruction
opmask <<= 4;
opmask |= xmm_pmovmskd(&mask.ymm128(0));
avx_masked_load32(i, &result, opmask);
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
avx_masked_load32(i, eaddr, &result, opmask);
BX_WRITE_AVX_REGZ(i->dst(), result, i->getVL());
@ -637,7 +639,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdHpdMpd(bxInstruction
opmask <<= 2;
opmask |= xmm_pmovmskq(&mask.ymm128(0));
avx_masked_load64(i, &result, opmask);
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
avx_masked_load64(i, eaddr, &result, opmask);
BX_WRITE_AVX_REGZ(i->dst(), result, i->getVL());
@ -653,7 +657,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsHpsVps(bxInstruction
opmask <<= 4;
opmask |= xmm_pmovmskd(&mask.ymm128(0));
avx_masked_store32(i, &BX_READ_AVX_REG(i->src2()), opmask);
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
avx_masked_store32(i, eaddr, &BX_READ_AVX_REG(i->src2()), opmask);
BX_NEXT_INSTR(i);
}
@ -667,7 +673,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_MpdHpdVpd(bxInstruction
opmask <<= 2;
opmask |= xmm_pmovmskq(&mask.ymm128(0));
avx_masked_store64(i, &BX_READ_AVX_REG(i->src2()), opmask);
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
avx_masked_store64(i, eaddr, &BX_READ_AVX_REG(i->src2()), opmask);
BX_NEXT_INSTR(i);
}

205
bochs/cpu/avx512.cc
View File

@ -26,216 +26,11 @@
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_AVX
void BX_CPU_C::avx_masked_load32(bxInstruction_c *i, BxPackedAvxRegister *op, unsigned mask)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
unsigned len = i->getVL();
if (i->as64L()) {
for (unsigned n=0; n < (4*len); n++) {
if (mask & (1<<n)) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 4*n)))
exception(int_number(i->seg()), 0);
}
}
}
#if BX_SUPPORT_ALIGNMENT_CHECK
unsigned save_alignment_check_mask = BX_CPU_THIS_PTR alignment_check_mask;
BX_CPU_THIS_PTR alignment_check_mask = 0;
#endif
for (int n=4*len-1; n >= 0; n--) {
if (mask & (1<<n))
op->vmm32u(n) = read_virtual_dword(i->seg(), eaddr + 4*n);
else
op->vmm32u(n) = 0;
}
#if BX_SUPPORT_ALIGNMENT_CHECK
BX_CPU_THIS_PTR alignment_check_mask = save_alignment_check_mask;
#endif
}
void BX_CPU_C::avx_masked_load64(bxInstruction_c *i, BxPackedAvxRegister *op, unsigned mask)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
unsigned len = i->getVL();
if (i->as64L()) {
for (unsigned n=0; n < (2*len); n++) {
if (mask & (1<<n)) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 8*n)))
exception(int_number(i->seg()), 0);
}
}
}
#if BX_SUPPORT_ALIGNMENT_CHECK
unsigned save_alignment_check_mask = BX_CPU_THIS_PTR alignment_check_mask;
BX_CPU_THIS_PTR alignment_check_mask = 0;
#endif
for (int n=2*len-1; n >= 0; n--) {
if (mask & (1<<n))
op->vmm64u(n) = read_virtual_qword(i->seg(), eaddr + 8*n);
else
op->vmm64u(n) = 0;
}
#if BX_SUPPORT_ALIGNMENT_CHECK
BX_CPU_THIS_PTR alignment_check_mask = save_alignment_check_mask;
#endif
}
void BX_CPU_C::avx_masked_store32(bxInstruction_c *i, const BxPackedAvxRegister *op, unsigned mask)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
unsigned len = i->getVL();
#if BX_SUPPORT_X86_64
if (i->as64L()) {
for (unsigned n=0; n < (4*len); n++) {
if (mask & (1<<n)) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 4*n)))
exception(int_number(i->seg()), 0);
}
}
}
#endif
#if BX_SUPPORT_ALIGNMENT_CHECK
unsigned save_alignment_check_mask = BX_CPU_THIS_PTR alignment_check_mask;
BX_CPU_THIS_PTR alignment_check_mask = 0;
#endif
// see you can successfully write all the elements first
for (int n=4*len-1; n >= 0; n--) {
if (mask & (1<<n))
read_RMW_virtual_dword(i->seg(), eaddr + 4*n);
}
for (unsigned n=0; n < (4*len); n++) {
if (mask & (1<<n))
write_virtual_dword(i->seg(), eaddr + 4*n, op->vmm32u(n));
}
#if BX_SUPPORT_ALIGNMENT_CHECK
BX_CPU_THIS_PTR alignment_check_mask = save_alignment_check_mask;
#endif
}
void BX_CPU_C::avx_masked_store64(bxInstruction_c *i, const BxPackedAvxRegister *op, unsigned mask)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
unsigned len = i->getVL();
#if BX_SUPPORT_X86_64
if (i->as64L()) {
for (unsigned n=0; n < (2*len); n++) {
if (mask & (1<<n)) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 8*n)))
exception(int_number(i->seg()), 0);
}
}
}
#endif
#if BX_SUPPORT_ALIGNMENT_CHECK
unsigned save_alignment_check_mask = BX_CPU_THIS_PTR alignment_check_mask;
BX_CPU_THIS_PTR alignment_check_mask = 0;
#endif
// see you can successfully write all the elements first
for (int n=2*len-1; n >= 0; n--) {
if (mask & (1<<n))
read_RMW_virtual_qword(i->seg(), eaddr + 8*n);
}
for (unsigned n=0; n < (2*len); n++) {
if (mask & (1<<n))
write_virtual_qword(i->seg(), eaddr + 8*n, op->vmm64u(n));
}
#if BX_SUPPORT_ALIGNMENT_CHECK
BX_CPU_THIS_PTR alignment_check_mask = save_alignment_check_mask;
#endif
}
#endif // BX_SUPPORT_AVX
#if BX_SUPPORT_EVEX
#include "simd_int.h"
#include "simd_compare.h"
BX_CPP_INLINE void BX_CPU_C::avx512_write_regd_masked(bxInstruction_c *i, const BxPackedAvxRegister *op, unsigned mask)
{
unsigned len = i->getVL();
if (i->isZeroMasking()) {
for (unsigned n=0; n < len; n++, mask >>= 4)
xmm_zero_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op->vmm128(n), mask);
}
else {
for (unsigned n=0; n < len; n++, mask >>= 4)
xmm_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op->vmm128(n), mask);
}
}
BX_CPP_INLINE void BX_CPU_C::avx512_write_regq_masked(bxInstruction_c *i, const BxPackedAvxRegister *op, unsigned mask)
{
unsigned len = i->getVL();
if (i->isZeroMasking()) {
for (unsigned n=0; n < len; n++, mask >>= 4)
xmm_zero_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op->vmm128(n), mask);
}
else {
for (unsigned n=0; n < len; n++, mask >>= 4)
xmm_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op->vmm128(n), mask);
}
BX_CLEAR_AVX_REGZ(i->dst(), len);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_MASK_VpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
avx512_write_regd_masked(i, &op, BX_READ_16BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPD_MASK_VpdWpdR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
avx512_write_regq_masked(i, &op, BX_READ_8BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_MASK_VpsWpsM(bxInstruction_c *i)
{
BX_PANIC(("%s: not implemented yet !", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPD_MASK_VpdWpdM(bxInstruction_c *i)
{
BX_PANIC(("%s: not implemented yet !", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_MASK_WpsVpsM(bxInstruction_c *i)
{
avx_masked_store32(i, &BX_READ_AVX_REG(i->src()), BX_READ_16BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPD_MASK_WpdVpdM(bxInstruction_c *i)
{
avx_masked_store64(i, &BX_READ_AVX_REG(i->src()), BX_READ_8BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
#define AVX512_2OP_DWORD_EL(HANDLER, func) \
/* AVX-512 instruction with two src operands working on DWORD elements */ \
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C :: HANDLER (bxInstruction_c *i) \

311
bochs/cpu/avx512_move.cc Normal file
View File

@ -0,0 +1,311 @@
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2013 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
//
/////////////////////////////////////////////////////////////////////////
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_AVX
void BX_CPU_C::avx_masked_load32(bxInstruction_c *i, bx_address eaddr, BxPackedAvxRegister *op, unsigned mask)
{
unsigned len = i->getVL();
if (i->as64L()) {
for (unsigned n=0; n < (4*len); n++) {
if (mask & (1<<n)) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 4*n)))
exception(int_number(i->seg()), 0);
}
}
}
#if BX_SUPPORT_ALIGNMENT_CHECK
unsigned save_alignment_check_mask = BX_CPU_THIS_PTR alignment_check_mask;
BX_CPU_THIS_PTR alignment_check_mask = 0;
#endif
for (int n=4*len-1; n >= 0; n--) {
if (mask & (1<<n))
op->vmm32u(n) = read_virtual_dword(i->seg(), eaddr + 4*n);
else
op->vmm32u(n) = 0;
}
#if BX_SUPPORT_ALIGNMENT_CHECK
BX_CPU_THIS_PTR alignment_check_mask = save_alignment_check_mask;
#endif
}
void BX_CPU_C::avx_masked_load64(bxInstruction_c *i, bx_address eaddr, BxPackedAvxRegister *op, unsigned mask)
{
unsigned len = i->getVL();
if (i->as64L()) {
for (unsigned n=0; n < (2*len); n++) {
if (mask & (1<<n)) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 8*n)))
exception(int_number(i->seg()), 0);
}
}
}
#if BX_SUPPORT_ALIGNMENT_CHECK
unsigned save_alignment_check_mask = BX_CPU_THIS_PTR alignment_check_mask;
BX_CPU_THIS_PTR alignment_check_mask = 0;
#endif
for (int n=2*len-1; n >= 0; n--) {
if (mask & (1<<n))
op->vmm64u(n) = read_virtual_qword(i->seg(), eaddr + 8*n);
else
op->vmm64u(n) = 0;
}
#if BX_SUPPORT_ALIGNMENT_CHECK
BX_CPU_THIS_PTR alignment_check_mask = save_alignment_check_mask;
#endif
}
void BX_CPU_C::avx_masked_store32(bxInstruction_c *i, bx_address eaddr, const BxPackedAvxRegister *op, unsigned mask)
{
unsigned len = i->getVL();
#if BX_SUPPORT_X86_64
if (i->as64L()) {
for (unsigned n=0; n < (4*len); n++) {
if (mask & (1<<n)) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 4*n)))
exception(int_number(i->seg()), 0);
}
}
}
#endif
#if BX_SUPPORT_ALIGNMENT_CHECK
unsigned save_alignment_check_mask = BX_CPU_THIS_PTR alignment_check_mask;
BX_CPU_THIS_PTR alignment_check_mask = 0;
#endif
// see you can successfully write all the elements first
for (int n=4*len-1; n >= 0; n--) {
if (mask & (1<<n))
read_RMW_virtual_dword(i->seg(), eaddr + 4*n);
}
for (unsigned n=0; n < (4*len); n++) {
if (mask & (1<<n))
write_virtual_dword(i->seg(), eaddr + 4*n, op->vmm32u(n));
}
#if BX_SUPPORT_ALIGNMENT_CHECK
BX_CPU_THIS_PTR alignment_check_mask = save_alignment_check_mask;
#endif
}
void BX_CPU_C::avx_masked_store64(bxInstruction_c *i, bx_address eaddr, const BxPackedAvxRegister *op, unsigned mask)
{
unsigned len = i->getVL();
#if BX_SUPPORT_X86_64
if (i->as64L()) {
for (unsigned n=0; n < (2*len); n++) {
if (mask & (1<<n)) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 8*n)))
exception(int_number(i->seg()), 0);
}
}
}
#endif
#if BX_SUPPORT_ALIGNMENT_CHECK
unsigned save_alignment_check_mask = BX_CPU_THIS_PTR alignment_check_mask;
BX_CPU_THIS_PTR alignment_check_mask = 0;
#endif
// see you can successfully write all the elements first
for (int n=2*len-1; n >= 0; n--) {
if (mask & (1<<n))
read_RMW_virtual_qword(i->seg(), eaddr + 8*n);
}
for (unsigned n=0; n < (2*len); n++) {
if (mask & (1<<n))
write_virtual_qword(i->seg(), eaddr + 8*n, op->vmm64u(n));
}
#if BX_SUPPORT_ALIGNMENT_CHECK
BX_CPU_THIS_PTR alignment_check_mask = save_alignment_check_mask;
#endif
}
#endif // BX_SUPPORT_AVX
#if BX_SUPPORT_EVEX
#include "simd_int.h"
void BX_CPU_C::avx512_write_regd_masked(bxInstruction_c *i, const BxPackedAvxRegister *op, unsigned mask)
{
unsigned len = i->getVL();
if (i->isZeroMasking()) {
for (unsigned n=0; n < len; n++, mask >>= 4)
xmm_zero_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op->vmm128(n), mask);
}
else {
for (unsigned n=0; n < len; n++, mask >>= 4)
xmm_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op->vmm128(n), mask);
}
}
void BX_CPU_C::avx512_write_regq_masked(bxInstruction_c *i, const BxPackedAvxRegister *op, unsigned mask)
{
unsigned len = i->getVL();
if (i->isZeroMasking()) {
for (unsigned n=0; n < len; n++, mask >>= 4)
xmm_zero_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op->vmm128(n), mask);
}
else {
for (unsigned n=0; n < len; n++, mask >>= 4)
xmm_blendps(&BX_READ_AVX_REG_LANE(i->dst(), n), &op->vmm128(n), mask);
}
BX_CLEAR_AVX_REGZ(i->dst(), len);
}
//////////////////////////
// masked register move //
//////////////////////////
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_MASK_VpsWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
avx512_write_regd_masked(i, &op, BX_READ_16BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPD_MASK_VpdWpdR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
avx512_write_regq_masked(i, &op, BX_READ_8BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
/////////////////////////////////
// masked load/store - aligned //
/////////////////////////////////
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_MASK_VpsWpsM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
bx_address laddr = get_laddr(i->seg(), eaddr);
unsigned len_in_bytes = 16 * i->getVL();
if (laddr & (len_in_bytes-1)) {
BX_ERROR(("AVX masked read len=%d: #GP misaligned access", len_in_bytes));
exception(BX_GP_EXCEPTION, 0);
}
BX_PANIC(("%s: not implemented yet !", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPD_MASK_VpdWpdM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
bx_address laddr = get_laddr(i->seg(), eaddr);
unsigned len_in_bytes = 16 * i->getVL();
if (laddr & (len_in_bytes-1)) {
BX_ERROR(("AVX masked read len=%d: #GP misaligned access", len_in_bytes));
exception(BX_GP_EXCEPTION, 0);
}
BX_PANIC(("%s: not implemented yet !", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_MASK_WpsVpsM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
bx_address laddr = get_laddr(i->seg(), eaddr);
unsigned len_in_bytes = 16 * i->getVL();
if (laddr & (len_in_bytes-1)) {
BX_ERROR(("AVX masked write len=%d: #GP misaligned access", len_in_bytes));
exception(BX_GP_EXCEPTION, 0);
}
avx_masked_store32(i, eaddr, &BX_READ_AVX_REG(i->src()), BX_READ_16BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPD_MASK_WpdVpdM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
bx_address laddr = get_laddr(i->seg(), eaddr);
unsigned len_in_bytes = 16 * i->getVL();
if (laddr & (len_in_bytes-1)) {
BX_ERROR(("AVX masked write len=%d: #GP misaligned access", len_in_bytes));
exception(BX_GP_EXCEPTION, 0);
}
avx_masked_store64(i, eaddr, &BX_READ_AVX_REG(i->src()), BX_READ_8BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
///////////////////////
// masked load/store //
///////////////////////
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPS_MASK_VpsWpsM(bxInstruction_c *i)
{
BX_PANIC(("%s: not implemented yet !", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPD_MASK_VpdWpdM(bxInstruction_c *i)
{
BX_PANIC(("%s: not implemented yet !", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPS_MASK_WpsVpsM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
avx_masked_store32(i, eaddr, &BX_READ_AVX_REG(i->src()), BX_READ_16BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPD_MASK_WpdVpdM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
avx_masked_store64(i, eaddr, &BX_READ_AVX_REG(i->src()), BX_READ_8BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
#endif

16
bochs/cpu/cpu.h
View File

@ -3238,11 +3238,17 @@ public: // for now...
BX_SMF BX_INSF_TYPE VMOVAPS_MASK_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVAPS_MASK_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVAPS_MASK_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVAPD_MASK_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVAPD_MASK_VpdWpdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVAPD_MASK_WpdVpdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVUPS_MASK_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVUPS_MASK_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVUPS_MASK_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVUPD_MASK_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVUPD_MASK_VpdWpdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVUPD_MASK_WpdVpdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDPD_MASK_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDPS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSD_MASK_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -4306,10 +4312,10 @@ public: // for now...
#endif
#if BX_SUPPORT_AVX
BX_SMF void avx_masked_load32(bxInstruction_c *i, BxPackedAvxRegister *dst, unsigned mask);
BX_SMF void avx_masked_load64(bxInstruction_c *i, BxPackedAvxRegister *dst, unsigned mask);
BX_SMF void avx_masked_store32(bxInstruction_c *i, const BxPackedAvxRegister *op, unsigned mask);
BX_SMF void avx_masked_store64(bxInstruction_c *i, const BxPackedAvxRegister *op, unsigned mask);
BX_SMF void avx_masked_load32(bxInstruction_c *i, bx_address eaddr, BxPackedAvxRegister *dst, unsigned mask);
BX_SMF void avx_masked_load64(bxInstruction_c *i, bx_address eaddr, BxPackedAvxRegister *dst, unsigned mask);
BX_SMF void avx_masked_store32(bxInstruction_c *i, bx_address eaddr, const BxPackedAvxRegister *op, unsigned mask);
BX_SMF void avx_masked_store64(bxInstruction_c *i, bx_address eaddr, const BxPackedAvxRegister *op, unsigned mask);
#endif
#if BX_SUPPORT_EVEX

7
bochs/cpu/fetchdecode.cc
View File

@ -1449,9 +1449,14 @@ fetch_b1:
goto decode_done;
unsigned evex_b = (evex >> 20) & 0x1;
i->setEvexb(evex_b);
unsigned evex_vl_rc = (evex >> 21) & 0x3;
i->setRC(evex_vl_rc);
i->setVL(evex_vl_rc);
if (evex_vl_rc == 3)
i->setVL(BX_VL512);
else
i->setVL(BX_VL128+evex_vl_rc);
unsigned evex_z = (evex >> 23) & 0x1;
i->setZeroMasking(evex_z);

7
bochs/cpu/fetchdecode64.cc
View File

@ -1927,9 +1927,14 @@ fetch_b1:
i->setOpmask(opmask);
unsigned evex_b = (evex >> 20) & 0x1;
i->setEvexb(evex_b);
unsigned evex_vl_rc = (evex >> 21) & 0x3;
i->setRC(evex_vl_rc);
i->setVL(evex_vl_rc);
if (evex_vl_rc == 3)
i->setVL(BX_VL512);
else
i->setVL(BX_VL128+evex_vl_rc);
unsigned evex_z = (evex >> 23) & 0x1;
i->setZeroMasking(evex_z);

54
bochs/cpu/fetchdecode_evex.h
View File

@ -52,8 +52,8 @@ static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f28[2] = {
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f28_Mask[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VMOVAPS_VpsWps_KMask },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVAPD_VpdWpd_KMask }
/* -- */ { BxVexW0, BX_IA_V512_VMOVAPS_VpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVAPD_VpdWpd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f29[2] = {
@ -62,8 +62,18 @@ static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f29[2] = {
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f29_Mask[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VMOVAPS_WpsVps_KMask },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVAPD_WpdVpd_KMask }
/* -- */ { BxVexW0, BX_IA_V512_VMOVAPS_WpsVps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVAPD_WpdVpd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f2e[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VUCOMISS_VssWss },
/* 66 */ { BxVexW1, BX_IA_V512_VUCOMISD_VsdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f2f[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VCOMISS_VssWss },
/* 66 */ { BxVexW1, BX_IA_V512_VCOMISD_VsdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f58[4] = {
@ -150,6 +160,30 @@ static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f5f_Mask[4] = {
/* F2 */ { BxVexW1, BX_IA_V512_VMAXSD_VsdHpdWsd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f6f[3] = {
/* 66 */ { BxAliasVexW, BX_IA_V512_VMOVDQA32_VdqWdq },
/* F3 */ { BxAliasVexW, BX_IA_V512_VMOVDQU32_VdqWdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f6f_Mask[3] = {
/* 66 */ { BxAliasVexW, BX_IA_V512_VMOVDQA32_VdqWdq_Kmask },
/* F3 */ { BxAliasVexW, BX_IA_V512_VMOVDQU32_VdqWdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f7f[3] = {
/* 66 */ { BxAliasVexW, BX_IA_V512_VMOVDQA32_WdqVdq },
/* F3 */ { BxAliasVexW, BX_IA_V512_VMOVDQU32_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f7f_Mask[3] = {
/* 66 */ { BxAliasVexW, BX_IA_V512_VMOVDQA32_WdqVdq_Kmask },
/* F3 */ { BxAliasVexW, BX_IA_V512_VMOVDQU32_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
/* ************************************************************************ */
static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
@ -246,9 +280,9 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 2C */ { 0, BX_IA_ERROR },
/* 2D k0 */ { 0, BX_IA_ERROR },
/* 2D */ { 0, BX_IA_ERROR },
/* 2E k0 */ { 0, BX_IA_ERROR },
/* 2E k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2e },
/* 2E */ { 0, BX_IA_ERROR },
/* 2F k0 */ { 0, BX_IA_ERROR },
/* 2F k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2f },
/* 2F */ { 0, BX_IA_ERROR },
/* 30 k0 */ { 0, BX_IA_ERROR },
/* 30 */ { 0, BX_IA_ERROR },
@ -376,8 +410,8 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 6D */ { 0, BX_IA_ERROR },
/* 6E k0 */ { 0, BX_IA_ERROR },
/* 6E */ { 0, BX_IA_ERROR },
/* 6F k0 */ { 0, BX_IA_ERROR },
/* 6F */ { 0, BX_IA_ERROR },
/* 6F k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f6f },
/* 6F */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f6f_Mask },
/* 70 k0 */ { 0, BX_IA_ERROR },
/* 70 */ { 0, BX_IA_ERROR },
/* 71 k0 */ { 0, BX_IA_ERROR },
@ -408,8 +442,8 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 7D */ { 0, BX_IA_ERROR },
/* 7E k0 */ { 0, BX_IA_ERROR },
/* 7E */ { 0, BX_IA_ERROR },
/* 7F k0 */ { 0, BX_IA_ERROR },
/* 7F */ { 0, BX_IA_ERROR },
/* 7F k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f7f },
/* 7F */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f7f_Mask },
/* 80 k0 */ { 0, BX_IA_ERROR },
/* 80 */ { 0, BX_IA_ERROR },
/* 81 k0 */ { 0, BX_IA_ERROR },

43
bochs/cpu/ia_opcodes.h
View File

@ -2520,15 +2520,30 @@ bx_define_opcode(BX_IA_V512_VUNPCKHPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST
bx_define_opcode(BX_IA_V512_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPMULLD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMULLD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_AVX512, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VssWssR, BX_ISA_AVX512, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VUCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VsdWsdR, BX_ISA_AVX512, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPS_VpsWps, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPS_VpsWps_KMask, &BX_CPU_C::VMOVAPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPS_VpsWps_Kmask, &BX_CPU_C::VMOVAPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPS_WpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPS_WpsVps_KMask, &BX_CPU_C::VMOVAPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Wps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPS_WpsVps_Kmask, &BX_CPU_C::VMOVAPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Wps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPD_VpdWpd_KMask, &BX_CPU_C::VMOVAPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPD_VpdWpd_Kmask, &BX_CPU_C::VMOVAPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPD_WpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPD_WpdVpd_KMask, &BX_CPU_C::VMOVAPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVAPD_WpdVpd_Kmask, &BX_CPU_C::VMOVAPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVUPS_VpsWps_Kmask, &BX_CPU_C::VMOVUPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVUPS_WpsVps, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVUPS_WpsVps_Kmask, &BX_CPU_C::VMOVUPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Wps, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVUPD_VpdWpd, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVUPD_VpdWpd_Kmask, &BX_CPU_C::VMOVUPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVUPD_WpdVpd, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVUPD_WpdVpd_Kmask, &BX_CPU_C::VMOVUPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
// VexW alias
bx_define_opcode(BX_IA_V512_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
@ -2581,6 +2596,26 @@ bx_define_opcode(BX_IA_V512_VPMINUQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ
bx_define_opcode(BX_IA_V512_VPMINUD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMINUD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPMINUQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMINUQ_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQU32_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQU64_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQU32_VdqWdq_Kmask, &BX_CPU_C::VMOVUPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQU64_VdqWdq_Kmask, &BX_CPU_C::VMOVUPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQU32_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQU64_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQU32_WdqVdq_Kmask, &BX_CPU_C::VMOVUPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQU64_WdqVdq_Kmask, &BX_CPU_C::VMOVUPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQA32_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQA64_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQA32_VdqWdq_Kmask, &BX_CPU_C::VMOVAPS_MASK_VpsWpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQA64_VdqWdq_Kmask, &BX_CPU_C::VMOVAPD_MASK_VpdWpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQA32_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQA64_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQA32_WdqVdq_Kmask, &BX_CPU_C::VMOVAPS_MASK_WpsVpsM, &BX_CPU_C::VMOVAPS_MASK_VpsWpsR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVDQA64_WdqVdq_Kmask, &BX_CPU_C::VMOVAPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Vps, OP_Wps, OP_Hps, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD132PD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VFMADDPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Vpd, OP_Wpd, OP_Hpd, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VFMADD213PS_VpsHpsWps, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VFMADDPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Vps, OP_Wps, BX_PREPARE_EVEX)

4
bochs/cpu/sse_pfp.cc
View File

@ -836,6 +836,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISS_VssWssR(bxInstruction_c *i
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
int rc = float32_compare_quiet(op1, op2, status);
check_exceptionsSSE(status.float_exception_flags);
BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
@ -856,6 +857,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsdR(bxInstruction_c *i
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
int rc = float64_compare_quiet(op1, op2, status);
check_exceptionsSSE(status.float_exception_flags);
BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
@ -876,6 +878,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISS_VssWssR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
int rc = float32_compare(op1, op2, status);
check_exceptionsSSE(status.float_exception_flags);
BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
@ -896,6 +899,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISD_VsdWsdR(bxInstruction_c *i)
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
int rc = float64_compare(op1, op2, status);
check_exceptionsSSE(status.float_exception_flags);
BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);

6
bochs/cpu/xmm.h
View File

@ -61,9 +61,9 @@ typedef union bx_xmm_reg_t {
enum bx_avx_vector_length {
BX_NO_VL,
BX_VL128,
BX_VL256,
BX_VL512
BX_VL128 = 1,
BX_VL256 = 2,
BX_VL512 = 4
};
#if BX_SUPPORT_EVEX