fixes for disasm
This commit is contained in:
Stanislav Shwartsman
parent
579dfc40df
commit
940c2a1c8e
@ -105,4 +105,30 @@ AVX512_2OP_QWORD_EL(VPMINUQ_MASK_VdqHdqWdqR, xmm_pminuq)
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AVX512_2OP_DWORD_EL(VUNPCKLPD_MASK_VpdHpdWpdR, xmm_unpcklpd)
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AVX512_2OP_DWORD_EL(VUNPCKHPD_MASK_VpdHpdWpdR, xmm_unpckhpd)
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/*
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VALIGND_MASK_VdqHdqWdqIbR(bxInstruction_c *i)
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{
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BX_PANIC(("%s: not implemented yet !", i->get_bx_opcode_name()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VALIGNQ_MASK_VdqHdqWdqIbR(bxInstruction_c *i)
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{
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BX_PANIC(("%s: not implemented yet !", i->get_bx_opcode_name()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDMPD_MASK_VpdHpdWpdR(bxInstruction_c *i)
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{
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BX_PANIC(("%s: not implemented yet !", i->get_bx_opcode_name()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDMPS_MASK_VpsHpsWpsR(bxInstruction_c *i)
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{
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BX_PANIC(("%s: not implemented yet !", i->get_bx_opcode_name()));
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BX_NEXT_INSTR(i);
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}
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*/
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#endif
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@ -658,4 +658,30 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSD_MASK_VsdHpdWsdR(bxInstructi
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BX_NEXT_INSTR(i);
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}
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/*
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPD_MASK_VpdHpdWpdIbR(bxInstruction_c *i)
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{
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BX_PANIC(("%s: not implemented yet !", i->get_bx_opcode_name()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPS_MASK_VpsHpsWpsIbR(bxInstruction_c *i)
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{
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BX_PANIC(("%s: not implemented yet !", i->get_bx_opcode_name()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSD_MASK_VsdHpdWsdIbR(bxInstruction_c *i)
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{
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BX_PANIC(("%s: not implemented yet !", i->get_bx_opcode_name()));
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSS_MASK_VssHpdWssIbR(bxInstruction_c *i)
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{
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BX_PANIC(("%s: not implemented yet !", i->get_bx_opcode_name()));
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BX_NEXT_INSTR(i);
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}
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*/
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#endif
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@ -1578,13 +1578,13 @@ public: // for now...
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BX_SMF BX_INSF_TYPE REP_CMPSD_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_STOSB_YbAL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_LODSB_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_SCASB_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_SCASB_ALYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_STOSW_YwAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_LODSW_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_SCASW_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_SCASW_AXYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_STOSD_YdEAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_LODSD_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_SCASD_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_SCASD_EAXYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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// qualified by address size
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BX_SMF void CMPSB16_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1594,12 +1594,12 @@ public: // for now...
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BX_SMF void CMPSW32_XwYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CMPSD32_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASB16_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASW16_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASD16_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASB32_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASW32_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASD32_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASB16_ALYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASW16_AXYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASD16_EAXYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASB32_ALYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASW32_AXYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASD32_EAXYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LODSB16_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LODSW16_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2296,8 +2296,8 @@ public: // for now...
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BX_SMF BX_INSF_TYPE PCMPEQW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE PCMPEQD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE EMMS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE MOVD_EdPdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE MOVD_EdPdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE MOVD_EdPqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE MOVD_EdPqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE MOVQ_QqPqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE PSRLW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE PSRLD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -3451,15 +3451,15 @@ public: // for now...
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BX_SMF BX_INSF_TYPE REP_CMPSQ_XqYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_STOSQ_YqRAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_LODSQ_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_SCASQ_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE REP_SCASQ_RAXYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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// qualified by address size
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BX_SMF void CMPSB64_XbYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CMPSW64_XwYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CMPSD64_XdYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASB64_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASW64_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASD64_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASB64_ALYb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASW64_AXYw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASD64_EAXYd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LODSB64_ALXb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LODSW64_AXXw(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LODSD64_EAXXd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -3472,8 +3472,8 @@ public: // for now...
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BX_SMF void CMPSQ32_XqYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CMPSQ64_XqYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASQ32_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASQ64_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASQ32_RAXYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SCASQ64_RAXYq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LODSQ32_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LODSQ64_RAXXq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void STOSQ32_YqRAX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -5165,14 +5165,15 @@ enum {
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#define BxPrefixSSEF2 0x0030 // Group encoding: 0011, SSE_PREFIX_F2 only
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#define BxPrefixSSE 0x0040 // Group encoding: 0100
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#define BxPrefixSSE2 0x0050 // Group encoding: 0101, do not allow SSE_PREFIX_F2 or SSE_PREFIX_F3
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#define BxPrefixSSEF2F3 0x0060 // Group encoding: 0110, ignore SSE_PREFIX_66
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#define BxGroupN 0x0070 // Group encoding: 0111
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#define BxSplitGroupN 0x0080 // Group encoding: 1000
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#define BxFPEscape 0x0090 // Group encoding: 1001
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#define BxOSizeGrp 0x00A0 // Group encoding: 1010
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#define BxSplitVexW 0x00B0 // Group encoding: 1011
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#define BxSplitVexW64 0x00C0 // Group encoding: 1100 - VexW ignored in 32-bit mode
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#define BxSplitMod11B 0x00D0 // Group encoding: 1101
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#define BxPrefixSSE4 0x0060 // Group encoding: 0110
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#define BxPrefixSSEF2F3 0x0070 // Group encoding: 0111, ignore SSE_PREFIX_66
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#define BxGroupN 0x0080 // Group encoding: 1000
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#define BxSplitGroupN 0x0090 // Group encoding: 1001
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#define BxFPEscape 0x00A0 // Group encoding: 1010
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#define BxOSizeGrp 0x00B0 // Group encoding: 1011
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#define BxSplitVexW 0x00C0 // Group encoding: 1100
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#define BxSplitVexW64 0x00D0 // Group encoding: 1101 - VexW ignored in 32-bit mode
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#define BxSplitMod11B 0x00E0 // Group encoding: 1110
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// The BxImmediate2 mask specifies kind of second immediate data
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// required by instruction.
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@ -90,11 +90,27 @@ static const char *rounding_mode[4] = {
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#define BX_JUMP_TARGET_NOT_REQ ((bx_address)(-1))
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char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regname[])
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char *resolve_sib_scale(char *disbufptr, const bxInstruction_c *i, const char *regname[], unsigned src_index)
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{
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unsigned sib_base = i->sibBase(), sib_index = i->sibIndex(), sib_scale = i->sibScale();
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unsigned sib_index = i->sibIndex(), sib_scale = i->sibScale();
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if (sib_index == 4) sib_index = BX_NIL_REGISTER;
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if (src_index == BX_SRC_VSIB)
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disbufptr = dis_sprintf(disbufptr, "%cmm%d", 'x' + i->getVL() - 1, sib_index);
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else
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disbufptr = dis_sprintf(disbufptr, "%s", regname[sib_index]);
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if (sib_scale)
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disbufptr = dis_sprintf(disbufptr, "*%d", 1 << sib_scale);
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return disbufptr;
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}
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char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regname[], unsigned src_index)
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{
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unsigned sib_base = i->sibBase(), sib_index = i->sibIndex();
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if (sib_index == 4 && src_index != BX_SRC_VSIB)
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sib_index = BX_NIL_REGISTER;
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if (sib_base == BX_NIL_REGISTER)
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{
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@ -115,18 +131,15 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regn
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return disbufptr;
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}
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disbufptr = dis_sprintf(disbufptr, "[%s", regname[i->sibIndex()]);
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if (sib_scale)
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disbufptr = dis_sprintf(disbufptr, "*%d", 1 << i->sibScale());
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disbufptr = dis_putc(disbufptr, '[');
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disbufptr = resolve_sib_scale(disbufptr, i, regname, src_index);
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}
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else {
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disbufptr = dis_sprintf(disbufptr, "[%s", regname[i->sibBase()]);
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if (sib_index != BX_NIL_REGISTER)
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{
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disbufptr = dis_sprintf(disbufptr, "+%s", regname[i->sibIndex()]);
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if (sib_scale)
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disbufptr = dis_sprintf(disbufptr, "*%d", 1 << i->sibScale());
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if (sib_index != BX_NIL_REGISTER) {
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disbufptr = dis_putc(disbufptr, '+');
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disbufptr = resolve_sib_scale(disbufptr, i, regname, src_index);
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}
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}
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@ -145,18 +158,18 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regn
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return disbufptr;
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}
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char *resolve_memref(char *disbufptr, const bxInstruction_c *i)
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char *resolve_memref(char *disbufptr, const bxInstruction_c *i, unsigned src_index)
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{
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// seg:[base + index*scale + disp]
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disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
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if (i->as64L()) {
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disbufptr = resolve_memref(disbufptr, i, intel_general_64bit_regname);
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disbufptr = resolve_memref(disbufptr, i, intel_general_64bit_regname, src_index);
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}
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else if (i->as32L()) {
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disbufptr = resolve_memref(disbufptr, i, intel_general_32bit_regname);
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disbufptr = resolve_memref(disbufptr, i, intel_general_32bit_regname, src_index);
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}
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else {
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disbufptr = resolve_memref(disbufptr, i, intel_general_16bit_regname);
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disbufptr = resolve_memref(disbufptr, i, intel_general_16bit_regname, src_index);
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}
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return disbufptr;
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}
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@ -215,12 +228,13 @@ char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_a
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for (n = 0; n <= 3; n++) {
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unsigned src = (unsigned) BxOpcodesTable[ia_opcode].src[n];
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unsigned src_type = src >> 3;
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unsigned src_index = src & 0x7;
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if (! src_type && src != BX_SRC_RM) continue;
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if (srcs_used++ > 0)
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disbufptr = dis_sprintf(disbufptr, ", ");
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if (! i->modC0() && ((src & 0x7) == BX_SRC_RM)) {
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disbufptr = resolve_memref(disbufptr, i);
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if (! i->modC0() && (src_index == BX_SRC_RM || src_index == BX_SRC_VSIB)) {
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disbufptr = resolve_memref(disbufptr, i, src_index);
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}
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else {
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unsigned srcreg = i->getSrcReg(n);
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@ -351,8 +351,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
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/* AB /w */ { 0, BX_IA_REP_STOSW_YwAX },
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/* AC /w */ { 0, BX_IA_REP_LODSB_ALXb },
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/* AD /w */ { 0, BX_IA_REP_LODSW_AXXw },
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/* AE /w */ { 0, BX_IA_REP_SCASB_ALXb },
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/* AF /w */ { 0, BX_IA_REP_SCASW_AXXw },
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/* AE /w */ { 0, BX_IA_REP_SCASB_ALYb },
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/* AF /w */ { 0, BX_IA_REP_SCASW_AXYw },
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/* B0 /w */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
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/* B1 /w */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
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/* B2 /w */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
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@ -590,7 +590,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
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/* 0F 7B /w */ { 0, BX_IA_ERROR },
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/* 0F 7C /w */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
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/* 0F 7D /w */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
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/* 0F 7E /w */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
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/* 0F 7E /w */ { BxPrefixSSE, BX_IA_MOVD_EdPq, BxOpcodeGroupSSE_0f7e },
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/* 0F 7F /w */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
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/* 0F 80 /w */ { BxImmediate_BrOff16, BX_IA_JO_Jw },
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/* 0F 81 /w */ { BxImmediate_BrOff16, BX_IA_JNO_Jw },
|
||||
@ -896,8 +896,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
|
||||
/* AB /d */ { 0, BX_IA_REP_STOSD_YdEAX },
|
||||
/* AC /d */ { 0, BX_IA_REP_LODSB_ALXb },
|
||||
/* AD /d */ { 0, BX_IA_REP_LODSD_EAXXd },
|
||||
/* AE /d */ { 0, BX_IA_REP_SCASB_ALXb },
|
||||
/* AF /d */ { 0, BX_IA_REP_SCASD_EAXXd },
|
||||
/* AE /d */ { 0, BX_IA_REP_SCASB_ALYb },
|
||||
/* AF /d */ { 0, BX_IA_REP_SCASD_EAXYd },
|
||||
/* B0 /d */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
/* B1 /d */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
/* B2 /d */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
@ -1135,7 +1135,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
|
||||
/* 0F 7B /d */ { 0, BX_IA_ERROR },
|
||||
/* 0F 7C /d */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /d */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /d */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7E /d */ { BxPrefixSSE, BX_IA_MOVD_EdPq, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7F /d */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
|
||||
/* 0F 80 /d */ { BxImmediate_BrOff32, BX_IA_JO_Jd },
|
||||
/* 0F 81 /d */ { BxImmediate_BrOff32, BX_IA_JNO_Jd },
|
||||
@ -1635,6 +1635,7 @@ fetch_b1:
|
||||
i->ResolveModrm = &BX_CPU_C::BxResolve16BaseIndex;
|
||||
i->setSibBase(Resolve16BaseReg[rm]);
|
||||
i->setSibIndex(Resolve16IndexReg[rm]);
|
||||
i->setSibScale(0);
|
||||
if (mod == 0x00) { // mod == 00b
|
||||
seg = sreg_mod00_rm16[rm];
|
||||
if (rm == 6) {
|
||||
@ -1716,15 +1717,20 @@ modrm_done:
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[os_32]);
|
||||
break;
|
||||
case BxPrefixSSE:
|
||||
/* For SSE opcodes look into another table
|
||||
/* For SSE opcodes look into another 3-entry table
|
||||
with the opcode prefixes (NONE, 0x66, 0xF3, 0xF2) */
|
||||
if (sse_prefix) {
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix-1]);
|
||||
break;
|
||||
}
|
||||
continue;
|
||||
case BxPrefixSSE4:
|
||||
/* For SSE opcodes look into another 4-entry table
|
||||
with the opcode prefixes (NONE, 0x66, 0xF3, 0xF2) */
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix]);
|
||||
break;
|
||||
case BxPrefixSSE2:
|
||||
/* For SSE opcodes look into another table
|
||||
/* For SSE opcodes look into another 2-entry table
|
||||
with the opcode prefixes (NONE, 0x66), 0xF2 and 0xF3 not allowed */
|
||||
if (sse_prefix > SSE_PREFIX_66) goto decode_done;
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix]);
|
||||
@ -1937,6 +1943,11 @@ modrm_done:
|
||||
case BX_SRC_VIB:
|
||||
i->setSrcReg(n, (i->Ib() >> 4) & 7);
|
||||
break;
|
||||
case BX_SRC_VSIB:
|
||||
if (! i->as32L() || i->sibIndex() == BX_NIL_REGISTER) {
|
||||
ia_opcode = BX_IA_ERROR;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
BX_PANIC(("fetchdecode32: unknown definition %d for src %d", src, n));
|
||||
@ -1948,9 +1959,6 @@ modrm_done:
|
||||
seg = seg_override;
|
||||
i->setSeg(seg);
|
||||
|
||||
i->setILen(remainingInPage - remain);
|
||||
i->setIaOpcode(ia_opcode);
|
||||
|
||||
#if BX_SUPPORT_AVX
|
||||
if (had_vex_xop) {
|
||||
if (! use_vvv && vvv != 0) {
|
||||
@ -1976,6 +1984,9 @@ modrm_done:
|
||||
|
||||
decode_done:
|
||||
|
||||
i->setILen(remainingInPage - remain);
|
||||
i->setIaOpcode(ia_opcode);
|
||||
|
||||
if (mod_mem) {
|
||||
i->execute1 = BxOpcodesTable[ia_opcode].execute1;
|
||||
i->handlers.execute2 = BxOpcodesTable[ia_opcode].execute2;
|
||||
|
||||
@ -79,7 +79,8 @@ enum {
|
||||
BX_SRC_RM = 3,
|
||||
BX_SRC_MEM_NO_VVV = 4,
|
||||
BX_SRC_VVV = 5,
|
||||
BX_SRC_VIB = 6
|
||||
BX_SRC_VIB = 6,
|
||||
BX_SRC_VSIB = 7 // gather/scatter vector index
|
||||
};
|
||||
|
||||
enum {
|
||||
@ -96,8 +97,7 @@ enum {
|
||||
BX_KMASK_REG = 0xA,
|
||||
BX_SEGREG = 0xB,
|
||||
BX_CREG = 0xC,
|
||||
BX_DREG = 0xD,
|
||||
BX_VSIB = 0xE // gather/scatter vector index
|
||||
BX_DREG = 0xD
|
||||
};
|
||||
|
||||
enum {
|
||||
@ -165,7 +165,6 @@ const Bit8u OP_Mt = BX_FORM_SRC(BX_FPU_REG, BX_SRC_RM);
|
||||
const Bit8u OP_Mdq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
|
||||
const Bit8u OP_Pq = BX_FORM_SRC(BX_MMX_REG, BX_SRC_NNN);
|
||||
const Bit8u OP_Pd = BX_FORM_SRC(BX_MMX_REG, BX_SRC_NNN);
|
||||
const Bit8u OP_Qq = BX_FORM_SRC(BX_MMX_REG, BX_SRC_RM);
|
||||
const Bit8u OP_Qd = BX_FORM_SRC(BX_MMX_REG, BX_SRC_RM);
|
||||
|
||||
@ -177,11 +176,11 @@ const Bit8u OP_Vsd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_NNN);
|
||||
const Bit8u OP_Vq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_NNN);
|
||||
const Bit8u OP_Vd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_NNN);
|
||||
|
||||
const Bit8u OP_Wdq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
const Bit8u OP_Wq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
const Bit8u OP_Wd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
const Bit8u OP_Ww = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
const Bit8u OP_Wb = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
const Bit8u OP_Wdq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
const Bit8u OP_Wps = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
const Bit8u OP_Wpd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
const Bit8u OP_Wss = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
|
||||
@ -198,7 +197,7 @@ const Bit8u OP_Bq = BX_FORM_SRC(BX_GPR64, BX_SRC_VVV);
|
||||
|
||||
const Bit8u OP_VIb = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VIB);
|
||||
|
||||
const Bit8u OP_VSib = BX_SRC_RM;
|
||||
const Bit8u OP_VSib = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VSIB);
|
||||
|
||||
const Bit8u OP_Cd = BX_FORM_SRC(BX_CREG, BX_SRC_NNN);
|
||||
const Bit8u OP_Cq = BX_FORM_SRC(BX_CREG, BX_SRC_NNN);
|
||||
|
||||
@ -313,8 +313,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* AB /w */ { 0, BX_IA_REP_STOSW_YwAX },
|
||||
/* AC /w */ { 0, BX_IA_REP_LODSB_ALXb },
|
||||
/* AD /w */ { 0, BX_IA_REP_LODSW_AXXw },
|
||||
/* AE /w */ { 0, BX_IA_REP_SCASB_ALXb },
|
||||
/* AF /w */ { 0, BX_IA_REP_SCASW_AXXw },
|
||||
/* AE /w */ { 0, BX_IA_REP_SCASB_ALYb },
|
||||
/* AF /w */ { 0, BX_IA_REP_SCASW_AXYw },
|
||||
/* B0 /w */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
/* B1 /w */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
/* B2 /w */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
@ -522,7 +522,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 0F 7B /w */ { 0, BX_IA_ERROR },
|
||||
/* 0F 7C /w */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /w */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /w */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7E /w */ { BxPrefixSSE, BX_IA_MOVD_EdPq, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7F /w */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
|
||||
/* 0F 80 /w */ { BxImmediate_BrOff32, BX_IA_JO_Jq },
|
||||
/* 0F 81 /w */ { BxImmediate_BrOff32, BX_IA_JNO_Jq },
|
||||
@ -828,8 +828,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* AB /d */ { 0, BX_IA_REP_STOSD_YdEAX },
|
||||
/* AC /d */ { 0, BX_IA_REP_LODSB_ALXb },
|
||||
/* AD /d */ { 0, BX_IA_REP_LODSD_EAXXd },
|
||||
/* AE /d */ { 0, BX_IA_REP_SCASB_ALXb },
|
||||
/* AF /d */ { 0, BX_IA_REP_SCASD_EAXXd },
|
||||
/* AE /d */ { 0, BX_IA_REP_SCASB_ALYb },
|
||||
/* AF /d */ { 0, BX_IA_REP_SCASD_EAXYd },
|
||||
/* B0 /d */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
/* B1 /d */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
/* B2 /d */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
@ -1037,7 +1037,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* 0F 7B /d */ { 0, BX_IA_ERROR },
|
||||
/* 0F 7C /d */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /d */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /d */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7E /d */ { BxPrefixSSE, BX_IA_MOVD_EdPq, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7F /d */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7f },
|
||||
/* 0F 80 /d */ { BxImmediate_BrOff32, BX_IA_JO_Jq },
|
||||
/* 0F 81 /d */ { BxImmediate_BrOff32, BX_IA_JNO_Jq },
|
||||
@ -1343,8 +1343,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
|
||||
/* AB /q */ { 0, BX_IA_REP_STOSQ_YqRAX },
|
||||
/* AC /q */ { 0, BX_IA_REP_LODSB_ALXb },
|
||||
/* AD /q */ { 0, BX_IA_REP_LODSQ_RAXXq },
|
||||
/* AE /q */ { 0, BX_IA_REP_SCASB_ALXb },
|
||||
/* AF /q */ { 0, BX_IA_REP_SCASQ_RAXXq },
|
||||
/* AE /q */ { 0, BX_IA_REP_SCASB_ALYb },
|
||||
/* AF /q */ { 0, BX_IA_REP_SCASQ_RAXYq },
|
||||
/* B0 /q */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
/* B1 /q */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
/* B2 /q */ { BxImmediate_Ib, BX_IA_MOV_EbIb },
|
||||
@ -1709,7 +1709,7 @@ BX_CPU_C::fetchDecode64(const Bit8u *iptr, Bit32u fetchModeMask, bxInstruction_c
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_EVEX
|
||||
bx_bool evex_v = 0;
|
||||
unsigned evex_v = 0;
|
||||
#endif
|
||||
|
||||
i->ResolveModrm = 0;
|
||||
@ -2156,15 +2156,20 @@ modrm_done:
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[offset >> 9]);
|
||||
break;
|
||||
case BxPrefixSSE:
|
||||
/* For SSE opcodes look into another table
|
||||
/* For SSE opcodes look into another 3-entry table
|
||||
with the opcode prefixes (NONE, 0x66, 0xF3, 0xF2) */
|
||||
if (sse_prefix) {
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix-1]);
|
||||
break;
|
||||
}
|
||||
continue;
|
||||
case BxPrefixSSE4:
|
||||
/* For SSE opcodes look into another 4-entry table
|
||||
with the opcode prefixes (NONE, 0x66, 0xF3, 0xF2) */
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix]);
|
||||
break;
|
||||
case BxPrefixSSE2:
|
||||
/* For SSE opcodes look into another table
|
||||
/* For SSE opcodes look into another 2-entry table
|
||||
with the opcode prefixes (NONE, 0x66), 0xF2 and 0xF3 not allowed */
|
||||
if (sse_prefix > SSE_PREFIX_66) goto decode_done;
|
||||
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix]);
|
||||
@ -2203,9 +2208,10 @@ modrm_done:
|
||||
// the if() above after fetching the 2nd byte, so this path is
|
||||
// taken in all cases if a modrm byte is NOT required.
|
||||
|
||||
if (b1 == 0x90 && sse_prefix == SSE_PREFIX_F3) {
|
||||
// attention: need to handle VEX separately, XOP never reach here
|
||||
ia_opcode = BX_IA_PAUSE;
|
||||
if (b1 == 0x90) {
|
||||
if (! rex_prefix) {
|
||||
ia_opcode = (sse_prefix == SSE_PREFIX_F3) ? BX_IA_PAUSE : BX_IA_NOP;
|
||||
}
|
||||
}
|
||||
else {
|
||||
unsigned group = attr & BxGroupX;
|
||||
@ -2393,7 +2399,20 @@ modrm_done:
|
||||
if (vvv >= 8) ia_opcode = BX_IA_ERROR;
|
||||
break;
|
||||
case BX_SRC_VIB:
|
||||
i->setSrcReg(n, i->Ib() >> 4);
|
||||
#if BX_SUPPORT_EVEX
|
||||
if (b1 == 0x62)
|
||||
i->setSrcReg(n, ((i->Ib() << 1) & 0x10) | (i->Ib() >> 4));
|
||||
else
|
||||
#endif
|
||||
i->setSrcReg(n, (i->Ib() >> 4));
|
||||
break;
|
||||
case BX_SRC_VSIB:
|
||||
if (i->sibIndex() == BX_NIL_REGISTER) {
|
||||
ia_opcode = BX_IA_ERROR;
|
||||
}
|
||||
#if BX_SUPPORT_EVEX
|
||||
i->setSibIndex(i->sibIndex() | evex_v);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
@ -2406,9 +2425,6 @@ modrm_done:
|
||||
seg = seg_override;
|
||||
i->setSeg(seg);
|
||||
|
||||
i->setILen(remainingInPage - remain);
|
||||
i->setIaOpcode(ia_opcode);
|
||||
|
||||
#if BX_SUPPORT_AVX
|
||||
if (had_vex_xop) {
|
||||
if (! use_vvv && vvv != 0) {
|
||||
@ -2434,6 +2450,9 @@ modrm_done:
|
||||
|
||||
decode_done:
|
||||
|
||||
i->setILen(remainingInPage - remain);
|
||||
i->setIaOpcode(ia_opcode);
|
||||
|
||||
if (mod_mem) {
|
||||
i->execute1 = BxOpcodesTable[ia_opcode].execute1;
|
||||
i->handlers.execute2 = BxOpcodesTable[ia_opcode].execute2;
|
||||
|
||||
@ -50,16 +50,6 @@ bx_address BX_CPP_AttrRegparmN(2) BX_CPU_C::BxResolveGatherQ(bxInstruction_c *i,
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERDPS_VpsHps(bxInstruction_c *i)
|
||||
{
|
||||
if (! i->as32L()) {
|
||||
BX_ERROR(("VGATHERDPS_VpsHps: Gather with 16-bit address size"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
}
|
||||
|
||||
if (i->sibIndex() == BX_NIL_REGISTER) {
|
||||
BX_ERROR(("VGATHERDPS_VpsHps: incorrect source operands"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
}
|
||||
|
||||
if (i->sibIndex() == i->src2() || i->sibIndex() == i->dst() || i->src2() == i->dst()) {
|
||||
BX_ERROR(("VGATHERDPS_VpsHps: incorrect source operands"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
@ -103,16 +93,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERDPS_VpsHps(bxInstruction_c
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERQPS_VpsHps(bxInstruction_c *i)
|
||||
{
|
||||
if (! i->as32L()) {
|
||||
BX_ERROR(("VGATHERQPS_VpsHps: Gather with 16-bit address size"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
}
|
||||
|
||||
if (i->sibIndex() == BX_NIL_REGISTER) {
|
||||
BX_ERROR(("VGATHERQPS_VpsHps: incorrect source operands"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
}
|
||||
|
||||
if (i->sibIndex() == i->src2() || i->sibIndex() == i->dst() || i->src2() == i->dst()) {
|
||||
BX_ERROR(("VGATHERQPS_VpsHps: incorrect source operands"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
@ -155,16 +135,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERQPS_VpsHps(bxInstruction_c
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERDPD_VpdHpd(bxInstruction_c *i)
|
||||
{
|
||||
if (! i->as32L()) {
|
||||
BX_ERROR(("VGATHERDPD_VpdHpd: Gather with 16-bit address size"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
}
|
||||
|
||||
if (i->sibIndex() == BX_NIL_REGISTER) {
|
||||
BX_ERROR(("VGATHERDPD_VpdHpd: incorrect source operands"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
}
|
||||
|
||||
if (i->sibIndex() == i->src2() || i->sibIndex() == i->dst() || i->src2() == i->dst()) {
|
||||
BX_ERROR(("VGATHERDPD_VpdHpd: incorrect source operands"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
@ -207,16 +177,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERDPD_VpdHpd(bxInstruction_c
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VGATHERQPD_VpdHpd(bxInstruction_c *i)
|
||||
{
|
||||
if (! i->as32L()) {
|
||||
BX_ERROR(("VGATHERQPD_VpdHpd: Gather with 16-bit address size"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
}
|
||||
|
||||
if (i->sibIndex() == BX_NIL_REGISTER) {
|
||||
BX_ERROR(("VGATHERQPD_VpdHpd: incorrect source operands"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
}
|
||||
|
||||
if (i->sibIndex() == i->src2() || i->sibIndex() == i->dst() || i->src2() == i->dst()) {
|
||||
BX_ERROR(("VGATHERQPD_VpdHpd: incorrect source operands"));
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
|
||||
@ -482,9 +482,9 @@ bx_define_opcode(BX_IA_REP_MOVSW_YwXw, NULL, &BX_CPU_C::REP_MOVSW_YwXw, 0, OP_Yw
|
||||
bx_define_opcode(BX_IA_REP_OUTSB_DXXb, NULL, &BX_CPU_C::REP_OUTSB_DXXb, 0, OP_DXReg, OP_Xb, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_OUTSD_DXXd, NULL, &BX_CPU_C::REP_OUTSD_DXXd, 0, OP_DXReg, OP_Xd, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_OUTSW_DXXw, NULL, &BX_CPU_C::REP_OUTSW_DXXw, 0, OP_DXReg, OP_Xw, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_SCASB_ALXb, NULL, &BX_CPU_C::REP_SCASB_ALXb, 0, OP_ALReg, OP_Xb, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_SCASD_EAXXd, NULL, &BX_CPU_C::REP_SCASD_EAXXd, 0, OP_EAXReg, OP_Xd, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_SCASW_AXXw, NULL, &BX_CPU_C::REP_SCASW_AXXw, 0, OP_AXReg, OP_Xw, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_SCASB_ALYb, NULL, &BX_CPU_C::REP_SCASB_ALYb, 0, OP_ALReg, OP_Yb, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_SCASD_EAXYd, NULL, &BX_CPU_C::REP_SCASD_EAXYd, 0, OP_EAXReg, OP_Yd, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_SCASW_AXYw, NULL, &BX_CPU_C::REP_SCASW_AXYw, 0, OP_AXReg, OP_Yw, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_STOSB_YbAL, NULL, &BX_CPU_C::REP_STOSB_YbAL, 0, OP_Yb, OP_ALReg, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_STOSD_YdEAX, NULL, &BX_CPU_C::REP_STOSD_YdEAX, 0, OP_Yd, OP_EAXReg, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_STOSW_YwAX, NULL, &BX_CPU_C::REP_STOSW_YwAX, 0, OP_Yw, OP_AXReg, OP_NONE, OP_NONE, 0)
|
||||
@ -788,13 +788,13 @@ bx_define_opcode(BX_IA_PUNPCKHBW_PqQq, &BX_CPU_C::PUNPCKHBW_PqQq, &BX_CPU_C::PUN
|
||||
bx_define_opcode(BX_IA_PUNPCKHWD_PqQq, &BX_CPU_C::PUNPCKHWD_PqQq, &BX_CPU_C::PUNPCKHWD_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PUNPCKHDQ_PqQq, &BX_CPU_C::PUNPCKHDQ_PqQq, &BX_CPU_C::PUNPCKHDQ_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PACKSSDW_PqQq, &BX_CPU_C::PACKSSDW_PqQq, &BX_CPU_C::PACKSSDW_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_MOVD_PqEd, &BX_CPU_C::MOVD_PqEdM, &BX_CPU_C::MOVD_PqEdR, BX_ISA_MMX, OP_Pq, OP_Eq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_MOVD_PqEd, &BX_CPU_C::MOVD_PqEdM, &BX_CPU_C::MOVD_PqEdR, BX_ISA_MMX, OP_Pq, OP_Ed, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_MOVQ_PqQq, &BX_CPU_C::MOVQ_PqQqM, &BX_CPU_C::MOVQ_PqQqR, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PCMPEQB_PqQq, &BX_CPU_C::PCMPEQB_PqQq, &BX_CPU_C::PCMPEQB_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PCMPEQW_PqQq, &BX_CPU_C::PCMPEQW_PqQq, &BX_CPU_C::PCMPEQW_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PCMPEQD_PqQq, &BX_CPU_C::PCMPEQD_PqQq, &BX_CPU_C::PCMPEQD_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_EMMS, NULL, &BX_CPU_C::EMMS, BX_ISA_MMX, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_MOVD_EdPd, &BX_CPU_C::MOVD_EdPdM, &BX_CPU_C::MOVD_EdPdR, BX_ISA_MMX, OP_Ed, OP_Pd, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_MOVD_EdPq, &BX_CPU_C::MOVD_EdPqM, &BX_CPU_C::MOVD_EdPqR, BX_ISA_MMX, OP_Ed, OP_Pq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_MOVQ_QqPq, &BX_CPU_C::MOVQ_QqPqM, &BX_CPU_C::MOVQ_PqQqR, BX_ISA_MMX, OP_Qq, OP_Pq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PSRLW_PqQq, &BX_CPU_C::PSRLW_PqQq, &BX_CPU_C::PSRLW_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PSRLD_PqQq, &BX_CPU_C::PSRLD_PqQq, &BX_CPU_C::PSRLD_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
@ -954,7 +954,7 @@ bx_define_opcode(BX_IA_RCPSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RCPSS_VssWs
|
||||
bx_define_opcode(BX_IA_PSHUFW_PqQqIb, &BX_CPU_C::PSHUFW_PqQqIb, &BX_CPU_C::PSHUFW_PqQqIb, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Qq, OP_Ib, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFLW_VdqWdqIbR, BX_ISA_SSE, OP_Vdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PINSRW_PqEwIb, &BX_CPU_C::PINSRW_PqEwIb, &BX_CPU_C::PINSRW_PqEwIb, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Ew, OP_Ib, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PEXTRW_GdNqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdNqIb, BX_ISA_SSE | BX_ISA_3DNOW, OP_Gd, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PEXTRW_GdNqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdNqIb, BX_ISA_SSE | BX_ISA_3DNOW, OP_Gd, OP_Qq, OP_Ib, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_SHUFPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPS_VpsWpsIbR, BX_ISA_SSE, OP_Vps, OP_Wps, OP_Ib, OP_NONE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMOVMSKB_GdNq, &BX_CPU_C::BxError, &BX_CPU_C::PMOVMSKB_GdNq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Gd, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_PMINUB_PqQq, &BX_CPU_C::PMINUB_PqQq, &BX_CPU_C::PMINUB_PqQq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
|
||||
@ -1376,7 +1376,7 @@ bx_define_opcode(BX_IA_REP_MOVSQ_YqXq, NULL, &BX_CPU_C::REP_MOVSQ_YqXq, 0, OP_Yq
|
||||
bx_define_opcode(BX_IA_REP_CMPSQ_XqYq, NULL, &BX_CPU_C::REP_CMPSQ_XqYq, 0, OP_Xq, OP_Yq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_STOSQ_YqRAX, NULL, &BX_CPU_C::REP_STOSQ_YqRAX, 0, OP_Yq, OP_RAXReg, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_LODSQ_RAXXq, NULL, &BX_CPU_C::REP_LODSQ_RAXXq, 0, OP_RAXReg, OP_Xq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_SCASQ_RAXXq, NULL, &BX_CPU_C::REP_SCASQ_RAXXq, 0, OP_RAXReg, OP_Xq, OP_NONE, OP_NONE, 0)
|
||||
bx_define_opcode(BX_IA_REP_SCASQ_RAXYq, NULL, &BX_CPU_C::REP_SCASQ_RAXYq, 0, OP_RAXReg, OP_Yq, OP_NONE, OP_NONE, 0)
|
||||
|
||||
bx_define_opcode(BX_IA_CALL_Jq, NULL, &BX_CPU_C::CALL_Jq, 0, OP_Jq, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
|
||||
bx_define_opcode(BX_IA_JMP_Jq, NULL, &BX_CPU_C::JMP_Jq, 0, OP_Jq, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
|
||||
@ -1565,8 +1565,8 @@ bx_define_opcode(BX_IA_VMREAD_EqGq, &BX_CPU_C::VMREAD_EqGq, &BX_CPU_C::VMREAD_Eq
|
||||
bx_define_opcode(BX_IA_VMWRITE_GqEq, &BX_CPU_C::VMWRITE_GqEq, &BX_CPU_C::VMWRITE_GqEq, BX_ISA_VMX, OP_Gq, OP_Eq, OP_NONE, OP_NONE, 0)
|
||||
#endif
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
bx_define_opcode(BX_IA_INVEPT, &BX_CPU_C::INVEPT, &BX_CPU_C::BxError, BX_ISA_VMX, BX_SRC_NNN, BX_SRC_RM, OP_NONE, OP_NONE, BX_TRACE_END) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_INVVPID, &BX_CPU_C::INVVPID, &BX_CPU_C::BxError, BX_ISA_VMX, BX_SRC_NNN, BX_SRC_RM, OP_NONE, OP_NONE, BX_TRACE_END) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_INVEPT, &BX_CPU_C::INVEPT, &BX_CPU_C::BxError, BX_ISA_VMX, OP_Gd, OP_Wdq, OP_NONE, OP_NONE, BX_TRACE_END)
|
||||
bx_define_opcode(BX_IA_INVVPID, &BX_CPU_C::INVVPID, &BX_CPU_C::BxError, BX_ISA_VMX, OP_Gd, OP_Wdq, OP_NONE, OP_NONE, BX_TRACE_END)
|
||||
#endif
|
||||
bx_define_opcode(BX_IA_VMFUNC, &BX_CPU_C::BxError, &BX_CPU_C::VMFUNC, BX_ISA_VMX, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
|
||||
// VMX
|
||||
@ -1587,7 +1587,7 @@ bx_define_opcode(BX_IA_INVLPGA, &BX_CPU_C::BxError, &BX_CPU_C::INVLPGA, BX_ISA_S
|
||||
// SVM
|
||||
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
bx_define_opcode(BX_IA_INVPCID, &BX_CPU_C::INVPCID, &BX_CPU_C::BxError, BX_ISA_INVPCID, BX_SRC_NNN, BX_SRC_RM, OP_NONE, OP_NONE, BX_TRACE_END) // FIXME disasm
|
||||
bx_define_opcode(BX_IA_INVPCID, &BX_CPU_C::INVPCID, &BX_CPU_C::BxError, BX_ISA_INVPCID, OP_Gd, OP_Wdq, OP_NONE, OP_NONE, BX_TRACE_END)
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
|
||||
@ -2566,4 +2566,5 @@ bx_define_opcode(BX_IA_V512_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_Vecto
|
||||
bx_define_opcode(BX_IA_V512_VUNPCKHPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX)
|
||||
bx_define_opcode(BX_IA_V512_VUNPCKHPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX)
|
||||
// VexW alias
|
||||
|
||||
#endif
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
// $Id$
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2002-2012 Stanislav Shwartsman
|
||||
// Copyright (c) 2002-2013 Stanislav Shwartsman
|
||||
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
|
||||
//
|
||||
// This library is free software; you can redistribute it and/or
|
||||
@ -1122,7 +1122,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EMMS(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* 0F 7E */
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdPdR(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdPqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
@ -1135,7 +1135,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdPdR(bxInstruction_c *i)
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdPdM(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdPqM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
@ -1227,71 +1227,71 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPSQ64_XqYq(bxInstruction_c *i)
|
||||
// REP SCAS methods
|
||||
//
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::REP_SCASB_ALXb(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::REP_SCASB_ALYb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->as64L()) {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASB64_ALXb);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASB64_ALYb);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if (i->as32L()) {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASB32_ALXb);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASB32_ALYb);
|
||||
BX_CLEAR_64BIT_HIGH(BX_64BIT_REG_RDI); // always clear upper part of RDI
|
||||
}
|
||||
else {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASB16_ALXb);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASB16_ALYb);
|
||||
}
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::REP_SCASW_AXXw(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::REP_SCASW_AXYw(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->as64L()) {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASW64_AXXw);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASW64_AXYw);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if (i->as32L()) {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASW32_AXXw);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASW32_AXYw);
|
||||
BX_CLEAR_64BIT_HIGH(BX_64BIT_REG_RDI); // always clear upper part of RDI
|
||||
}
|
||||
else {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASW16_AXXw);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASW16_AXYw);
|
||||
}
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::REP_SCASD_EAXXd(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::REP_SCASD_EAXYd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (i->as64L()) {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASD64_EAXXd);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASD64_EAXYd);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if (i->as32L()) {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASD32_EAXXd);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASD32_EAXYd);
|
||||
BX_CLEAR_64BIT_HIGH(BX_64BIT_REG_RDI); // always clear upper part of RDI
|
||||
}
|
||||
else {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASD16_EAXXd);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASD16_EAXYd);
|
||||
}
|
||||
|
||||
BX_NEXT_INSTR(i);
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::REP_SCASQ_RAXXq(bxInstruction_c *i)
|
||||
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::REP_SCASQ_RAXYq(bxInstruction_c *i)
|
||||
{
|
||||
if (i->as64L()) {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASQ64_RAXXq);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASQ64_RAXYq);
|
||||
}
|
||||
else {
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASQ32_RAXXq);
|
||||
BX_CPU_THIS_PTR repeat_ZF(i, &BX_CPU_C::SCASQ32_RAXYq);
|
||||
BX_CLEAR_64BIT_HIGH(BX_64BIT_REG_RDI); // always clear upper part of RDI
|
||||
}
|
||||
|
||||
@ -1304,7 +1304,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::REP_SCASQ_RAXXq(bxInstruction_c *i
|
||||
//
|
||||
|
||||
/* 16 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASB16_ALXb(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASB16_ALYb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8 = AL, op2_8, diff_8;
|
||||
|
||||
@ -1327,7 +1327,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASB16_ALXb(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* 32 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASB32_ALXb(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASB32_ALYb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8 = AL, op2_8, diff_8;
|
||||
|
||||
@ -1351,7 +1351,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASB32_ALXb(bxInstruction_c *i)
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
/* 64 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASB64_ALXb(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASB64_ALYb(bxInstruction_c *i)
|
||||
{
|
||||
Bit8u op1_8 = AL, op2_8, diff_8;
|
||||
|
||||
@ -1375,7 +1375,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASB64_ALXb(bxInstruction_c *i)
|
||||
#endif
|
||||
|
||||
/* 16 bit opsize mode, 16 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASW16_AXXw(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASW16_AXYw(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16 = AX, op2_16, diff_16;
|
||||
|
||||
@ -1397,7 +1397,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASW16_AXXw(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* 16 bit opsize mode, 32 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASW32_AXXw(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASW32_AXYw(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16 = AX, op2_16, diff_16;
|
||||
|
||||
@ -1421,7 +1421,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASW32_AXXw(bxInstruction_c *i)
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
/* 16 bit opsize mode, 64 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASW64_AXXw(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASW64_AXYw(bxInstruction_c *i)
|
||||
{
|
||||
Bit16u op1_16 = AX, op2_16, diff_16;
|
||||
|
||||
@ -1445,7 +1445,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASW64_AXXw(bxInstruction_c *i)
|
||||
#endif
|
||||
|
||||
/* 32 bit opsize mode, 16 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASD16_EAXXd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASD16_EAXYd(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32 = EAX, op2_32, diff_32;
|
||||
|
||||
@ -1467,7 +1467,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASD16_EAXXd(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* 32 bit opsize mode, 32 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASD32_EAXXd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASD32_EAXYd(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32 = EAX, op2_32, diff_32;
|
||||
|
||||
@ -1492,7 +1492,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASD32_EAXXd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_X86_64
|
||||
|
||||
/* 32 bit opsize mode, 64 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASD64_EAXXd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASD64_EAXYd(bxInstruction_c *i)
|
||||
{
|
||||
Bit32u op1_32 = EAX, op2_32, diff_32;
|
||||
|
||||
@ -1515,7 +1515,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASD64_EAXXd(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* 64 bit opsize mode, 32 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASQ32_RAXXq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASQ32_RAXYq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64 = RAX, op2_64, diff_64;
|
||||
|
||||
@ -1539,7 +1539,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASQ32_RAXXq(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* 64 bit opsize mode, 64 bit address size */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASQ64_RAXXq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SCASQ64_RAXYq(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64 = RAX, op2_64, diff_64;
|
||||
|
||||
|
||||
@ -86,7 +86,8 @@ Bit32u gen_instruction_info(bxInstruction_c *i, Bit32u reason, bx_bool rw_form)
|
||||
|
||||
instr_info |= i->seg() << 15;
|
||||
|
||||
if (i->sibIndex() != BX_NIL_REGISTER)
|
||||
// index field is always initialized because of gather but not always valid
|
||||
if (i->sibIndex() != BX_NIL_REGISTER && i->sibIndex() != 4)
|
||||
instr_info |= i->sibScale() | (i->sibIndex() << 18);
|
||||
else
|
||||
instr_info |= 1 << 22; // index invalid
|
||||
|
||||
@ -503,11 +503,11 @@ void disassembler::OP_O(const x86_insn *insn, unsigned size)
|
||||
}
|
||||
else if (insn->as_32) {
|
||||
Bit32u imm32 = fetch_dword();
|
||||
dis_sprintf("%s:0x%x", seg, (unsigned) imm32);
|
||||
dis_sprintf("%s:0x%08x", seg, (unsigned) imm32);
|
||||
}
|
||||
else {
|
||||
Bit16u imm16 = fetch_word();
|
||||
dis_sprintf("%s:0x%x", seg, (unsigned) imm16);
|
||||
dis_sprintf("%s:0x%04x", seg, (unsigned) imm16);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -861,8 +861,8 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes16[256*2] = {
|
||||
/* AB */ { 0, &Ia_stosw_Yw_AX },
|
||||
/* AC */ { 0, &Ia_lodsb_AL_Xb },
|
||||
/* AD */ { 0, &Ia_lodsw_AX_Xw },
|
||||
/* AE */ { 0, &Ia_scasb_Yb_AL },
|
||||
/* AF */ { 0, &Ia_scasw_Yw_AX },
|
||||
/* AE */ { 0, &Ia_scasb_AL_Yb },
|
||||
/* AF */ { 0, &Ia_scasw_AX_Yw },
|
||||
/* B0 */ { 0, &Ia_movb_R8_Ib },
|
||||
/* B1 */ { 0, &Ia_movb_R8_Ib },
|
||||
/* B2 */ { 0, &Ia_movb_R8_Ib },
|
||||
@ -1011,20 +1011,20 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes16[256*2] = {
|
||||
/* 0F 3F */ { 0, &Ia_Invalid },
|
||||
/* 0F 40 */ { 0, &Ia_cmovow_Gw_Ew },
|
||||
/* 0F 41 */ { 0, &Ia_cmovnow_Gw_Ew },
|
||||
/* 0F 42 */ { 0, &Ia_cmovcw_Gw_Ew },
|
||||
/* 0F 43 */ { 0, &Ia_cmovncw_Gw_Ew },
|
||||
/* 0F 42 */ { 0, &Ia_cmovbw_Gw_Ew },
|
||||
/* 0F 43 */ { 0, &Ia_cmovnbw_Gw_Ew },
|
||||
/* 0F 44 */ { 0, &Ia_cmovzw_Gw_Ew },
|
||||
/* 0F 45 */ { 0, &Ia_cmovnzw_Gw_Ew },
|
||||
/* 0F 46 */ { 0, &Ia_cmovnaw_Gw_Ew },
|
||||
/* 0F 47 */ { 0, &Ia_cmovaw_Gw_Ew },
|
||||
/* 0F 46 */ { 0, &Ia_cmovbew_Gw_Ew },
|
||||
/* 0F 47 */ { 0, &Ia_cmovnbew_Gw_Ew },
|
||||
/* 0F 48 */ { 0, &Ia_cmovsw_Gw_Ew },
|
||||
/* 0F 49 */ { 0, &Ia_cmovnsw_Gw_Ew },
|
||||
/* 0F 4A */ { 0, &Ia_cmovpw_Gw_Ew },
|
||||
/* 0F 4B */ { 0, &Ia_cmovnpw_Gw_Ew },
|
||||
/* 0F 4C */ { 0, &Ia_cmovlw_Gw_Ew },
|
||||
/* 0F 4D */ { 0, &Ia_cmovnlw_Gw_Ew },
|
||||
/* 0F 4E */ { 0, &Ia_cmovngw_Gw_Ew },
|
||||
/* 0F 4F */ { 0, &Ia_cmovgw_Gw_Ew },
|
||||
/* 0F 4E */ { 0, &Ia_cmovlew_Gw_Ew },
|
||||
/* 0F 4F */ { 0, &Ia_cmovnlew_Gw_Ew },
|
||||
/* 0F 50 */ { GRPSSE2(0f50) },
|
||||
/* 0F 51 */ { GRPSSE(0f51) },
|
||||
/* 0F 52 */ { GRPSSE(0f52) },
|
||||
@ -1382,8 +1382,8 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes32[256*2] = {
|
||||
/* AB */ { 0, &Ia_stosl_Yd_EAX },
|
||||
/* AC */ { 0, &Ia_lodsb_AL_Xb },
|
||||
/* AD */ { 0, &Ia_lodsl_EAX_Xd },
|
||||
/* AE */ { 0, &Ia_scasb_Yb_AL },
|
||||
/* AF */ { 0, &Ia_scasl_Yd_EAX },
|
||||
/* AE */ { 0, &Ia_scasb_AL_Yb },
|
||||
/* AF */ { 0, &Ia_scasl_EAX_Yd },
|
||||
/* B0 */ { 0, &Ia_movb_R8_Ib },
|
||||
/* B1 */ { 0, &Ia_movb_R8_Ib },
|
||||
/* B2 */ { 0, &Ia_movb_R8_Ib },
|
||||
@ -1532,20 +1532,20 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes32[256*2] = {
|
||||
/* 0F 3F */ { 0, &Ia_Invalid },
|
||||
/* 0F 40 */ { 0, &Ia_cmovol_Gd_Ed },
|
||||
/* 0F 41 */ { 0, &Ia_cmovnol_Gd_Ed },
|
||||
/* 0F 42 */ { 0, &Ia_cmovcl_Gd_Ed },
|
||||
/* 0F 43 */ { 0, &Ia_cmovncl_Gd_Ed },
|
||||
/* 0F 42 */ { 0, &Ia_cmovbl_Gd_Ed },
|
||||
/* 0F 43 */ { 0, &Ia_cmovnbl_Gd_Ed },
|
||||
/* 0F 44 */ { 0, &Ia_cmovzl_Gd_Ed },
|
||||
/* 0F 45 */ { 0, &Ia_cmovnzl_Gd_Ed },
|
||||
/* 0F 46 */ { 0, &Ia_cmovnal_Gd_Ed },
|
||||
/* 0F 47 */ { 0, &Ia_cmoval_Gd_Ed },
|
||||
/* 0F 46 */ { 0, &Ia_cmovbel_Gd_Ed },
|
||||
/* 0F 47 */ { 0, &Ia_cmovnbel_Gd_Ed },
|
||||
/* 0F 48 */ { 0, &Ia_cmovsl_Gd_Ed },
|
||||
/* 0F 49 */ { 0, &Ia_cmovnsl_Gd_Ed },
|
||||
/* 0F 4A */ { 0, &Ia_cmovpl_Gd_Ed },
|
||||
/* 0F 4B */ { 0, &Ia_cmovnpl_Gd_Ed },
|
||||
/* 0F 4C */ { 0, &Ia_cmovll_Gd_Ed },
|
||||
/* 0F 4D */ { 0, &Ia_cmovnll_Gd_Ed },
|
||||
/* 0F 4E */ { 0, &Ia_cmovngl_Gd_Ed },
|
||||
/* 0F 4F */ { 0, &Ia_cmovgl_Gd_Ed },
|
||||
/* 0F 4E */ { 0, &Ia_cmovlel_Gd_Ed },
|
||||
/* 0F 4F */ { 0, &Ia_cmovnlel_Gd_Ed },
|
||||
/* 0F 50 */ { GRPSSE2(0f50) },
|
||||
/* 0F 51 */ { GRPSSE(0f51) },
|
||||
/* 0F 52 */ { GRPSSE(0f52) },
|
||||
@ -1903,8 +1903,8 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes64w[256*2] = {
|
||||
/* AB */ { 0, &Ia_stosw_Yw_AX },
|
||||
/* AC */ { 0, &Ia_lodsb_AL_Xb },
|
||||
/* AD */ { 0, &Ia_lodsw_AX_Xw },
|
||||
/* AE */ { 0, &Ia_scasb_Yb_AL },
|
||||
/* AF */ { 0, &Ia_scasw_Yw_AX },
|
||||
/* AE */ { 0, &Ia_scasb_AL_Yb },
|
||||
/* AF */ { 0, &Ia_scasw_AX_Yw },
|
||||
/* B0 */ { 0, &Ia_movb_R8_Ib },
|
||||
/* B1 */ { 0, &Ia_movb_R8_Ib },
|
||||
/* B2 */ { 0, &Ia_movb_R8_Ib },
|
||||
@ -2053,20 +2053,20 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes64w[256*2] = {
|
||||
/* 0F 3F */ { 0, &Ia_Invalid },
|
||||
/* 0F 40 */ { 0, &Ia_cmovow_Gw_Ew },
|
||||
/* 0F 41 */ { 0, &Ia_cmovnow_Gw_Ew },
|
||||
/* 0F 42 */ { 0, &Ia_cmovcw_Gw_Ew },
|
||||
/* 0F 43 */ { 0, &Ia_cmovncw_Gw_Ew },
|
||||
/* 0F 42 */ { 0, &Ia_cmovbw_Gw_Ew },
|
||||
/* 0F 43 */ { 0, &Ia_cmovnbw_Gw_Ew },
|
||||
/* 0F 44 */ { 0, &Ia_cmovzw_Gw_Ew },
|
||||
/* 0F 45 */ { 0, &Ia_cmovnzw_Gw_Ew },
|
||||
/* 0F 46 */ { 0, &Ia_cmovnaw_Gw_Ew },
|
||||
/* 0F 47 */ { 0, &Ia_cmovaw_Gw_Ew },
|
||||
/* 0F 46 */ { 0, &Ia_cmovbew_Gw_Ew },
|
||||
/* 0F 47 */ { 0, &Ia_cmovnbew_Gw_Ew },
|
||||
/* 0F 48 */ { 0, &Ia_cmovsw_Gw_Ew },
|
||||
/* 0F 49 */ { 0, &Ia_cmovnsw_Gw_Ew },
|
||||
/* 0F 4A */ { 0, &Ia_cmovpw_Gw_Ew },
|
||||
/* 0F 4B */ { 0, &Ia_cmovnpw_Gw_Ew },
|
||||
/* 0F 4C */ { 0, &Ia_cmovlw_Gw_Ew },
|
||||
/* 0F 4D */ { 0, &Ia_cmovnlw_Gw_Ew },
|
||||
/* 0F 4E */ { 0, &Ia_cmovngw_Gw_Ew },
|
||||
/* 0F 4F */ { 0, &Ia_cmovgw_Gw_Ew },
|
||||
/* 0F 4E */ { 0, &Ia_cmovlew_Gw_Ew },
|
||||
/* 0F 4F */ { 0, &Ia_cmovnlew_Gw_Ew },
|
||||
/* 0F 50 */ { GRPSSE2(0f50) },
|
||||
/* 0F 51 */ { GRPSSE(0f51) },
|
||||
/* 0F 52 */ { GRPSSE(0f52) },
|
||||
@ -2421,8 +2421,8 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes64d[256*2] = {
|
||||
/* AB */ { 0, &Ia_stosl_Yd_EAX },
|
||||
/* AC */ { 0, &Ia_lodsb_AL_Xb },
|
||||
/* AD */ { 0, &Ia_lodsl_EAX_Xd },
|
||||
/* AE */ { 0, &Ia_scasb_Yb_AL },
|
||||
/* AF */ { 0, &Ia_scasl_Yd_EAX },
|
||||
/* AE */ { 0, &Ia_scasb_AL_Yb },
|
||||
/* AF */ { 0, &Ia_scasl_EAX_Yd },
|
||||
/* B0 */ { 0, &Ia_movb_R8_Ib },
|
||||
/* B1 */ { 0, &Ia_movb_R8_Ib },
|
||||
/* B2 */ { 0, &Ia_movb_R8_Ib },
|
||||
@ -2571,20 +2571,20 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes64d[256*2] = {
|
||||
/* 0F 3F */ { 0, &Ia_Invalid },
|
||||
/* 0F 40 */ { 0, &Ia_cmovol_Gd_Ed },
|
||||
/* 0F 41 */ { 0, &Ia_cmovnol_Gd_Ed },
|
||||
/* 0F 42 */ { 0, &Ia_cmovcl_Gd_Ed },
|
||||
/* 0F 43 */ { 0, &Ia_cmovncl_Gd_Ed },
|
||||
/* 0F 42 */ { 0, &Ia_cmovbl_Gd_Ed },
|
||||
/* 0F 43 */ { 0, &Ia_cmovnbl_Gd_Ed },
|
||||
/* 0F 44 */ { 0, &Ia_cmovzl_Gd_Ed },
|
||||
/* 0F 45 */ { 0, &Ia_cmovnzl_Gd_Ed },
|
||||
/* 0F 46 */ { 0, &Ia_cmovnal_Gd_Ed },
|
||||
/* 0F 47 */ { 0, &Ia_cmoval_Gd_Ed },
|
||||
/* 0F 46 */ { 0, &Ia_cmovbel_Gd_Ed },
|
||||
/* 0F 47 */ { 0, &Ia_cmovnbel_Gd_Ed },
|
||||
/* 0F 48 */ { 0, &Ia_cmovsl_Gd_Ed },
|
||||
/* 0F 49 */ { 0, &Ia_cmovnsl_Gd_Ed },
|
||||
/* 0F 4A */ { 0, &Ia_cmovpl_Gd_Ed },
|
||||
/* 0F 4B */ { 0, &Ia_cmovnpl_Gd_Ed },
|
||||
/* 0F 4C */ { 0, &Ia_cmovll_Gd_Ed },
|
||||
/* 0F 4D */ { 0, &Ia_cmovnll_Gd_Ed },
|
||||
/* 0F 4E */ { 0, &Ia_cmovngl_Gd_Ed },
|
||||
/* 0F 4F */ { 0, &Ia_cmovgl_Gd_Ed },
|
||||
/* 0F 4E */ { 0, &Ia_cmovlel_Gd_Ed },
|
||||
/* 0F 4F */ { 0, &Ia_cmovnlel_Gd_Ed },
|
||||
/* 0F 50 */ { GRPSSE2(0f50) },
|
||||
/* 0F 51 */ { GRPSSE(0f51) },
|
||||
/* 0F 52 */ { GRPSSE(0f52) },
|
||||
@ -2939,8 +2939,8 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes64q[256*2] = {
|
||||
/* AB */ { 0, &Ia_stosq_Yq_RAX },
|
||||
/* AC */ { 0, &Ia_lodsb_AL_Xb },
|
||||
/* AD */ { 0, &Ia_lodsq_RAX_Xq },
|
||||
/* AE */ { 0, &Ia_scasb_Yb_AL },
|
||||
/* AF */ { 0, &Ia_scasq_Yq_RAX },
|
||||
/* AE */ { 0, &Ia_scasb_AL_Yb },
|
||||
/* AF */ { 0, &Ia_scasq_RAX_Yq },
|
||||
/* B0 */ { 0, &Ia_movb_R8_Ib },
|
||||
/* B1 */ { 0, &Ia_movb_R8_Ib },
|
||||
/* B2 */ { 0, &Ia_movb_R8_Ib },
|
||||
@ -3089,20 +3089,20 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes64q[256*2] = {
|
||||
/* 0F 3F */ { 0, &Ia_Invalid },
|
||||
/* 0F 40 */ { 0, &Ia_cmovoq_Gq_Eq },
|
||||
/* 0F 41 */ { 0, &Ia_cmovnoq_Gq_Eq },
|
||||
/* 0F 42 */ { 0, &Ia_cmovcq_Gq_Eq },
|
||||
/* 0F 43 */ { 0, &Ia_cmovncq_Gq_Eq },
|
||||
/* 0F 42 */ { 0, &Ia_cmovbq_Gq_Eq },
|
||||
/* 0F 43 */ { 0, &Ia_cmovnbq_Gq_Eq },
|
||||
/* 0F 44 */ { 0, &Ia_cmovzq_Gq_Eq },
|
||||
/* 0F 45 */ { 0, &Ia_cmovnzq_Gq_Eq },
|
||||
/* 0F 46 */ { 0, &Ia_cmovnaq_Gq_Eq },
|
||||
/* 0F 47 */ { 0, &Ia_cmovaq_Gq_Eq },
|
||||
/* 0F 46 */ { 0, &Ia_cmovbeq_Gq_Eq },
|
||||
/* 0F 47 */ { 0, &Ia_cmovnbeq_Gq_Eq },
|
||||
/* 0F 48 */ { 0, &Ia_cmovsq_Gq_Eq },
|
||||
/* 0F 49 */ { 0, &Ia_cmovnsq_Gq_Eq },
|
||||
/* 0F 4A */ { 0, &Ia_cmovpq_Gq_Eq },
|
||||
/* 0F 4B */ { 0, &Ia_cmovnpq_Gq_Eq },
|
||||
/* 0F 4C */ { 0, &Ia_cmovlq_Gq_Eq },
|
||||
/* 0F 4D */ { 0, &Ia_cmovnlq_Gq_Eq },
|
||||
/* 0F 4E */ { 0, &Ia_cmovngq_Gq_Eq },
|
||||
/* 0F 4F */ { 0, &Ia_cmovgq_Gq_Eq },
|
||||
/* 0F 4E */ { 0, &Ia_cmovleq_Gq_Eq },
|
||||
/* 0F 4F */ { 0, &Ia_cmovnleq_Gq_Eq },
|
||||
/* 0F 50 */ { GRPSSE2(0f50) },
|
||||
/* 0F 51 */ { GRPSSE(0f51) },
|
||||
/* 0F 52 */ { GRPSSE(0f52) },
|
||||
|
||||
@ -172,27 +172,27 @@ Ia_clgi = { "clgi", "clgi", XX, XX, XX, XX, IA_SVM },
|
||||
Ia_cli = { "cli", "cli", XX, XX, XX, XX, 0 },
|
||||
Ia_clts = { "clts", "clts", XX, XX, XX, XX, 0 },
|
||||
Ia_cmc = { "cmc", "cmc", XX, XX, XX, XX, 0 },
|
||||
Ia_cmoval_Gd_Ed = { "cmova", "cmoval", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovaq_Gq_Eq = { "cmova", "cmovaq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovaw_Gw_Ew = { "cmova", "cmovaw", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovcl_Gd_Ed = { "cmovc", "cmovcl", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovcq_Gq_Eq = { "cmovc", "cmovcq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovcw_Gw_Ew = { "cmovc", "cmovcw", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovgl_Gd_Ed = { "cmovg", "cmovgl", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovgq_Gq_Eq = { "cmovg", "cmovgq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovgw_Gw_Ew = { "cmovg", "cmovgw", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovnbel_Gd_Ed = { "cmovnbe", "cmovnbel", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovnbeq_Gq_Eq = { "cmovnbe", "cmovnbeq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovnbew_Gw_Ew = { "cmovnbe", "cmovnbew", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovbl_Gd_Ed = { "cmovb", "cmovbl", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovbq_Gq_Eq = { "cmovb", "cmovbq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovbw_Gw_Ew = { "cmovb", "cmovbw", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovnlel_Gd_Ed = { "cmovnle", "cmovnlel", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovnleq_Gq_Eq = { "cmovnle", "cmovnleq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovnlew_Gw_Ew = { "cmovnle", "cmovnlew", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovll_Gd_Ed = { "cmovl", "cmovll", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovlq_Gq_Eq = { "cmovl", "cmovlq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovlw_Gw_Ew = { "cmovl", "cmovlw", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovnal_Gd_Ed = { "cmovna", "cmovnal", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovnaq_Gq_Eq = { "cmovna", "cmovnaq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovnaw_Gw_Ew = { "cmovna", "cmovnaw", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovncl_Gd_Ed = { "cmovnc", "cmovncl", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovncq_Gq_Eq = { "cmovnc", "cmovncq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovncw_Gw_Ew = { "cmovnc", "cmovncw", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovngl_Gd_Ed = { "cmovng", "cmovngl", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovngq_Gq_Eq = { "cmovng", "cmovngq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovngw_Gw_Ew = { "cmovng", "cmovngw", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovbel_Gd_Ed = { "cmovbe", "cmovbel", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovbeq_Gq_Eq = { "cmovbe", "cmovbeq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovbew_Gw_Ew = { "cmovbe", "cmovbew", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovnbl_Gd_Ed = { "cmovnb", "cmovnbl", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovnbq_Gq_Eq = { "cmovnb", "cmovnbq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovnbw_Gw_Ew = { "cmovnb", "cmovnbw", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovlel_Gd_Ed = { "cmovle", "cmovlel", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovleq_Gq_Eq = { "cmovle", "cmovleq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovlew_Gw_Ew = { "cmovle", "cmovlew", Gw, Ew, XX, XX, IA_P6 },
|
||||
Ia_cmovnll_Gd_Ed = { "cmovnl", "cmovnll", Gd, Ed, XX, XX, IA_P6 },
|
||||
Ia_cmovnlq_Gq_Eq = { "cmovnl", "cmovnlq", Gq, Eq, XX, XX, 0 },
|
||||
Ia_cmovnlw_Gw_Ew = { "cmovnl", "cmovnlw", Gw, Ew, XX, XX, IA_P6 },
|
||||
@ -612,9 +612,9 @@ Ia_lssl_Gd_Mp = { "lss", "lssl", Gd, Mp, XX, XX, 0 },
|
||||
Ia_lssq_Gq_Mp = { "lss", "lssq", Gq, Mp, XX, XX, 0 },
|
||||
Ia_lssw_Gw_Mp = { "lss", "lssw", Gw, Mp, XX, XX, 0 },
|
||||
Ia_ltr = { "ltr", "ltr", Ew, XX, XX, XX, 0 },
|
||||
Ia_lzcntl_Gd_Ed = { "lzcntl", "lzcntl", Gd, Ed, XX, XX, IA_LZCNT },
|
||||
Ia_lzcntq_Gq_Eq = { "lzcntq", "lzcntq", Gq, Eq, XX, XX, IA_LZCNT },
|
||||
Ia_lzcntw_Gw_Ew = { "lzcntw", "lzcntw", Gw, Ew, XX, XX, IA_LZCNT },
|
||||
Ia_lzcntl_Gd_Ed = { "lzcnt", "lzcntl", Gd, Ed, XX, XX, IA_LZCNT },
|
||||
Ia_lzcntq_Gq_Eq = { "lzcnt", "lzcntq", Gq, Eq, XX, XX, IA_LZCNT },
|
||||
Ia_lzcntw_Gw_Ew = { "lzcnt", "lzcntw", Gw, Ew, XX, XX, IA_LZCNT },
|
||||
Ia_maskmovdqu_Vdq_Udq = { "maskmovdqu", "maskmovdqu", Vdq, Udq, sYdq, XX, IA_SSE2 },
|
||||
Ia_maskmovq_Pq_Nq = { "maskmovq", "maskmovq", Pq, Nq, sYq, XX, IA_3DNOW | IA_SSE },
|
||||
Ia_maxpd_Vpd_Wpd = { "maxpd", "maxpd", Vpd, Wpd, XX, XX, IA_SSE2 },
|
||||
@ -680,7 +680,7 @@ Ia_movmskps_Gd_Ups = { "movmskps", "movmskps", Gd, Ups, XX, XX, IA_SSE },
|
||||
Ia_movntdq_Mdq_Vdq = { "movntdq", "movntdq", Mdq, Vdq, XX, XX, IA_SSE2 },
|
||||
Ia_movntdqa_Vdq_Mdq = { "movntdqa", "movntdqa", Vdq, Mdq, XX, XX, IA_SSE4_1 },
|
||||
Ia_movnti_Md_Gd = { "movnti", "movnti", Md, Gd, XX, XX, IA_SSE2 },
|
||||
Ia_movntiq_Mq_Gq = { "movntiq", "movntiq", Mq, Gq, XX, XX, 0 },
|
||||
Ia_movntiq_Mq_Gq = { "movnti", "movntiq", Mq, Gq, XX, XX, 0 },
|
||||
Ia_movntpd_Mpd_Vpd = { "movntpd", "movntpd", Mpd, Vpd, XX, XX, IA_SSE2 },
|
||||
Ia_movntps_Mps_Vps = { "movntps", "movntps", Mps, Vps, XX, XX, IA_SSE },
|
||||
Ia_movntq_Mq_Pq = { "movntq", "movntq", Mq, Pq, XX, XX, IA_3DNOW | IA_SSE },
|
||||
@ -944,13 +944,13 @@ Ia_pmullw_Pq_Qq = { "pmullw", "pmullw", Pq, Qq, XX, XX, IA_MMX },
|
||||
Ia_pmullw_Vdq_Wdq = { "pmullw", "pmullw", Vdq, Wdq, XX, XX, IA_SSE2 },
|
||||
Ia_pmuludq_Pq_Qq = { "pmuludq", "pmuludq", Pq, Qq, XX, XX, IA_SSE2 },
|
||||
Ia_pmuludq_Vdq_Wdq = { "pmuludq", "pmuludq", Vdq, Wdq, XX, XX, IA_SSE2 },
|
||||
Ia_popal = { "popad", "popal", XX, XX, XX, XX, 0 },
|
||||
Ia_popal = { "popa", "popal", XX, XX, XX, XX, 0 },
|
||||
Ia_popaw = { "popa", "popa", XX, XX, XX, XX, 0 },
|
||||
Ia_popcnt_Gd_Ed = { "popcnt", "popcnt", Gd, Ed, XX, XX, IA_POPCNT },
|
||||
Ia_popcnt_Gq_Eq = { "popcnt", "popcnt", Gq, Eq, XX, XX, IA_POPCNT },
|
||||
Ia_popcnt_Gw_Ew = { "popcnt", "popcnt", Gw, Ew, XX, XX, IA_POPCNT },
|
||||
Ia_popfl = { "popfd", "popfl", XX, XX, XX, XX, 0 },
|
||||
Ia_popfq = { "popfq", "popfq", XX, XX, XX, XX, 0 },
|
||||
Ia_popfl = { "popf", "popfl", XX, XX, XX, XX, 0 },
|
||||
Ia_popfq = { "popf", "popfq", XX, XX, XX, XX, 0 },
|
||||
Ia_popfw = { "popf", "popf", XX, XX, XX, XX, 0 },
|
||||
Ia_popl_DS = { "pop", "popl", DS, XX, XX, XX, 0 },
|
||||
Ia_popl_Ed = { "pop", "popl", Ed, XX, XX, XX, 0 },
|
||||
@ -1070,7 +1070,7 @@ Ia_punpckldq_Vdq_Wdq = { "punpckldq", "punpckldq", Vdq, Wdq, XX, XX, IA_SSE2 },
|
||||
Ia_punpcklqdq_Vdq_Wdq = { "punpcklqdq", "punpcklqdq", Vdq, Wdq, XX, XX, IA_SSE2 },
|
||||
Ia_punpcklwd_Pq_Qd = { "punpcklwd", "punpcklwd", Pq, Qd, XX, XX, IA_MMX },
|
||||
Ia_punpcklwd_Vdq_Wdq = { "punpcklwd", "punpcklwd", Vdq, Wdq, XX, XX, IA_SSE2 },
|
||||
Ia_pushal = { "pushad", "pushal", XX, XX, XX, XX, 0 },
|
||||
Ia_pushal = { "pusha", "pushal", XX, XX, XX, XX, 0 },
|
||||
Ia_pushaw = { "pusha", "pusha", XX, XX, XX, XX, 0 },
|
||||
Ia_pushfl = { "pushf", "pushfl", XX, XX, XX, XX, 0 },
|
||||
Ia_pushfq = { "pushf", "pushfq", XX, XX, XX, XX, 0 },
|
||||
@ -1209,10 +1209,10 @@ Ia_sbbw_Ew_Gw = { "sbb", "sbbw", Ew, Gw, XX, XX, 0 },
|
||||
Ia_sbbw_Ew_Iw = { "sbb", "sbbw", Ew, Iw, XX, XX, 0 },
|
||||
Ia_sbbw_Ew_sIb = { "sbb", "sbbw", Ew, sIbw, XX, XX, 0 },
|
||||
Ia_sbbw_Gw_Ew = { "sbb", "sbbw", Gw, Ew, XX, XX, 0 },
|
||||
Ia_scasb_Yb_AL = { "scasb", "scasb", Yb, AL_Reg, XX, XX, 0 },
|
||||
Ia_scasl_Yd_EAX = { "scasd", "scasl", Yd, EAX_Reg, XX, XX, 0 },
|
||||
Ia_scasq_Yq_RAX = { "scasq", "scasq", Yq, RAX_Reg, XX, XX, 0 },
|
||||
Ia_scasw_Yw_AX = { "scasw", "scasw", Yw, AX_Reg, XX, XX, 0 },
|
||||
Ia_scasb_AL_Yb = { "scasb", "scasb", AL_Reg, Yb, XX, XX, 0 },
|
||||
Ia_scasl_EAX_Yd = { "scasd", "scasl", EAX_Reg, Yd, XX, XX, 0 },
|
||||
Ia_scasq_RAX_Yq = { "scasq", "scasq", RAX_Reg, Yq, XX, XX, 0 },
|
||||
Ia_scasw_AX_Yw = { "scasw", "scasw", AX_Reg, Yw, XX, XX, 0 },
|
||||
Ia_setb_Eb = { "setb", "setb", Eb, XX, XX, XX, 0 },
|
||||
Ia_setbe_Eb = { "setbe", "setbe", Eb, XX, XX, XX, 0 },
|
||||
Ia_setl_Eb = { "setl", "setl", Eb, XX, XX, XX, 0 },
|
||||
@ -1338,9 +1338,9 @@ Ia_testq_RAX_sId = { "test", "testq", RAX_Reg, sIdq, XX, XX, 0 },
|
||||
Ia_testw_AX_Iw = { "test", "testw", AX_Reg, Iw, XX, XX, 0 },
|
||||
Ia_testw_Ew_Gw = { "test", "testw", Ew, Gw, XX, XX, 0 },
|
||||
Ia_testw_Ew_Iw = { "test", "testw", Ew, Iw, XX, XX, 0 },
|
||||
Ia_tzcntl_Gd_Ed = { "tzcntl", "tzcntl", Gd, Ed, XX, XX, IA_BMI1 },
|
||||
Ia_tzcntq_Gq_Eq = { "tzcntq", "tzcntq", Gq, Eq, XX, XX, IA_BMI1 },
|
||||
Ia_tzcntw_Gw_Ew = { "tzcntw", "tzcntw", Gw, Ew, XX, XX, IA_BMI1 },
|
||||
Ia_tzcntl_Gd_Ed = { "tzcnt", "tzcntl", Gd, Ed, XX, XX, IA_BMI1 },
|
||||
Ia_tzcntq_Gq_Eq = { "tzcnt", "tzcntq", Gq, Eq, XX, XX, IA_BMI1 },
|
||||
Ia_tzcntw_Gw_Ew = { "tzcnt", "tzcntw", Gw, Ew, XX, XX, IA_BMI1 },
|
||||
Ia_tzmsk_By_Ey = { "tzmsk", "tzmsk", Gy, By, Ey, XX, IA_TBM },
|
||||
Ia_ucomisd_Vsd_Wsd = { "ucomisd", "ucomisd", Vsd, Wsd, XX, XX, IA_SSE2 },
|
||||
Ia_ucomiss_Vss_Wss = { "ucomiss", "ucomiss", Vss, Wss, XX, XX, IA_SSE },
|
||||
|
||||
@ -67,8 +67,8 @@ static const char *intel_index16[8] = {
|
||||
"bx"
|
||||
};
|
||||
|
||||
static const char *intel_vector_reg_name[2] = {
|
||||
"xmm", "ymm"
|
||||
static const char *intel_vector_reg_name[3] = {
|
||||
"xmm", "ymm", "zmm"
|
||||
};
|
||||
|
||||
//////////////////
|
||||
@ -114,8 +114,8 @@ static const char *att_index16[8] = {
|
||||
"%bx"
|
||||
};
|
||||
|
||||
static const char *att_vector_reg_name[2] = {
|
||||
"%xmm", "%ymm"
|
||||
static const char *att_vector_reg_name[3] = {
|
||||
"%xmm", "%ymm", "%zmm"
|
||||
};
|
||||
|
||||
#define NULL_SEGMENT_REGISTER 7
|
||||
|
||||
Loading…
Reference in New Issue
Block a user