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Implemented VPMOVSX*/VPMOVZX* AVX-512 instructions

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Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 26 VGETMANTPS
512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
NDS.LIG.66.0F3A.W1 27 VGETMANTSD
This commit is contained in:
Stanislav Shwartsman 2014-02-02 19:56:08 +00:00
parent 55e1d53a48
commit ac06ee46ae
6 changed files with 991 additions and 695 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

252
bochs/cpu/avx2.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011-2013 Stanislav Shwartsman
// Copyright (c) 2011-2014 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -361,207 +361,159 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTQ_VdqWqR(bxInstruction_
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBW256_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBW_VdqWdqR(bxInstruction_c *i)
{
BxPackedYmmRegister op = BX_READ_YMM_REG(i->src());
BxPackedAvxRegister result;
unsigned len = i->getVL();
for (unsigned n=0; n < WORD_ELEMENTS(len); n++)
result.vmm16s(n) = (Bit16s) op.ymmsbyte(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBD_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedYmmRegister result;
BxPackedAvxRegister result;
unsigned len = i->getVL();
for (int n=0; n<16; n++)
result.ymm16u(n) = (Bit8s) op.xmmsbyte(n);
BX_WRITE_YMM_REGZ(i->dst(), result);
for (unsigned n=0; n < DWORD_ELEMENTS(len); n++)
result.vmm32s(n) = (Bit32s) op.xmmsbyte(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBD256_VdqWqR(bxInstruction_c *i)
{
BxPackedYmmRegister result;
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.ymm32u(0) = (Bit8s) MMXSB0(op);
result.ymm32u(1) = (Bit8s) MMXSB1(op);
result.ymm32u(2) = (Bit8s) MMXSB2(op);
result.ymm32u(3) = (Bit8s) MMXSB3(op);
result.ymm32u(4) = (Bit8s) MMXSB4(op);
result.ymm32u(5) = (Bit8s) MMXSB5(op);
result.ymm32u(6) = (Bit8s) MMXSB6(op);
result.ymm32u(7) = (Bit8s) MMXSB7(op);
BX_WRITE_YMM_REGZ(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBQ256_VdqWdR(bxInstruction_c *i)
{
BxPackedYmmRegister result;
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->src());
result.ymm64u(0) = (Bit8s) (val32 & 0xFF);
result.ymm64u(1) = (Bit8s) ((val32 >> 8) & 0xFF);
result.ymm64u(2) = (Bit8s) ((val32 >> 16) & 0xFF);
result.ymm64u(3) = (Bit8s) (val32 >> 24);
BX_WRITE_YMM_REGZ(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXWD256_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXBQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedYmmRegister result;
BxPackedAvxRegister result;
unsigned len = i->getVL();
result.ymm32u(0) = op.xmm16s(0);
result.ymm32u(1) = op.xmm16s(1);
result.ymm32u(2) = op.xmm16s(2);
result.ymm32u(3) = op.xmm16s(3);
result.ymm32u(4) = op.xmm16s(4);
result.ymm32u(5) = op.xmm16s(5);
result.ymm32u(6) = op.xmm16s(6);
result.ymm32u(7) = op.xmm16s(7);
BX_WRITE_YMM_REGZ(i->dst(), result);
for (unsigned n=0; n < QWORD_ELEMENTS(len); n++)
result.vmm64s(n) = (Bit64s) op.xmmsbyte(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXWQ256_VdqWqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXWD_VdqWdqR(bxInstruction_c *i)
{
BxPackedYmmRegister result;
BxPackedMmxRegister op;
BxPackedYmmRegister op = BX_READ_YMM_REG(i->src());
BxPackedAvxRegister result;
unsigned len = i->getVL();
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.ymm64u(0) = MMXSW0(op);
result.ymm64u(1) = MMXSW1(op);
result.ymm64u(2) = MMXSW2(op);
result.ymm64u(3) = MMXSW3(op);
BX_WRITE_YMM_REGZ(i->dst(), result);
for (unsigned n=0; n < DWORD_ELEMENTS(len); n++)
result.vmm32s(n) = (Bit32s) op.ymm16s(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXDQ256_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXWQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedYmmRegister result;
BxPackedAvxRegister result;
unsigned len = i->getVL();
result.ymm64u(0) = op.xmm32s(0);
result.ymm64u(1) = op.xmm32s(1);
result.ymm64u(2) = op.xmm32s(2);
result.ymm64u(3) = op.xmm32s(3);
BX_WRITE_YMM_REGZ(i->dst(), result);
for (unsigned n=0; n < QWORD_ELEMENTS(len); n++)
result.vmm64s(n) = (Bit64s) op.xmm16s(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBW256_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVSXDQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedYmmRegister op = BX_READ_YMM_REG(i->src());
BxPackedAvxRegister result;
unsigned len = i->getVL();
for (unsigned n=0; n < QWORD_ELEMENTS(len); n++)
result.vmm64s(n) = (Bit64s) op.ymm32s(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBW_VdqWdqR(bxInstruction_c *i)
{
BxPackedYmmRegister op = BX_READ_YMM_REG(i->src());
BxPackedAvxRegister result;
unsigned len = i->getVL();
for (unsigned n=0; n < WORD_ELEMENTS(len); n++)
result.vmm16u(n) = (Bit16u) op.ymmubyte(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBD_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedYmmRegister result;
BxPackedAvxRegister result;
unsigned len = i->getVL();
for (int n=0; n<16; n++)
result.ymm16u(n) = op.xmmubyte(n);
BX_WRITE_YMM_REGZ(i->dst(), result);
for (unsigned n=0; n < DWORD_ELEMENTS(len); n++)
result.vmm32u(n) = (Bit32u) op.xmmubyte(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBD256_VdqWqR(bxInstruction_c *i)
{
BxPackedYmmRegister result;
BxPackedMmxRegister op;
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.ymm32u(0) = MMXUB0(op);
result.ymm32u(1) = MMXUB1(op);
result.ymm32u(2) = MMXUB2(op);
result.ymm32u(3) = MMXUB3(op);
result.ymm32u(4) = MMXUB4(op);
result.ymm32u(5) = MMXUB5(op);
result.ymm32u(6) = MMXUB6(op);
result.ymm32u(7) = MMXUB7(op);
BX_WRITE_YMM_REGZ(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBQ256_VdqWdR(bxInstruction_c *i)
{
BxPackedYmmRegister result;
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->src());
result.ymm64u(0) = (Bit8u) (val32 & 0xFF);
result.ymm64u(1) = (Bit8u) ((val32 >> 8) & 0xFF);
result.ymm64u(2) = (Bit8u) ((val32 >> 16) & 0xFF);
result.ymm64u(3) = (Bit8u) (val32 >> 24);
BX_WRITE_YMM_REGZ(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXWD256_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXBQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedYmmRegister result;
BxPackedAvxRegister result;
unsigned len = i->getVL();
result.ymm32u(0) = op.xmm16u(0);
result.ymm32u(1) = op.xmm16u(1);
result.ymm32u(2) = op.xmm16u(2);
result.ymm32u(3) = op.xmm16u(3);
result.ymm32u(4) = op.xmm16u(4);
result.ymm32u(5) = op.xmm16u(5);
result.ymm32u(6) = op.xmm16u(6);
result.ymm32u(7) = op.xmm16u(7);
BX_WRITE_YMM_REGZ(i->dst(), result);
for (unsigned n=0; n < QWORD_ELEMENTS(len); n++)
result.vmm64u(n) = (Bit64u) op.xmmubyte(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXWQ256_VdqWqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXWD_VdqWdqR(bxInstruction_c *i)
{
BxPackedYmmRegister result;
BxPackedMmxRegister op;
BxPackedYmmRegister op = BX_READ_YMM_REG(i->src());
BxPackedAvxRegister result;
unsigned len = i->getVL();
// use MMX register as 64-bit value with convinient accessors
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());
result.ymm64u(0) = MMXUW0(op);
result.ymm64u(1) = MMXUW1(op);
result.ymm64u(2) = MMXUW2(op);
result.ymm64u(3) = MMXUW3(op);
BX_WRITE_YMM_REGZ(i->dst(), result);
for (unsigned n=0; n < DWORD_ELEMENTS(len); n++)
result.vmm32u(n) = (Bit32u) op.ymm16u(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXDQ256_VdqWdqR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXWQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
BxPackedYmmRegister result;
BxPackedAvxRegister result;
unsigned len = i->getVL();
result.ymm64u(0) = op.xmm32u(0);
result.ymm64u(1) = op.xmm32u(1);
result.ymm64u(2) = op.xmm32u(2);
result.ymm64u(3) = op.xmm32u(3);
for (unsigned n=0; n < QWORD_ELEMENTS(len); n++)
result.vmm64u(n) = (Bit64u) op.xmm16u(n);
BX_WRITE_YMM_REGZ(i->dst(), result);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVZXDQ_VdqWdqR(bxInstruction_c *i)
{
BxPackedYmmRegister op = BX_READ_YMM_REG(i->src());
BxPackedAvxRegister result;
unsigned len = i->getVL();
for (unsigned n=0; n < QWORD_ELEMENTS(len); n++)
result.vmm64u(n) = (Bit64u) op.ymm32u(n);
BX_WRITE_AVX_REGZ(i->dst(), result, len);
BX_NEXT_INSTR(i);
}

1134
bochs/cpu/avx512_move.cc
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File diff suppressed because it is too large Load Diff

39
bochs/cpu/cpu.h
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@ -2133,6 +2133,8 @@ public: // for now...
#if BX_SUPPORT_AVX
BX_SMF BX_INSF_TYPE LOAD_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOAD_Half_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOAD_Quarter_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOAD_Oct_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
#if BX_SUPPORT_EVEX
BX_SMF BX_INSF_TYPE LOAD_BROADCAST_VectorD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -3002,18 +3004,19 @@ public: // for now...
BX_SMF BX_INSF_TYPE VPSLLDQ_UdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPALIGNR_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBW256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBD256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBQ256_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXWD256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXWQ256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXDQ256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBW256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBD256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBQ256_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXWD256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXWQ256_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXDQ256_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXWD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXWQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXWD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXWQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPERMD_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPERMQ_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -3545,6 +3548,18 @@ public: // for now...
BX_SMF BX_INSF_TYPE VPMOVSDW_MASK_WdqVdqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSQW_MASK_WdqVdqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSQD_MASK_WdqVdqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBD_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXBQ_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXWD_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXWQ_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVSXDQ_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBD_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXBQ_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXWD_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXWQ_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPMOVZXDQ_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
BX_SMF BX_INSF_TYPE LZCNT_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);

160
bochs/cpu/fetchdecode_evex.h
View File

@ -446,12 +446,132 @@ static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3815_Mask[3] = {
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3821[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVSXBD_VdqWdq },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVSDB_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3821_Mask[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVSXBD_VdqWdq_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVSDB_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3822[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVSXBQ_VdqWdq },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVSQB_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3822_Mask[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVSXBQ_VdqWdq_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVSQB_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3823[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVSXWD_VdqWdq },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVSDW_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3823_Mask[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVSXWQ_VdqWdq_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVSDW_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3824[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVSXWQ_VdqWdq },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVSQW_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3824_Mask[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVSXWD_VdqWdq_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVSQW_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3825[3] = {
/* 66 */ { BxVexW0, BX_IA_V512_VPMOVSXDQ_VdqWdq },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVSQD_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3825_Mask[3] = {
/* 66 */ { BxVexW0, BX_IA_V512_VPMOVSXDQ_VdqWdq_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVSQD_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3827[3] = {
/* 66 */ { BxAliasVexW, BX_IA_V512_VPTESTMD_KGwHdqWdq },
/* F3 */ { BxAliasVexW, BX_IA_V512_VPTESTNMD_KGwHdqWdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3831[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVZXBD_VdqWdq },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVDB_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3831_Mask[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVZXBD_VdqWdq_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVDB_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3832[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVZXBQ_VdqWdq },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVQB_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3832_Mask[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVZXBQ_VdqWdq_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVQB_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3833[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVZXWD_VdqWdq },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVDW_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3833_Mask[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVZXWQ_VdqWdq_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVDW_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3834[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVZXWQ_VdqWdq },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVQW_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3834_Mask[3] = {
/* 66 */ { 0, BX_IA_V512_VPMOVZXWD_VdqWdq_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVQW_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3835[3] = {
/* 66 */ { BxVexW0, BX_IA_V512_VPMOVZXDQ_VdqWdq },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVQD_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f3835_Mask[3] = {
/* 66 */ { BxVexW0, BX_IA_V512_VPMOVZXDQ_VdqWdq_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VPMOVQD_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
/* ************************************************************************ */
/* ******** */
@ -1090,16 +1210,16 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 1F */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPABSQ_VdqWdq_Kmask },
/* 20 k0 */ { 0, BX_IA_ERROR },
/* 20 */ { 0, BX_IA_ERROR },
/* 21 k0 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVSDB_WdqVdq },
/* 21 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVSDB_WdqVdq_Kmask },
/* 22 k0 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVSQB_WdqVdq },
/* 22 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVSQB_WdqVdq_Kmask },
/* 23 k0 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVSDW_WdqVdq },
/* 23 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVSDW_WdqVdq_Kmask },
/* 24 k0 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVSQW_WdqVdq },
/* 24 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVSQW_WdqVdq_Kmask },
/* 25 k0 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVSQD_WdqVdq },
/* 25 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVSQD_WdqVdq_Kmask },
/* 21 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3821 },
/* 21 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3821_Mask },
/* 22 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3822 },
/* 22 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3822_Mask },
/* 23 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3823 },
/* 23 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3823_Mask },
/* 24 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3824 },
/* 24 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3824_Mask },
/* 25 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3825 },
/* 25 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3825_Mask },
/* 26 k0 */ { 0, BX_IA_ERROR },
/* 26 */ { 0, BX_IA_ERROR },
/* 27 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3827 },
@ -1122,16 +1242,16 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 2F */ { 0, BX_IA_ERROR },
/* 30 k0 */ { 0, BX_IA_ERROR },
/* 30 */ { 0, BX_IA_ERROR },
/* 31 k0 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVDB_WdqVdq },
/* 31 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVDB_WdqVdq_Kmask },
/* 32 k0 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVQB_WdqVdq },
/* 32 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVQB_WdqVdq_Kmask },
/* 33 k0 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVDW_WdqVdq },
/* 33 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVDW_WdqVdq_Kmask },
/* 34 k0 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVQW_WdqVdq },
/* 34 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVQW_WdqVdq_Kmask },
/* 35 k0 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVQD_WdqVdq },
/* 35 */ { BxVexW0 | BxPrefixSSEF3, BX_IA_V512_VPMOVQD_WdqVdq_Kmask },
/* 31 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3831 },
/* 31 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3831_Mask },
/* 32 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3832 },
/* 32 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3832_Mask },
/* 33 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3833 },
/* 33 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3833_Mask },
/* 34 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3834 },
/* 34 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3834_Mask },
/* 35 k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3835 },
/* 35 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f3835_Mask },
/* 36 k0 */ { BxAliasVexW | BxPrefixSSE66 | BxVexL1, BX_IA_V512_VPERMD_VdqHdqWdq_Kmask },
/* 36 */ { BxAliasVexW | BxPrefixSSE66 | BxVexL1, BX_IA_V512_VPERMD_VdqHdqWdq_Kmask },
/* 37 k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPCMPGTQ_KGbHdqWdq },

48
bochs/cpu/ia_opcodes.h
View File

@ -2089,18 +2089,18 @@ bx_define_opcode(BX_IA_VMOVQ_VqWq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VqW
bx_define_opcode(BX_IA_VCVTPH2PS_VpsWps, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_ISA_AVX_F16C, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, BX_ISA_AVX_F16C, OP_Wps, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXBW256_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXBD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXBD256_VdqWqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXBQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVSXBQ256_VdqWdR, BX_ISA_AVX2, OP_Vdq, OP_Wd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXWD256_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXWQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXWQ256_VdqWqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXDQ256_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXBW256_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXBD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXBD256_VdqWqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXBQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVZXBQ256_VdqWdR, BX_ISA_AVX2, OP_Vdq, OP_Wd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXWD256_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXWQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXWQ256_VdqWqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXDQ256_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXBW_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXBD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXBD_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXBQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVSXBQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXWD_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXWQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXWQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXDQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXBW_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXBD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXBD_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXBQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVZXBQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXWD_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXWQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXWQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXDQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPERM2I128_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqHdqWdqIbR, BX_ISA_AVX2, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VINSERTI128_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX2, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_AVX)
@ -2789,6 +2789,30 @@ bx_define_opcode(BX_IA_V512_VPMOVSDW_WdqVdq_Kmask, &BX_CPU_C::VPMOVSDW_MASK_WdqV
bx_define_opcode(BX_IA_V512_VPMOVSQW_WdqVdq_Kmask, &BX_CPU_C::VPMOVSQW_MASK_WdqVdqM, &BX_CPU_C::VPMOVSQW_MASK_WdqVdqR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSQD_WdqVdq_Kmask, &BX_CPU_C::VPMOVSQD_MASK_WdqVdqM, &BX_CPU_C::VPMOVSQD_MASK_WdqVdqR, BX_ISA_AVX512, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSXBD_VdqWdq, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVSXBD_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSXBQ_VdqWdq, &BX_CPU_C::LOAD_Oct_Vector, &BX_CPU_C::VPMOVSXBQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSXWD_VdqWdq, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVSXWD_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSXWQ_VdqWdq, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVSXWQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSXDQ_VdqWdq, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVSXDQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVZXBD_VdqWdq, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVZXBD_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVZXBQ_VdqWdq, &BX_CPU_C::LOAD_Oct_Vector, &BX_CPU_C::VPMOVZXBQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVZXWD_VdqWdq, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXWD_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVZXWQ_VdqWdq, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVZXWQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVZXDQ_VdqWdq, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXDQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSXBD_VdqWdq_Kmask, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVSXBD_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSXBQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Oct_Vector, &BX_CPU_C::VPMOVSXBQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSXWD_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVSXWD_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSXWQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVSXWQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVSXDQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVSXDQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVZXBD_VdqWdq_Kmask, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVZXBD_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVZXBQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Oct_Vector, &BX_CPU_C::VPMOVZXBQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVZXWD_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXWD_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVZXWQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVZXWQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVZXDQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXDQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
// VexW alias
bx_define_opcode(BX_IA_V512_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE)
bx_define_opcode(BX_IA_V512_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE)

53
bochs/cpu/load.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2013 Stanislav Shwartsman
// Copyright (c) 2008-2014 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -171,6 +171,57 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Half_Vector(bxInstruction_c *
BX_CPU_CALL_METHOD(i->execute2(), (i));
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Quarter_Vector(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
unsigned vl = i->getVL();
#if BX_SUPPORT_EVEX
if (vl == BX_VL512) {
read_virtual_xmmword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_VECTOR_TMP_REGISTER));
}
else
#endif
{
if (vl == BX_VL256) {
Bit64u val_64 = read_virtual_qword(i->seg(), eaddr);
BX_WRITE_XMM_REG_LO_QWORD(BX_VECTOR_TMP_REGISTER, val_64);
}
else {
Bit32u val_32 = read_virtual_dword(i->seg(), eaddr);
BX_WRITE_XMM_REG_LO_DWORD(BX_VECTOR_TMP_REGISTER, val_32);
}
}
BX_CPU_CALL_METHOD(i->execute2(), (i));
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Oct_Vector(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
unsigned vl = i->getVL();
#if BX_SUPPORT_EVEX
if (vl == BX_VL512) {
Bit64u val_64 = read_virtual_qword(i->seg(), eaddr);
BX_WRITE_XMM_REG_LO_QWORD(BX_VECTOR_TMP_REGISTER, val_64);
}
else
#endif
{
if (vl == BX_VL256) {
Bit32u val_32 = read_virtual_dword(i->seg(), eaddr);
BX_WRITE_XMM_REG_LO_DWORD(BX_VECTOR_TMP_REGISTER, val_32);
}
else {
Bit16u val_16 = read_virtual_word(i->seg(), eaddr);
BX_WRITE_XMM_REG_LO_WORD(BX_VECTOR_TMP_REGISTER, val_16);
}
}
BX_CPU_CALL_METHOD(i->execute2(), (i));
}
#endif
#if BX_SUPPORT_EVEX