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Implemented VEXTRACT* AVX512DQ instructions

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The only missing AVX512BW/AVX512DQ opcodes are now:

"512.66.0F38.W1 10 VPSRLVW"
"512.66.0F38.W1 11 VPSRAVW"
"512.66.0F38.W1 12 VPSLLVW"

"512.F3.0F38.W0 28 VPMOVM2B
 512.F3.0F38.W1 28 VPMOVM2W"
"512.F3.0F38.W0 29 VPMOVB2M
 512.F3.0F38.W1 29 VPMOVW2M"

"512.F3.0F38.W0 38 VPMOVM2D
 512.F3.0F38.W1 38 VPMOVM2Q"
"512.F3.0F38.W0 39 VPMOVD2M
 512.F3.0F38.W1 39 VPMOVQ2M"

"NDS.512.66.0F38.WIG 38 VPMINSB"
"NDS.512.66.0F38.WIG 3A VPMINUW"

"W1.NDS.512.66.0F38 40 VPMULLQ"

"512.66.0F3A.W1 0F VPALIGNR"
"NDS.66.0F3A.W0 42 VDBPSADBW"

"NDS.512.66.0F3A.W0 50 VRANGEPS
 NDS.512.66.0F3A.W1 50 VRANGEPD"
"NDS.512.66.0F3A.W0 51 VRANGESS
 NDS.512.66.0F3A.W1 51 VRANGESD"

"NDS.512.66.0F3A.W0 56 VREDUCEPS
 NDS.512.66.0F3A.W1 56 VREDUCEPD"
"NDS.512.66.0F3A.W0 57 VREDUCESS
 NDS.512.66.0F3A.W1 57 VREDUCESD"
This commit is contained in:
Stanislav Shwartsman 2014-07-20 20:46:48 +00:00
parent 8108da227d
commit 009629f4d9
5 changed files with 152 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
bochs/cpu/avx.cc
View File

@ -488,32 +488,32 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDVB_VdqHdqWdqIbR(bxInstructi
/* Opcode: VEX.66.0F.3A 18 (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF128_VdqHdqWdqIbR(bxInstruction_c *i)
{
BxPackedYmmRegister op1 = BX_READ_YMM_REG(i->src1());
op1.ymm128(i->Ib() & 0x1) = BX_READ_XMM_REG(i->src2());
BX_WRITE_YMM_REGZ(i->dst(), op1);
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src1());
unsigned len = i->getVL();
unsigned offset = i->Ib() & (len-1);
op.vmm128(offset) = BX_READ_XMM_REG(i->src2());
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
/* Opcode: VEX.66.0F.3A 19 (VEX.W=0, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF128_WdqVdqIbM(bxInstruction_c *i)
{
BxPackedYmmRegister op = BX_READ_YMM_REG(i->src());
unsigned len = i->getVL(), offset = i->Ib() & (len - 1);
BxPackedXmmRegister op = BX_READ_AVX_REG_LANE(i->src(), offset);
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_xmmword(i->seg(), eaddr, &(op.ymm128(i->Ib() & 1)));
write_virtual_xmmword(i->seg(), eaddr, &op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF128_WdqVdqIbR(bxInstruction_c *i)
{
BxPackedYmmRegister op = BX_READ_YMM_REG(i->src());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op.ymm128(i->Ib() & 1));
unsigned len = i->getVL(), offset = i->Ib() & (len - 1);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), BX_READ_AVX_REG_LANE(i->src(), offset));
BX_NEXT_INSTR(i);
}

139
bochs/cpu/avx512.cc
View File

@ -1120,41 +1120,28 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMPD_MASK_VpdHpdWpdR(bxInstruct
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF32x4_MASK_VpsHpsWpsIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src1());
unsigned len = i->getVL();
unsigned offset = i->Ib() & (len-1);
op1.vmm128(offset) = BX_READ_XMM_REG(i->src2());
if (i->opmask()) {
avx512_write_regd_masked(i, &op1, len, BX_READ_16BIT_OPMASK(i->opmask()));
}
else {
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
}
op.vmm128(offset) = BX_READ_XMM_REG(i->src2());
avx512_write_regd_masked(i, &op, len, BX_READ_16BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF64x2_MASK_VpdHpdWpdIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src1());
unsigned len = i->getVL();
unsigned offset = i->Ib() & (len-1);
op1.vmm128(offset) = BX_READ_XMM_REG(i->src2());
if (i->opmask()) {
avx512_write_regq_masked(i, &op1, len, BX_READ_8BIT_OPMASK(i->opmask()));
}
else {
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
}
op.vmm128(offset) = BX_READ_XMM_REG(i->src2());
avx512_write_regq_masked(i, &op, len, BX_READ_8BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF32x8_MASK_VpsHpsWpsIbR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF64x4_VpdHpdWpdIbR(bxInstruction_c *i)
{
unsigned len = i->getVL();
if (len != BX_VL512) {
@ -1162,16 +1149,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF32x8_MASK_VpsHpsWpsIbR(bxI
exception(BX_UD_EXCEPTION, 0);
}
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
op1.vmm256(i->Ib() & 0x1) = BX_READ_YMM_REG(i->src2());
if (i->opmask()) {
avx512_write_regd_masked(i, &op1, len, BX_READ_16BIT_OPMASK(i->opmask()));
}
else {
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
}
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src1());
op.vmm256(i->Ib() & 0x1) = BX_READ_YMM_REG(i->src2());
BX_WRITE_AVX_REGZ(i->dst(), op, len);
BX_NEXT_INSTR(i);
}
@ -1184,25 +1164,24 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF64x4_MASK_VpdHpdWpdIbR(bxI
exception(BX_UD_EXCEPTION, 0);
}
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
op1.vmm256(i->Ib() & 0x1) = BX_READ_YMM_REG(i->src2());
if (i->opmask()) {
avx512_write_regq_masked(i, &op1, len, BX_READ_8BIT_OPMASK(i->opmask()));
}
else {
BX_WRITE_AVX_REGZ(i->dst(), op1, len);
}
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src1());
op.vmm256(i->Ib() & 0x1) = BX_READ_YMM_REG(i->src2());
avx512_write_regq_masked(i, &op, len, BX_READ_8BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF32x4_WpsVpsIbR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF32x8_MASK_VpsHpsWpsIbR(bxInstruction_c *i)
{
unsigned len = i->getVL(), offset = i->Ib() & (len - 1);
unsigned len = i->getVL();
if (len != BX_VL512) {
BX_ERROR(("%s: vector length must be 512 bit", i->getIaOpcodeNameShort()));
exception(BX_UD_EXCEPTION, 0);
}
BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), BX_READ_AVX_REG_LANE(i->src(), offset));
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src1());
op.vmm256(i->Ib() & 0x1) = BX_READ_YMM_REG(i->src2());
avx512_write_regd_masked(i, &op, len, BX_READ_16BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
@ -1223,17 +1202,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbR(bxIns
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF32x4_WpsVpsIbM(bxInstruction_c *i)
{
unsigned len = i->getVL(), offset = i->Ib() & (len - 1);
BxPackedXmmRegister op = BX_READ_AVX_REG_LANE(i->src(), offset);
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_xmmword(i->seg(), eaddr, &op);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbM(bxInstruction_c *i)
{
unsigned len = i->getVL(), offset = i->Ib() & (len - 1);
@ -1247,6 +1215,35 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbM(bxIns
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF64x2_MASK_WpdVpdIbR(bxInstruction_c *i)
{
unsigned len = i->getVL(), offset = i->Ib() & (len - 1);
BxPackedXmmRegister op = BX_READ_AVX_REG_LANE(i->src(), offset);
Bit32u mask = BX_READ_8BIT_OPMASK(i->opmask());
if (i->isZeroMasking())
xmm_zero_blendpd(&BX_READ_XMM_REG(i->dst()), &op, mask);
else
xmm_blendpd(&BX_READ_XMM_REG(i->dst()), &op, mask);
BX_CLEAR_AVX_HIGH128(i->dst());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF64x2_MASK_WpdVpdIbM(bxInstruction_c *i)
{
unsigned len = i->getVL(), offset = i->Ib() & (len - 1);
BxPackedAvxRegister op;
op.vmm128(0) = BX_READ_AVX_REG_LANE(i->src(), offset);
Bit32u opmask = BX_READ_8BIT_OPMASK(i->opmask()) & 0x3;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
avx_masked_store64(i, eaddr, &op, opmask);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF64x4_WpdVpdIbR(bxInstruction_c *i)
{
unsigned len = i->getVL();
@ -1309,6 +1306,40 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF64x4_MASK_WpdVpdIbM(bxIns
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF32x8_MASK_WpsVpsIbR(bxInstruction_c *i)
{
unsigned len = i->getVL();
if (len != BX_VL512) {
BX_ERROR(("%s: vector length must be 512 bit", i->getIaOpcodeNameShort()));
exception(BX_UD_EXCEPTION, 0);
}
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
if (i->Ib() & 0x1)
op.vmm256(0) = op.vmm256(1);
avx512_write_regd_masked(i, &op, BX_VL256, BX_READ_8BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF32x8_MASK_WpsVpsIbM(bxInstruction_c *i)
{
unsigned len = i->getVL();
if (len != BX_VL512) {
BX_ERROR(("%s: vector length must be 512 bit", i->getIaOpcodeNameShort()));
exception(BX_UD_EXCEPTION, 0);
}
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
if (i->Ib() & 0x1)
op.vmm256(0) = op.vmm256(1);
Bit32u opmask = BX_READ_8BIT_OPMASK(i->opmask());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
avx_masked_store32(i, eaddr, &op, opmask);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVDDUP_MASK_VpdWpdR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());

16
bochs/cpu/cpu.h
View File

@ -3657,19 +3657,23 @@ public: // for now...
BX_SMF BX_INSF_TYPE VINSERTF32x4_MASK_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VINSERTF64x2_MASK_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VINSERTF32x8_MASK_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VINSERTF64x4_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VINSERTF64x4_MASK_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VINSERTF32x8_MASK_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF32x4_WpsVpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF32x4_MASK_WpsVpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF64x4_WpdVpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF64x4_MASK_WpdVpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF32x4_WpsVpsIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF32x4_MASK_WpsVpsIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF64x4_WpdVpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF64x4_WpdVpdIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF64x4_MASK_WpdVpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF64x4_MASK_WpdVpdIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF32x8_MASK_WpsVpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF32x8_MASK_WpsVpsIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF64x2_MASK_WpdVpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VEXTRACTF64x2_MASK_WpdVpdIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPBROADCASTB_MASK_VdqWbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPBROADCASTW_MASK_VdqWwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPBROADCASTD_MASK_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);

24
bochs/cpu/fetchdecode_evex.h
View File

@ -1842,14 +1842,14 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 16 */ { 0, BX_IA_ERROR }, // #UD
/* 17 k0 */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib, BX_IA_V512_VEXTRACTPS_EdVpsIb },
/* 17 */ { 0, BX_IA_ERROR }, // #UD
/* 18 k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb_Kmask },
/* 18 k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb },
/* 18 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb_Kmask },
/* 19 k0 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTF32x4_WpsVpsIb },
/* 19 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTF32x4_WpsVpsIb_Kmask },
/* 1A k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF32x8_VpsHpsWpsIb_Kmask },
/* 19 k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTF32x4_WpsVpsIb },
/* 19 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTF32x4_WpsVpsIb_Kmask },
/* 1A k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF32x8_VpsHpsWpsIb },
/* 1A */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF32x8_VpsHpsWpsIb_Kmask },
/* 1B k0 */ { BxVexW1 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTF64x4_WpdVpdIb },
/* 1B */ { BxVexW1 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTF64x4_WpdVpdIb_Kmask },
/* 1B k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTF32x8_WpsVpsIb },
/* 1B */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTF32x8_WpsVpsIb_Kmask },
/* 1C k0 */ { 0, BX_IA_ERROR },
/* 1C */ { 0, BX_IA_ERROR },
/* 1D k0 */ { BxVexW0 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VCVTPS2PH_WpsVpsIb },
@ -1906,14 +1906,14 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 36 */ { 0, BX_IA_ERROR },
/* 37 k0 */ { 0, BX_IA_ERROR },
/* 37 */ { 0, BX_IA_ERROR },
/* 38 k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTI32x4_VdqHdqWdqIb_Kmask },
/* 38 k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTI32x4_VdqHdqWdqIb },
/* 38 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTI32x4_VdqHdqWdqIb_Kmask },
/* 39 k0 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTI32x4_WdqVdqIb },
/* 39 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTI32x4_WdqVdqIb_Kmask },
/* 3A k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTI32x8_VdqHdqWdqIb_Kmask },
/* 39 k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTI32x4_WdqVdqIb },
/* 39 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTI32x4_WdqVdqIb_Kmask },
/* 3A k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTI32x8_VdqHdqWdqIb },
/* 3A */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTI32x8_VdqHdqWdqIb_Kmask },
/* 3B k0 */ { BxVexW1 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTI64x4_WdqVdqIb },
/* 3B */ { BxVexW1 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTI64x4_WdqVdqIb_Kmask },
/* 3B k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTI32x8_WdqVdqIb },
/* 3B */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTI32x8_WdqVdqIb_Kmask },
/* 3C k0 */ { 0, BX_IA_ERROR },
/* 3C */ { 0, BX_IA_ERROR },
/* 3D k0 */ { 0, BX_IA_ERROR },

48
bochs/cpu/ia_opcodes.h
View File

@ -2815,16 +2815,6 @@ bx_define_opcode(BX_IA_V512_VMOVQ_VqWq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOV
bx_define_opcode(BX_IA_V512_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVss, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_ISA_AVX512, OP_Ed, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF32x4_WpsVpsIb, &BX_CPU_C::VEXTRACTF32x4_WpsVpsIbM, &BX_CPU_C::VEXTRACTF32x4_WpsVpsIbR, BX_ISA_AVX512, OP_mVdq128, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF32x4_WpsVpsIb_Kmask, &BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbM, &BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbR, BX_ISA_AVX512, OP_mVdq128, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF64x4_WpdVpdIb, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbR, BX_ISA_AVX512, OP_mVdq256, OP_Vpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF64x4_WpdVpdIb_Kmask, &BX_CPU_C::VEXTRACTF64x4_MASK_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x4_MASK_WpdVpdIbR, BX_ISA_AVX512, OP_mVdq256, OP_Vpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI32x4_WdqVdqIb, &BX_CPU_C::VEXTRACTF32x4_WpsVpsIbM, &BX_CPU_C::VEXTRACTF32x4_WpsVpsIbR, BX_ISA_AVX512, OP_mVdq128, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI32x4_WdqVdqIb_Kmask, &BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbM, &BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbR, BX_ISA_AVX512, OP_mVdq128, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI64x4_WdqVdqIb, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbR, BX_ISA_AVX512, OP_mVdq256, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI64x4_WdqVdqIb_Kmask, &BX_CPU_C::VEXTRACTF64x4_MASK_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x4_MASK_WpdVpdIbR, BX_ISA_AVX512, OP_mVdq256, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMOVLPS_VpsHpsMq, &BX_CPU_C::VMOVLPD_VpdHpdMq, &BX_CPU_C::VMOVHLPS_VpsHpsWps, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVHV, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMOVHPS_VpsHpsMq, &BX_CPU_C::VMOVHPD_VpdHpdMq, &BX_CPU_C::VMOVLHPS_VpsHpsWps, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVHV, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMOVLPS_MqVps, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::BxError, BX_ISA_AVX512, OP_mVHV, OP_Vps, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
@ -2998,16 +2988,46 @@ bx_define_opcode(BX_IA_V512_VPERMT2W_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &B
bx_define_opcode(BX_IA_V512_VPERMI2W_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMI2W_MASK_VdqHdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
// VexW alias
bx_define_opcode(BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF32x4_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTF64x2_VpdHpdWpdIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF64x2_MASK_VpdHpdWpdIbR, BX_ISA_AVX512_DQ, OP_Vpd, OP_Hpd, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTF64x2_VpdHpdWpdIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX512_DQ, OP_Vpd, OP_Hpd, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF32x4_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTF64x2_VpdHpdWpdIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF64x2_MASK_VpdHpdWpdIbR, BX_ISA_AVX512_DQ, OP_Vpd, OP_Hpd, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTF32x8_VpsHpsWpsIb, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VINSERTF64x4_VpdHpdWpdIbR, BX_ISA_AVX512_DQ, OP_Vps, OP_Hps, OP_mVdq256, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTF64x4_VpdHpdWpdIb, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VINSERTF64x4_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVdq256, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTF32x8_VpsHpsWpsIb_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VINSERTF32x8_MASK_VpsHpsWpsIbR, BX_ISA_AVX512_DQ, OP_Vps, OP_Hps, OP_mVdq256, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTF64x4_VpdHpdWpdIb_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VINSERTF64x4_MASK_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_mVdq256, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTI32x4_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF32x4_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTI64x2_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF64x2_MASK_VpdHpdWpdIbR, BX_ISA_AVX512_DQ, OP_Vdq, OP_Hdq, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTI32x4_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTI64x2_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX512_DQ, OP_Vpd, OP_Hpd, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTI32x4_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF32x4_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTI64x2_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF64x2_MASK_VpdHpdWpdIbR, BX_ISA_AVX512_DQ, OP_Vdq, OP_Hdq, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTI32x8_VdqHdqWdqIb, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VINSERTF64x4_VpdHpdWpdIbR, BX_ISA_AVX512_DQ, OP_Vps, OP_Hps, OP_mVdq256, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTI64x4_VdqHdqWdqIb, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VINSERTF64x4_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq256, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTI32x8_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VINSERTF32x8_MASK_VpsHpsWpsIbR, BX_ISA_AVX512_DQ, OP_Vps, OP_Hps, OP_mVdq256, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTI64x4_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VINSERTF64x4_MASK_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_mVdq256, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF32x4_WpsVpsIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_ISA_AVX512, OP_mVdq128, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF64x2_WpdVpdIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_ISA_AVX512_DQ, OP_mVdq128, OP_Vpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF32x4_WpsVpsIb_Kmask, &BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbM, &BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbR, BX_ISA_AVX512, OP_mVdq128, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF64x2_WpdVpdIb_Kmask, &BX_CPU_C::VEXTRACTF64x2_MASK_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x2_MASK_WpdVpdIbR, BX_ISA_AVX512_DQ, OP_mVdq128, OP_Vpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF32x8_WpsVpsIb, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbR, BX_ISA_AVX512_DQ, OP_mVdq256, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF64x4_WpdVpdIb, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbR, BX_ISA_AVX512, OP_mVdq256, OP_Vpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF32x8_WpsVpsIb_Kmask, &BX_CPU_C::VEXTRACTF32x8_MASK_WpsVpsIbM, &BX_CPU_C::VEXTRACTF32x8_MASK_WpsVpsIbR, BX_ISA_AVX512_DQ, OP_mVdq256, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTF64x4_WpdVpdIb_Kmask, &BX_CPU_C::VEXTRACTF64x4_MASK_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x4_MASK_WpdVpdIbR, BX_ISA_AVX512, OP_mVdq256, OP_Vpd, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI32x4_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_ISA_AVX512, OP_mVdq128, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI64x2_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_ISA_AVX512_DQ, OP_mVdq128, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI32x4_WdqVdqIb_Kmask, &BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbM, &BX_CPU_C::VEXTRACTF32x4_MASK_WpsVpsIbR, BX_ISA_AVX512, OP_mVdq128, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI64x2_WdqVdqIb_Kmask, &BX_CPU_C::VEXTRACTF64x2_MASK_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x2_MASK_WpdVpdIbR, BX_ISA_AVX512_DQ, OP_mVdq128, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI32x8_WdqVdqIb, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbR, BX_ISA_AVX512_DQ, OP_mVdq256, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI64x4_WdqVdqIb, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x4_WpdVpdIbR, BX_ISA_AVX512, OP_mVdq256, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI32x8_WdqVdqIb_Kmask, &BX_CPU_C::VEXTRACTF32x8_MASK_WpsVpsIbM, &BX_CPU_C::VEXTRACTF32x8_MASK_WpsVpsIbR, BX_ISA_AVX512_DQ, OP_mVdq256, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTI64x4_WdqVdqIb_Kmask, &BX_CPU_C::VEXTRACTF64x4_MASK_WpdVpdIbM, &BX_CPU_C::VEXTRACTF64x4_MASK_WpdVpdIbR, BX_ISA_AVX512, OP_mVdq256, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VBROADCASTF32x2_VpsWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWqR, BX_ISA_AVX512_DQ, OP_Vps, OP_mVdq64, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VBROADCASTSD_VpdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPBROADCASTQ_VdqWqR, BX_ISA_AVX512, OP_Vpd, OP_mVsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VBROADCASTF32x2_VpsWq_Kmask, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VBROADCASTF32x2_MASK_VpsWqR, BX_ISA_AVX512_DQ, OP_Vps, OP_mVdq64, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)