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disasm fixes

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This commit is contained in:
Stanislav Shwartsman 2013-10-06 19:04:52 +00:00
parent add8eea761
commit e55611df21
4 changed files with 40 additions and 41 deletions
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31
bochs/cpu/disasm.cc
View File

@ -88,6 +88,8 @@ static const char *rounding_mode[4] = {
};
#endif
#define BX_JUMP_TARGET_NOT_REQ ((bx_address)(-1))
char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regname[])
{
unsigned sib_base = i->sibBase(), sib_index = i->sibIndex(), sib_scale = i->sibScale();
@ -99,14 +101,10 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regn
if (sib_index == BX_NIL_REGISTER)
{
if (! i->as32L()) {
if (i->displ16s() != 0) {
disbufptr = dis_sprintf(disbufptr, "0x%04x", (Bit32u) (Bit16u) i->displ16s());
}
disbufptr = dis_sprintf(disbufptr, "0x%04x", (Bit32u) (Bit16u) i->displ16s());
}
else {
if (i->displ32s() != 0) {
disbufptr = dis_sprintf(disbufptr, "0x%08x", (Bit32u) i->displ32s());
}
disbufptr = dis_sprintf(disbufptr, "0x%08x", (Bit32u) i->displ32s());
}
return disbufptr;
}
@ -312,19 +310,18 @@ char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_a
break;
case BX_IMM_BrOff32:
{
#if BX_SUPPORT_X86_64
if (i->os64L()) {
Bit64u target = rip + i->ilen() + (Bit32s) i->Id();
disbufptr = dis_sprintf(disbufptr, ".%+d (0x" FMT_ADDRX ")", i->Id(), (Bit64u) (cs_base + target));
}
else
#endif
{
Bit32u target = rip + i->ilen() + (Bit32s) i->Id();
disbufptr = dis_sprintf(disbufptr, ".%+d (0x%08x)", i->Id(), (Bit32u) (cs_base + target));
}
Bit32u target = rip + i->ilen() + (Bit32s) i->Id();
disbufptr = dis_sprintf(disbufptr, ".%+d (0x%08x)", i->Id(), (Bit32u) (cs_base + target));
}
break;
#if BX_SUPPORT_X86_64
case BX_IMM_BrOff64:
{
Bit64u target = rip + i->ilen() + (Bit32s) i->Id();
disbufptr = dis_sprintf(disbufptr, ".%+d (0x" FMT_ADDRX ")", i->Id(), (Bit64u) (cs_base + target));
}
break;
#endif
case BX_RSIREF:
disbufptr = dis_sprintf(disbufptr, "%s:", intel_segment_name[i->seg()]);
#if BX_SUPPORT_X86_64

17
bochs/cpu/fetchdecode.h
View File

@ -108,13 +108,14 @@ enum {
BX_IMMB2 = 0x15,
BX_IMM_BrOff16 = 0x16,
BX_IMM_BrOff32 = 0x17,
BX_RSIREF = 0x18,
BX_RDIREF = 0x19,
BX_USECL = 0x1A,
BX_USEDX = 0x1B,
BX_DIRECT_PTR = 0x1C,
BX_DIRECT_MEMREF32 = 0x1D,
BX_DIRECT_MEMREF64 = 0x1E,
BX_IMM_BrOff64 = 0x18,
BX_RSIREF = 0x19,
BX_RDIREF = 0x1A,
BX_USECL = 0x1B,
BX_USEDX = 0x1C,
BX_DIRECT_PTR = 0x1D,
BX_DIRECT_MEMREF32 = 0x1E,
BX_DIRECT_MEMREF64 = 0x1F
};
#define BX_FORM_SRC(type, src) (((type) << 3) | (src))
@ -150,7 +151,7 @@ const Bit8u OP_Ib2 = BX_FORM_SRC(BX_IMMB2, BX_SRC_NONE);
const Bit8u OP_Jw = BX_FORM_SRC(BX_IMM_BrOff16, BX_SRC_NONE);
const Bit8u OP_Jd = BX_FORM_SRC(BX_IMM_BrOff32, BX_SRC_NONE);
const Bit8u OP_Jq = BX_FORM_SRC(BX_IMM_BrOff32, BX_SRC_NONE); /* always same as OP_Jd ? */
const Bit8u OP_Jq = BX_FORM_SRC(BX_IMM_BrOff64, BX_SRC_NONE);
const Bit8u OP_M = BX_SRC_RM;
const Bit8u OP_Mb = BX_SRC_RM;

32
bochs/disasm/dis_tables.inc
View File

@ -1145,14 +1145,14 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes16[256*2] = {
/* 0F C5 */ { GRPSSE(0fc5) },
/* 0F C6 */ { GRPSSE(0fc6) },
/* 0F C7 */ { GRPMOD(G9w) },
/* 0F C8 */ { 0, &Ia_bswapl_ERX },
/* 0F C9 */ { 0, &Ia_bswapl_ERX },
/* 0F CA */ { 0, &Ia_bswapl_ERX },
/* 0F CB */ { 0, &Ia_bswapl_ERX },
/* 0F CC */ { 0, &Ia_bswapl_ERX },
/* 0F CD */ { 0, &Ia_bswapl_ERX },
/* 0F CE */ { 0, &Ia_bswapl_ERX },
/* 0F CF */ { 0, &Ia_bswapl_ERX },
/* 0F C8 */ { 0, &Ia_bswapw_RX },
/* 0F C9 */ { 0, &Ia_bswapw_RX },
/* 0F CA */ { 0, &Ia_bswapw_RX },
/* 0F CB */ { 0, &Ia_bswapw_RX },
/* 0F CC */ { 0, &Ia_bswapw_RX },
/* 0F CD */ { 0, &Ia_bswapw_RX },
/* 0F CE */ { 0, &Ia_bswapw_RX },
/* 0F CF */ { 0, &Ia_bswapw_RX },
/* 0F D0 */ { GRPSSE(0fd0) },
/* 0F D1 */ { GRPSSE(0fd1) },
/* 0F D2 */ { GRPSSE(0fd2) },
@ -2187,14 +2187,14 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodes64w[256*2] = {
/* 0F C5 */ { GRPSSE(0fc5) },
/* 0F C6 */ { GRPSSE(0fc6) },
/* 0F C7 */ { GRPMOD(G9w) },
/* 0F C8 */ { 0, &Ia_bswapl_ERX },
/* 0F C9 */ { 0, &Ia_bswapl_ERX },
/* 0F CA */ { 0, &Ia_bswapl_ERX },
/* 0F CB */ { 0, &Ia_bswapl_ERX },
/* 0F CC */ { 0, &Ia_bswapl_ERX },
/* 0F CD */ { 0, &Ia_bswapl_ERX },
/* 0F CE */ { 0, &Ia_bswapl_ERX },
/* 0F CF */ { 0, &Ia_bswapl_ERX },
/* 0F C8 */ { 0, &Ia_bswapw_RX },
/* 0F C9 */ { 0, &Ia_bswapw_RX },
/* 0F CA */ { 0, &Ia_bswapw_RX },
/* 0F CB */ { 0, &Ia_bswapw_RX },
/* 0F CC */ { 0, &Ia_bswapw_RX },
/* 0F CD */ { 0, &Ia_bswapw_RX },
/* 0F CE */ { 0, &Ia_bswapw_RX },
/* 0F CF */ { 0, &Ia_bswapw_RX },
/* 0F D0 */ { GRPSSE(0fd0) },
/* 0F D1 */ { GRPSSE(0fd1) },
/* 0F D2 */ { GRPSSE(0fd2) },

1
bochs/disasm/opcodes.inc
View File

@ -128,6 +128,7 @@ Ia_bsfw_Gw_Ew = { "bsf", "bsfw", Gw, Ew, XX, XX, 0 },
Ia_bsrl_Gd_Ed = { "bsr", "bsrl", Gd, Ed, XX, XX, 0 },
Ia_bsrq_Gq_Eq = { "bsr", "bsrq", Gq, Eq, XX, XX, 0 },
Ia_bsrw_Gw_Ew = { "bsr", "bsrw", Gw, Ew, XX, XX, 0 },
Ia_bswapw_RX = { "bswap", "bswapw", RX, XX, XX, XX, IA_486 },
Ia_bswapl_ERX = { "bswap", "bswapl", ERX, XX, XX, XX, IA_486 },
Ia_bswapq_RRX = { "bswap", "bswapq", RRX, XX, XX, XX, 0 },
Ia_btcl_Ed_Gd = { "btc", "btcl", Ed, Gd, XX, XX, 0 },