mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

more avx-512 instructions implemented

Browse Source
This commit is contained in:
Stanislav Shwartsman 2013-12-01 19:39:18 +00:00
parent e141fbf848
commit 2b83146ae2
8 changed files with 181 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
bochs/cpu/3dnow.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-2012 Stanislav Shwartsman
// Copyright (c) 2002-2013 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -38,7 +38,7 @@ BX_CPP_INLINE void prepare_softfloat_status_word(float_status_t &status, int rou
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFPNACC_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFPNACC_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
@ -115,7 +115,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PI2FD_PqQq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PF2IW_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PF2IW_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
@ -157,112 +157,112 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PF2ID_PqQq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFNACC_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFNACC_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFCMPGE_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFCMPGE_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFMIN_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFMIN_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFRCP_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFRCP_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFRSQRT_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFRSQRT_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFSUB_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFSUB_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFADD_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFADD_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFCMPGT_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFCMPGT_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFMAX_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFMAX_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFRCPIT1_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFRCPIT1_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFRSQIT1_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFRSQIT1_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFSUBR_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFSUBR_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFACC_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFACC_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFCMPEQ_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFCMPEQ_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFMUL_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFMUL_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PFRCPIT2_PqQq(bxInstruction_c *i)
{
BX_PANIC(("PFRCPIT2_PqQq: 3DNow! instruction still not implemented"));
BX_PANIC(("%s: 3DNow! instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}

88
bochs/cpu/avx512_move.cc
View File

@ -304,9 +304,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPD_MASK_WpdVpdM(bxInstruction
BX_NEXT_INSTR(i);
}
///////////////////////
// masked load/store //
///////////////////////
//////////////////////////////
// masked packed load/store //
//////////////////////////////
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPS_MASK_VpsWpsM(bxInstruction_c *i)
{
@ -366,4 +366,86 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPD_MASK_WpdVpdM(bxInstruction
BX_NEXT_INSTR(i);
}
//////////////////////////////
// masked scalar load/store //
//////////////////////////////
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSD_MASK_VsdWsdM(bxInstruction_c *i)
{
BxPackedXmmRegister op;
op.xmm64u(1) = 0;
if (BX_SCALAR_ELEMENT_MASK(i->opmask())) {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op.xmm64u(0) = read_virtual_qword(i->seg(), eaddr);
}
else {
if (! i->isZeroMasking()) {
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->dst());
}
else {
op.xmm64u(0) = 0;
}
}
BX_WRITE_XMM_REGZ(i->dst(), op, i->getVL());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSS_MASK_VssWssM(bxInstruction_c *i)
{
BxPackedXmmRegister op;
op.xmm64u(1) = 0;
if (BX_SCALAR_ELEMENT_MASK(i->opmask())) {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op.xmm64u(0) = (Bit64u) read_virtual_dword(i->seg(), eaddr);
}
else {
if (! i->isZeroMasking()) {
op.xmm64u(0) = (Bit64u) BX_READ_XMM_REG_LO_DWORD(i->dst());
}
else {
op.xmm64u(0) = 0;
}
}
BX_WRITE_XMM_REGZ(i->dst(), op, i->getVL());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSD_MASK_WsdVsdM(bxInstruction_c *i)
{
if (BX_SCALAR_ELEMENT_MASK(i->opmask())) {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_qword(i->seg(), eaddr, BX_READ_XMM_REG_LO_QWORD(i->src()));
}
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSS_MASK_WssVssM(bxInstruction_c *i)
{
if (BX_SCALAR_ELEMENT_MASK(i->opmask())) {
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dword(i->seg(), eaddr, BX_READ_XMM_REG_LO_DWORD(i->src()));
}
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSD_MASK_VsdHpdWsdR(bxInstruction_c *i)
{
BX_PANIC(("%s: instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSS_MASK_VssHpsWssR(bxInstruction_c *i)
{
BX_PANIC(("%s: instruction still not implemented", i->getIaOpcodeName()));
BX_NEXT_INSTR(i);
}
#endif

9
bochs/cpu/cpu.h
View File

@ -2388,6 +2388,7 @@ public: // for now...
BX_SMF BX_INSF_TYPE MOVSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVSS_VssWssM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVSS_WssVssM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVSD_VsdWsdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVSD_WsdVsdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVHLPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVLPS_VpsMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2499,7 +2500,6 @@ public: // for now...
BX_SMF BX_INSF_TYPE PCMPEQD_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVD_EdVdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVQ_VqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVQ_VqWqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE CMPPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE CMPSD_VsdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRW_VdqHdqEwIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -3255,6 +3255,13 @@ public: // for now...
BX_SMF BX_INSF_TYPE VMOVUPD_MASK_VpdWpdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVUPD_MASK_WpdVpdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSD_MASK_VsdWsdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSS_MASK_VssWssM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSD_MASK_WsdVsdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSS_MASK_WssVssM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSD_MASK_VsdHpdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VMOVSS_MASK_VssHpsWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDPD_MASK_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDPS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VFMADDSD_MASK_VpdHsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);

2
bochs/cpu/crregs.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2010-2012 Stanislav Shwartsman
// Copyright (c) 2010-2013 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or

2
bochs/cpu/crregs.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007-2011 Stanislav Shwartsman
// Copyright (c) 2007-2013 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or

52
bochs/cpu/fetchdecode_evex.h
View File

@ -26,6 +26,34 @@
#if BX_SUPPORT_EVEX
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f10[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VMOVUPS_VpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVUPD_VpdWpd },
/* F3 */ { BxVexW0, BX_IA_V512_VMOVSS_VssHpsWss },
/* F2 */ { BxVexW1, BX_IA_V512_VMOVSD_VsdHpdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f10_Mask[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VMOVUPS_VpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVUPD_VpdWpd_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VMOVSS_VssHpsWss_Kmask },
/* F2 */ { BxVexW1, BX_IA_V512_VMOVSD_VsdHpdWsd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f11[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VMOVUPS_WpsVps },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVUPD_WpdVpd },
/* F3 */ { BxVexW0, BX_IA_V512_VMOVSS_WssHpsVss },
/* F2 */ { BxVexW1, BX_IA_V512_VMOVSD_WsdHpdVsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f11_Mask[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VMOVUPS_WpsVps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVUPD_WpdVpd_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VMOVSS_WssHpsVss_Kmask },
/* F2 */ { BxVexW1, BX_IA_V512_VMOVSD_WsdHpdVsd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f14[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VUNPCKLPS_VpsHpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VUNPCKLPD_VpdHpdWpd }
@ -234,10 +262,10 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 0E */ { 0, BX_IA_ERROR },
/* 0F k0 */ { 0, BX_IA_ERROR },
/* 0F */ { 0, BX_IA_ERROR },
/* 10 k0 */ { 0, BX_IA_ERROR },
/* 10 */ { 0, BX_IA_ERROR },
/* 11 k0 */ { 0, BX_IA_ERROR },
/* 11 */ { 0, BX_IA_ERROR },
/* 10 k0 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f10 },
/* 10 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f10_Mask },
/* 11 k0 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f11 },
/* 11 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f11_Mask },
/* 12 k0 */ { 0, BX_IA_ERROR },
/* 12 */ { 0, BX_IA_ERROR },
/* 13 k0 */ { 0, BX_IA_ERROR },
@ -398,8 +426,8 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 60 */ { 0, BX_IA_ERROR },
/* 61 k0 */ { 0, BX_IA_ERROR },
/* 61 */ { 0, BX_IA_ERROR },
/* 62 k0 */ { 0, BX_IA_ERROR },
/* 62 */ { 0, BX_IA_ERROR },
/* 62 k0 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPUNPCKLDQ_VdqHdqWdq },
/* 62 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPUNPCKLDQ_VdqHdqWdq_Kmask },
/* 63 k0 */ { 0, BX_IA_ERROR },
/* 63 */ { 0, BX_IA_ERROR },
/* 64 k0 */ { 0, BX_IA_ERROR },
@ -414,14 +442,14 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 68 */ { 0, BX_IA_ERROR },
/* 69 k0 */ { 0, BX_IA_ERROR },
/* 69 */ { 0, BX_IA_ERROR },
/* 6A k0 */ { 0, BX_IA_ERROR },
/* 6A */ { 0, BX_IA_ERROR },
/* 6A k0 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPUNPCKHDQ_VdqHdqWdq },
/* 6A */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPUNPCKHDQ_VdqHdqWdq_Kmask },
/* 6B k0 */ { 0, BX_IA_ERROR },
/* 6B */ { 0, BX_IA_ERROR },
/* 6C k0 */ { 0, BX_IA_ERROR },
/* 6C */ { 0, BX_IA_ERROR },
/* 6D k0 */ { 0, BX_IA_ERROR },
/* 6D */ { 0, BX_IA_ERROR },
/* 6C k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPUNPCKLQDQ_VdqHdqWdq },
/* 6C */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPUNPCKLQDQ_VdqHdqWdq_Kmask },
/* 6D k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPUNPCKHQDQ_VdqHdqWdq },
/* 6D */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPUNPCKHQDQ_VdqHdqWdq_Kmask },
/* 6E k0 */ { 0, BX_IA_ERROR },
/* 6E */ { 0, BX_IA_ERROR },
/* 6F k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f6f },

32
bochs/cpu/ia_opcodes.h
View File

@ -1019,7 +1019,7 @@ bx_define_opcode(BX_IA_CVTSS2SD_VsdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SD
bx_define_opcode(BX_IA_CVTSD2SS_VssWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SS_VssWsdR, BX_ISA_SSE2, OP_Vss, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
// SSE alias
bx_define_opcode(BX_IA_MOVSD_VsdWsd, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVSD_VsdWsdR, BX_ISA_SSE2, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVSD_VsdWsd, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVSD_VsdWsdR, BX_ISA_SSE2, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVSD_WsdVsd, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVSD_VsdWsdR, BX_ISA_SSE2, OP_Wsd, OP_Vsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTPI2PD_VpdQq, &BX_CPU_C::CVTPI2PD_VpdQqM, &BX_CPU_C::CVTPI2PD_VpdQqR, BX_ISA_SSE2, OP_Vpd, OP_Qq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTSI2SD_VsdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CVTSI2SD_VsdEdR, BX_ISA_SSE2, OP_Vsd, OP_Ed, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@ -1079,7 +1079,7 @@ bx_define_opcode(BX_IA_PCMPEQB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQB_V
bx_define_opcode(BX_IA_PCMPEQW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQW_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PCMPEQD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQD_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, BX_ISA_SSE2, OP_Ed, OP_Vd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_SSE2, OP_Vq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVQ_VqWq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_SSE2, OP_Vq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVNTI_Op32_MdGd, &BX_CPU_C::MOV32_EdGdM, &BX_CPU_C::BxError, BX_ISA_SSE2, OP_Ed, OP_Gd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::PINSRW_VdqHdqEwIbR, BX_ISA_SSE2, OP_Vdq, OP_Vdq, OP_Ew, OP_Ib, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_ISA_SSE2, OP_Gd, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
@ -1521,7 +1521,7 @@ bx_define_opcode(BX_IA_JRCXZ_Jb, NULL, &BX_CPU_C::JRCXZ_Jb, 0, OP_Jq, OP_NONE, O
bx_define_opcode(BX_IA_MOVQ_EqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_EqVqR, 0, OP_Eq, OP_Vq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVQ_PqEq, &BX_CPU_C::MOVQ_PqQqM, &BX_CPU_C::MOVQ_PqEqR, 0, OP_Pq, OP_Eq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_MOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, 0, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVQ_VdqEq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VdqEqR, 0, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::CVTSI2SS_VssEqR, 0, OP_Vss, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::CVTSI2SD_VsdEqR, 0, OP_Vsd, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, 0, OP_Gq, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@ -1631,7 +1631,7 @@ bx_define_opcode(BX_IA_V256_VMOVDQU_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_
bx_define_opcode(BX_IA_V128_VMOVDQU_WdqVdq, &BX_CPU_C::MOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VMOVDQU_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX, OP_Wdq, OP_Vdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVSD_VsdHpdWsd, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVSD_VsdHpdWsd, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVSS_VssHpsWss, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::VMOVSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_NNN, BX_SRC_RM, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVSD_WsdHpdVsd, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVSS_WssHpsVss, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::VMOVSS_VssHpsWssR, BX_ISA_AVX, BX_SRC_RM, BX_SRC_NNN, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_AVX)
@ -2066,8 +2066,8 @@ bx_define_opcode(BX_IA_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI
bx_define_opcode(BX_IA_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, BX_ISA_AVX, OP_Gq, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVQ_WqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX, OP_Wq, OP_Vq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX, OP_Vq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, BX_ISA_AVX, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVQ_VqWq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX, OP_Vq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVQ_VdqEq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VdqEqR, BX_ISA_AVX, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVQ_EqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_EqVqR, BX_ISA_AVX, OP_Eq, OP_Vq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTPH2PS_VpsWps, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_ISA_AVX_F16C, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_AVX)
@ -2527,6 +2527,16 @@ bx_define_opcode(BX_IA_V512_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_BROADCAST_Vecto
bx_define_opcode(BX_IA_V512_VUNPCKHPS_VpsHpsWps_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VUNPCKHPD_VpdHpdWpd_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPUNPCKLDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPUNPCKLQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPUNPCKLDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKLPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPUNPCKLQDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKLPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPUNPCKHDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPUNPCKHQDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPUNPCKHDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VUNPCKHPS_MASK_VpsHpsWpsR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPUNPCKHQDQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VUNPCKHPD_MASK_VpdHpdWpdR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPMULLD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMULLD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPMULLD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPMULLD_MASK_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
@ -2555,6 +2565,16 @@ bx_define_opcode(BX_IA_V512_VMOVUPD_VpdWpd_Kmask, &BX_CPU_C::VMOVUPD_MASK_VpdWpd
bx_define_opcode(BX_IA_V512_VMOVUPD_WpdVpd, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVUPD_WpdVpd_Kmask, &BX_CPU_C::VMOVUPD_MASK_WpdVpdM, &BX_CPU_C::VMOVAPD_MASK_VpdWpdR, BX_ISA_AVX512, OP_Wpd, OP_Vpd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVSD_VsdHpdWsd, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_RM, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVSS_VssHpsWss, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::VMOVSS_VssHpsWssR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_RM, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVSD_WsdHpdVsd, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::VMOVSD_VsdHpdWsdR, BX_ISA_AVX512, BX_SRC_RM, BX_SRC_NNN, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVSS_WssHpsVss, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::VMOVSS_VssHpsWssR, BX_ISA_AVX512, BX_SRC_RM, BX_SRC_NNN, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVSD_VsdHpdWsd_Kmask, &BX_CPU_C::VMOVSD_MASK_VsdWsdM, &BX_CPU_C::VMOVSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_RM, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVSS_VssHpsWss_Kmask, &BX_CPU_C::VMOVSS_MASK_VssWssM, &BX_CPU_C::VMOVSS_MASK_VssHpsWssR, BX_ISA_AVX512, BX_SRC_NNN, BX_SRC_RM, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVSD_WsdHpdVsd_Kmask, &BX_CPU_C::VMOVSD_MASK_WsdVsdM, &BX_CPU_C::VMOVSD_MASK_VsdHpdWsdR, BX_ISA_AVX512, BX_SRC_RM, BX_SRC_NNN, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VMOVSS_WssHpsVss_Kmask, &BX_CPU_C::VMOVSS_MASK_WssVssM, &BX_CPU_C::VMOVSS_MASK_VssHpsWssR, BX_ISA_AVX512, BX_SRC_RM, BX_SRC_NNN, BX_SRC_MEM_NO_VVV, OP_NONE, BX_PREPARE_EVEX)
// VexW alias
bx_define_opcode(BX_IA_V512_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX)

2
bochs/cpu/sse_move.cc
View File

@ -741,7 +741,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqR(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqM(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_VsdWsdM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op;