mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

code cleanups

Browse Source
This commit is contained in:
Stanislav Shwartsman 2013-12-09 20:36:24 +00:00
parent f534e8f6f6
commit ccb1d86d6e
3 changed files with 27 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
bochs/cpu/cpu.h
View File

@ -5339,8 +5339,7 @@ enum {
#define BxSplitGroupN 0x0090 // Group encoding: 1001
#define BxFPEscape 0x00A0 // Group encoding: 1010
#define BxOSizeGrp 0x00B0 // Group encoding: 1011
#define BxSplitVexW 0x00C0 // Group encoding: 1100
#define BxSplitMod11B 0x00D0 // Group encoding: 1101
#define BxSplitMod11B 0x00C0 // Group encoding: 1100
// The BxImmediate2 mask specifies kind of second immediate data
// required by instruction.

3
bochs/cpu/fetchdecode.cc
View File

@ -2018,9 +2018,6 @@ Bit16u BX_CPU_C::WalkOpcodeTables(const BxOpcodeInfo_t *OpcodeInfoPtr, Bit16u &a
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn + (mod_mem << 3)]);
break;
#if BX_SUPPORT_AVX
case BxSplitVexW:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[vex_w]);
break;
case BxSplitMod11B:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[mod_mem]);
break;

38
bochs/cpu/load.cc
View File

@ -129,13 +129,20 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOADU_Wdq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Vector(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
unsigned vl = i->getVL();
BX_ASSERT(i->getVL() != BX_VL512);
if (i->getVL() == BX_VL256)
read_virtual_ymmword(i->seg(), eaddr, &BX_READ_YMM_REG(BX_VECTOR_TMP_REGISTER));
#if BX_SUPPORT_EVEX
if (vl == BX_VL512) {
read_virtual_zmmword(i->seg(), eaddr, &BX_READ_AVX_REG(BX_VECTOR_TMP_REGISTER));
}
else
read_virtual_xmmword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_VECTOR_TMP_REGISTER));
#endif
{
if (vl == BX_VL256)
read_virtual_ymmword(i->seg(), eaddr, &BX_READ_YMM_REG(BX_VECTOR_TMP_REGISTER));
else
read_virtual_xmmword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_VECTOR_TMP_REGISTER));
}
BX_CPU_CALL_METHOD(i->execute2(), (i));
}
@ -143,15 +150,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Vector(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Half_Vector(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
unsigned vl = i->getVL();
BX_ASSERT(i->getVL() != BX_VL512);
if (i->getVL() == BX_VL256) {
read_virtual_xmmword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_VECTOR_TMP_REGISTER));
#if BX_SUPPORT_EVEX
if (vl == BX_VL512) {
read_virtual_ymmword(i->seg(), eaddr, &BX_READ_YMM_REG(BX_VECTOR_TMP_REGISTER));
}
else {
Bit64u val_64 = read_virtual_qword(i->seg(), eaddr);
BX_WRITE_XMM_REG_LO_QWORD(BX_VECTOR_TMP_REGISTER, val_64);
else
#endif
{
if (vl == BX_VL256) {
read_virtual_xmmword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_VECTOR_TMP_REGISTER));
}
else {
Bit64u val_64 = read_virtual_qword(i->seg(), eaddr);
BX_WRITE_XMM_REG_LO_QWORD(BX_VECTOR_TMP_REGISTER, val_64);
}
}
BX_CPU_CALL_METHOD(i->execute2(), (i));