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fixes in disasm, added example of using bxInstruction_c disasm into dbg_main.cc (commented out for now)

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This commit is contained in:
Stanislav Shwartsman 2013-10-05 19:32:09 +00:00
parent b1d703e47c
commit fd370a4d41
4 changed files with 34 additions and 11 deletions
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23
bochs/bx_debug/dbg_main.cc
View File

@ -1936,10 +1936,33 @@ void bx_dbg_disassemble_current(int which_cpu, int print_time)
if (bx_dbg_read_linear(which_cpu, BX_CPU(which_cpu)->guard_found.laddr, 16, bx_disasm_ibuf))
{
#if 1
unsigned ilen = bx_disassemble.disasm(IS_CODE_32(BX_CPU(which_cpu)->guard_found.code_32_64),
IS_CODE_64(BX_CPU(which_cpu)->guard_found.code_32_64),
BX_CPU(which_cpu)->get_segment_base(BX_SEG_REG_CS),
BX_CPU(which_cpu)->guard_found.eip, bx_disasm_ibuf, bx_disasm_tbuf);
#else
extern char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_address rip);
Bit32u fetchModeMask = BX_CPU(which_cpu)->fetchModeMask | BX_FETCH_MODE_SSE_MASK |
BX_FETCH_MODE_AVX_MASK |
BX_FETCH_MODE_EVEX_MASK;
int ret;
bxInstruction_c i;
#if BX_SUPPORT_X86_64
if (BX_CPU(which_cpu)->cpu_mode == BX_MODE_LONG_64)
ret = BX_CPU(which_cpu)->fetchDecode64(bx_disasm_ibuf, fetchModeMask, &i, 16);
else
#endif
ret = BX_CPU(which_cpu)->fetchDecode32(bx_disasm_ibuf, fetchModeMask, &i, 16);
if (ret < 0)
sprintf(bx_disasm_tbuf, "decode failed");
else
disasm(bx_disasm_tbuf, &i, BX_CPU(which_cpu)->get_segment_base(BX_SEG_REG_CS), BX_CPU(which_cpu)->guard_found.eip);
unsigned ilen = i.ilen();
#endif
// Note: it would be nice to display only the modified registers here, the easy
// way out I have thought of would be to keep a prev_eax, prev_ebx, etc copies

4
bochs/cpu/disasm.cc
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@ -98,7 +98,7 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regn
{
if (sib_index == BX_NIL_REGISTER)
{
if (! i->os32L()) {
if (! i->as32L()) {
if (i->displ16s() != 0) {
disbufptr = dis_sprintf(disbufptr, "0x%04x", (Bit32u) (Bit16u) i->displ16s());
}
@ -126,7 +126,7 @@ char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regn
}
}
if (! i->os32L()) {
if (! i->as32L()) {
if (i->displ16s() != 0) {
disbufptr = dis_sprintf(disbufptr, "%+d", (Bit32s) i->displ16s());
}

10
bochs/cpu/ia_opcodes.h
View File

@ -397,10 +397,10 @@ bx_define_opcode(BX_IA_SIDT_Ms, &BX_CPU_C::SIDT_Ms, &BX_CPU_C::BxError, 0, OP_M,
bx_define_opcode(BX_IA_LIDT_Ms, &BX_CPU_C::LIDT_Ms, &BX_CPU_C::BxError, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_SGDT_Ms, &BX_CPU_C::SGDT_Ms, &BX_CPU_C::BxError, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_LGDT_Ms, &BX_CPU_C::LGDT_Ms, &BX_CPU_C::BxError, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_SLDT_Ew, &BX_CPU_C::SLDT_Ew, &BX_CPU_C::SLDT_Ew, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_LLDT_Ew, &BX_CPU_C::LLDT_Ew, &BX_CPU_C::LLDT_Ew, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_STR_Ew, &BX_CPU_C::STR_Ew, &BX_CPU_C::STR_Ew, 0, OP_M, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_LTR_Ew, &BX_CPU_C::LTR_Ew, &BX_CPU_C::LTR_Ew, 0, BX_SRC_NNN, OP_M, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_SLDT_Ew, &BX_CPU_C::SLDT_Ew, &BX_CPU_C::SLDT_Ew, 0, OP_Ew, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_LLDT_Ew, &BX_CPU_C::LLDT_Ew, &BX_CPU_C::LLDT_Ew, 0, BX_SRC_NNN, OP_Ew, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_STR_Ew, &BX_CPU_C::STR_Ew, &BX_CPU_C::STR_Ew, 0, OP_Ew, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_LTR_Ew, &BX_CPU_C::LTR_Ew, &BX_CPU_C::LTR_Ew, 0, BX_SRC_NNN, OP_Ew, OP_NONE, OP_NONE, 0)
// IDT/GDT/LDTR/TR access - keep NNN for VMX
bx_define_opcode(BX_IA_SMSW_Ew, &BX_CPU_C::SMSW_EwM, &BX_CPU_C::SMSW_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, 0)
@ -604,7 +604,7 @@ bx_define_opcode(BX_IA_XCHG_EbGb, &BX_CPU_C::XCHG_EbGbM, &BX_CPU_C::XCHG_EbGbR,
bx_define_opcode(BX_IA_XCHG_EwGw, &BX_CPU_C::XCHG_EwGwM, &BX_CPU_C::XCHG_EwGwR, 0, OP_Ew, OP_Gw, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_XCHG_EdGd, &BX_CPU_C::XCHG_EdGdM, &BX_CPU_C::XCHG_EdGdR, 0, OP_Ed, OP_Gd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_XCHG_RXAX, NULL, &BX_CPU_C::XCHG_RXAX, 0, OP_Ew, OP_AXReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_XCHG_ERXEAX, NULL, &BX_CPU_C::XCHG_ERXEAX, 0, OP_Ew, OP_EAXReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_XCHG_ERXEAX, NULL, &BX_CPU_C::XCHG_ERXEAX, 0, OP_Ed, OP_EAXReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_XLAT, NULL, &BX_CPU_C::XLAT, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_SYSENTER, NULL, &BX_CPU_C::SYSENTER, BX_ISA_SYSENTER_SYSEXIT, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)

8
bochs/disasm/opcodes.inc
View File

@ -504,8 +504,8 @@ Ia_invpcid_Gy_Mdq = { "invpcid", "invpcid", Gy, Mdq, XX, XX, IA_INVPCID },
Ia_invvpid_Gy_Mdq = { "invvpid", "invvpid", Gy, Mdq, XX, XX, IA_VMX },
Ia_inw_AX_DX = { "in", "inw", AX_Reg, DX_Reg, XX, XX, 0 },
Ia_inw_AX_Ib = { "in", "inw", AX_Reg, Ib, XX, XX, 0 },
Ia_iretl = { "iretd", "iretd", XX, XX, XX, XX, 0 },
Ia_iretq = { "iretq", "iretq", XX, XX, XX, XX, 0 },
Ia_iretl = { "iret", "iretd", XX, XX, XX, XX, 0 },
Ia_iretq = { "iret", "iretq", XX, XX, XX, XX, 0 },
Ia_iretw = { "iret", "iretw", XX, XX, XX, XX, 0 },
Ia_jb_Jb = { "jb", "jb", Jb, XX, XX, XX, 0 },
Ia_jb_Jd = { "jb", "jb", Jd, XX, XX, XX, 0 },
@ -1071,8 +1071,8 @@ Ia_punpcklwd_Pq_Qd = { "punpcklwd", "punpcklwd", Pq, Qd, XX, XX, IA_MMX },
Ia_punpcklwd_Vdq_Wdq = { "punpcklwd", "punpcklwd", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_pushal = { "pushad", "pushal", XX, XX, XX, XX, 0 },
Ia_pushaw = { "pusha", "pusha", XX, XX, XX, XX, 0 },
Ia_pushfl = { "pushfd", "pushfl", XX, XX, XX, XX, 0 },
Ia_pushfq = { "pushfq", "pushfq", XX, XX, XX, XX, 0 },
Ia_pushfl = { "pushf", "pushfl", XX, XX, XX, XX, 0 },
Ia_pushfq = { "pushf", "pushfq", XX, XX, XX, XX, 0 },
Ia_pushfw = { "pushf", "pushf", XX, XX, XX, XX, 0 },
Ia_pushl_CS = { "push", "pushl", CS, XX, XX, XX, 0 },
Ia_pushl_DS = { "push", "pushl", DS, XX, XX, XX, 0 },