implemented AVX-512 VINSERTF*/VINSERTI* opcodes
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@ -390,13 +390,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBROADCASTF128_VdqMdq(bxInstructio
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BxPackedAvxRegister dst;
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BxPackedXmmRegister src;
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unsigned len = i->getVL();
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#if BX_SUPPORT_EVEX
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if (len == BX_VL128) {
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BX_ERROR(("%s: vector length must be >= 256 bit", i->getIaOpcodeNameShort()));
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exception(BX_UD_EXCEPTION, 0);
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}
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#endif
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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read_virtual_xmmword(i->seg(), eaddr, (Bit8u*) &src);
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@ -497,7 +490,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF128_VdqHdqWdqIbR(bxInstruc
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{
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BxPackedYmmRegister op1 = BX_READ_YMM_REG(i->src1());
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op1.ymm128(i->Ib() & 1) = BX_READ_XMM_REG(i->src2());
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op1.ymm128(i->Ib() & 0x1) = BX_READ_XMM_REG(i->src2());
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BX_WRITE_YMM_REGZ(i->dst(), op1);
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@ -519,6 +519,50 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFF64x2_MASK_VpdHpdWpdIbR(bxIns
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF32x4_MASK_VpsHpsWpsIbR(bxInstruction_c *i)
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{
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unsigned len = i->getVL();
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if (len != BX_VL512) {
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BX_ERROR(("%s: vector length must be 512 bit", i->getIaOpcodeNameShort()));
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exception(BX_UD_EXCEPTION, 0);
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}
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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op1.vmm128(i->Ib() & 0x3) = BX_READ_XMM_REG(i->src2());
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if (i->opmask()) {
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avx512_write_regd_masked(i, &op1, len, BX_READ_16BIT_OPMASK(i->opmask()));
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}
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else {
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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}
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BX_NEXT_INSTR(i);
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}
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF64x4_MASK_VpdHpdWpdIbR(bxInstruction_c *i)
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{
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unsigned len = i->getVL();
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if (len != BX_VL512) {
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BX_ERROR(("%s: vector length must be 512 bit", i->getIaOpcodeNameShort()));
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exception(BX_UD_EXCEPTION, 0);
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}
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BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1());
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op1.vmm256(i->Ib() & 0x1) = BX_READ_YMM_REG(i->src2());
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if (i->opmask()) {
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avx512_write_regq_masked(i, &op1, len, BX_READ_8BIT_OPMASK(i->opmask()));
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}
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else {
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BX_WRITE_AVX_REGZ(i->dst(), op1, len);
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}
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BX_NEXT_INSTR(i);
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}
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// broadcast
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBROADCASTD_MASK_VdqWdR(bxInstruction_c *i)
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@ -589,13 +633,6 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VBROADCASTF32x4_MASK_VpsMps(bxInst
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BxPackedXmmRegister src;
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unsigned len = i->getVL();
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#if BX_SUPPORT_EVEX
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if (len == BX_VL128) {
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BX_ERROR(("%s: vector length must be >= 256 bit", i->getIaOpcodeNameShort()));
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exception(BX_UD_EXCEPTION, 0);
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}
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#endif
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Bit32u opmask = BX_READ_16BIT_OPMASK(i->opmask());
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if (opmask != 0) {
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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@ -3374,6 +3374,11 @@ public: // for now...
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BX_SMF BX_INSF_TYPE VSHUFF32x4_MASK_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE VSHUFF64x2_MASK_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE VINSERTF32x4_MASK_VpsHpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE VINSERTI32x4_MASK_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE VINSERTF64x4_MASK_VpdHpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE VINSERTI64x4_MASK_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE VPBROADCASTD_MASK_VdqWdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF BX_INSF_TYPE VPBROADCASTQ_MASK_VdqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -956,10 +956,10 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
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/* 18 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VBROADCASTSS_VpsWss_Kmask },
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/* 19 k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTSD_VpdWsd },
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/* 19 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTSD_VpdWsd_Kmask },
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/* 1A k0 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VBROADCASTF32x4_VpsWps },
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/* 1A */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VBROADCASTF32x4_VpsWps_Kmask },
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/* 1B k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTF64x4_VpdWpd },
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/* 1B */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTF64x4_VpdWpd_Kmask },
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/* 1A k0 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTF32x4_VpsWps },
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/* 1A */ { BxVexW0 | BxVexL1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTF32x4_VpsWps_Kmask },
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/* 1B k0 */ { BxVexW1 | BxVexL1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTF64x4_VpdWpd },
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/* 1B */ { BxVexW1 | BxVexL1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTF64x4_VpdWpd_Kmask },
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/* 1C k0 */ { 0, BX_IA_ERROR },
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/* 1C */ { 0, BX_IA_ERROR },
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/* 1D k0 */ { 0, BX_IA_ERROR },
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@ -1084,10 +1084,10 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
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/* 58 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPBROADCASTD_VdqWd_Kmask },
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/* 59 k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPBROADCASTQ_VdqWq },
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/* 59 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPBROADCASTQ_VdqWq_Kmask },
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/* 5A k0 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VBROADCASTI32x4_VdqWdq },
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/* 5A */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VBROADCASTI32x4_VdqWdq_Kmask },
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/* 5B k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTI64x4_VdqWdq },
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/* 5B */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTI64x4_VdqWdq_Kmask },
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/* 5A k0 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTI32x4_VdqWdq },
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/* 5A */ { BxVexW0 | BxVexL1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTI32x4_VdqWdq_Kmask },
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/* 5B k0 */ { BxVexW1 | BxVexL1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTI64x4_VdqWdq },
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/* 5B */ { BxVexW1 | BxVexL1 | BxPrefixSSE66, BX_IA_V512_VBROADCASTI64x4_VdqWdq_Kmask },
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/* 5C k0 */ { 0, BX_IA_ERROR },
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/* 5C */ { 0, BX_IA_ERROR },
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/* 5D k0 */ { 0, BX_IA_ERROR },
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@ -1466,12 +1466,12 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
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/* 16 */ { 0, BX_IA_ERROR },
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/* 17 k0 */ { BxVexW0 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTPS_EdVpsIb },
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/* 17 */ { 0, BX_IA_ERROR }, // #UD
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/* 18 k0 */ { 0, BX_IA_ERROR },
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/* 18 */ { 0, BX_IA_ERROR },
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/* 18 k0 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb_Kmask },
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/* 18 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb_Kmask },
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/* 19 k0 */ { 0, BX_IA_ERROR },
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/* 19 */ { 0, BX_IA_ERROR },
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/* 1A k0 */ { 0, BX_IA_ERROR },
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/* 1A */ { 0, BX_IA_ERROR },
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/* 1A k0 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF64x4_VpdHpdWpdIb_Kmask },
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/* 1A */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF64x4_VpdHpdWpdIb_Kmask },
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/* 1B k0 */ { 0, BX_IA_ERROR },
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/* 1B */ { 0, BX_IA_ERROR },
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/* 1C k0 */ { 0, BX_IA_ERROR },
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@ -1488,8 +1488,8 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
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/* 21 */ { 0, BX_IA_ERROR }, // #UD
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/* 22 k0 */ { 0, BX_IA_ERROR },
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/* 22 */ { 0, BX_IA_ERROR },
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/* 23 k0 */ { BxAliasVexW | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VSHUFF32x4_VpsHpsWpsIb_Kmask },
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/* 23 */ { BxAliasVexW | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VSHUFF32x4_VpsHpsWpsIb_Kmask },
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/* 23 k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VSHUFF32x4_VpsHpsWpsIb_Kmask },
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/* 23 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VSHUFF32x4_VpsHpsWpsIb_Kmask },
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/* 24 k0 */ { 0, BX_IA_ERROR },
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/* 24 */ { 0, BX_IA_ERROR },
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/* 25 k0 */ { BxAliasVexW | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VPTERNLOGD_VdqHdqWdqIb },
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@ -1530,12 +1530,12 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
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/* 36 */ { 0, BX_IA_ERROR },
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/* 37 k0 */ { 0, BX_IA_ERROR },
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/* 37 */ { 0, BX_IA_ERROR },
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/* 38 k0 */ { 0, BX_IA_ERROR },
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/* 38 */ { 0, BX_IA_ERROR },
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/* 38 k0 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTI32x4_VdqHdqWdqIb_Kmask },
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/* 38 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTI32x4_VdqHdqWdqIb_Kmask },
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/* 39 k0 */ { 0, BX_IA_ERROR },
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/* 39 */ { 0, BX_IA_ERROR },
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/* 3A k0 */ { 0, BX_IA_ERROR },
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/* 3A */ { 0, BX_IA_ERROR },
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/* 3A k0 */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTI64x4_VdqHdqWdqIb_Kmask },
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/* 3A */ { BxVexW0 | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTI64x4_VdqHdqWdqIb_Kmask },
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/* 3B k0 */ { 0, BX_IA_ERROR },
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/* 3B */ { 0, BX_IA_ERROR },
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/* 3C k0 */ { 0, BX_IA_ERROR },
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@ -1552,8 +1552,8 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
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/* 41 */ { 0, BX_IA_ERROR },
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/* 42 k0 */ { 0, BX_IA_ERROR },
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/* 42 */ { 0, BX_IA_ERROR },
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/* 43 k0 */ { BxAliasVexW | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VSHUFI32x4_VdqHdqWdqIb_Kmask },
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/* 43 */ { BxAliasVexW | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VSHUFI32x4_VdqHdqWdqIb_Kmask },
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/* 43 k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VSHUFI32x4_VdqHdqWdqIb_Kmask },
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/* 43 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VSHUFI32x4_VdqHdqWdqIb_Kmask },
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/* 44 k0 */ { 0, BX_IA_ERROR },
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/* 44 */ { 0, BX_IA_ERROR },
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/* 45 k0 */ { 0, BX_IA_ERROR },
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@ -2682,6 +2682,12 @@ bx_define_opcode(BX_IA_V512_VMOVQ_VqWq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOV
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bx_define_opcode(BX_IA_V512_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wss, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
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bx_define_opcode(BX_IA_V512_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_ISA_AVX512, OP_Ed, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
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bx_define_opcode(BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF32x4_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wps, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
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bx_define_opcode(BX_IA_V512_VINSERTF64x4_VpdHpdWpdIb_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VINSERTF64x4_MASK_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vpd, OP_Hpd, OP_Wpd, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
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bx_define_opcode(BX_IA_V512_VINSERTI32x4_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF32x4_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
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bx_define_opcode(BX_IA_V512_VINSERTI64x4_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VINSERTF64x4_MASK_VpdHpdWpdIbR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
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// VexW alias
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bx_define_opcode(BX_IA_V512_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE)
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bx_define_opcode(BX_IA_V512_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE)
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