rename one more mem access handler
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@ -797,7 +797,7 @@ BX_CPU_C::read_RMW_virtual_qword_64(unsigned s, Bit64u laddr)
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return data;
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}
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void BX_CPU_C::read_RMW_virtual_dqword_aligned_64(unsigned s, Bit64u laddr, Bit64u *hi, Bit64u *lo)
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void BX_CPU_C::read_RMW_linear_dqword_aligned_64(unsigned s, Bit64u laddr, Bit64u *hi, Bit64u *lo)
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{
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64);
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@ -836,7 +836,7 @@ void BX_CPU_C::read_RMW_virtual_dqword_aligned_64(unsigned s, Bit64u laddr, Bit6
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*hi = data.xmm64u(1);
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}
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void BX_CPU_C::write_RMW_virtual_dqword(Bit64u hi, Bit64u lo)
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void BX_CPU_C::write_RMW_linear_dqword(Bit64u hi, Bit64u lo)
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{
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write_RMW_virtual_qword(lo);
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@ -599,18 +599,18 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG16B(bxInstruction_c *i)
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Bit64u op1_64_lo, op1_64_hi, diff;
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// check write permission for following write
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read_RMW_virtual_dqword_aligned_64(i->seg(), get_laddr64(i->seg(), eaddr), &op1_64_hi, &op1_64_lo);
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read_RMW_linear_dqword_aligned_64(i->seg(), get_laddr64(i->seg(), eaddr), &op1_64_hi, &op1_64_lo);
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diff = RAX - op1_64_lo;
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diff |= RDX - op1_64_hi;
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if (diff == 0) { // if accumulator == dest
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write_RMW_virtual_dqword(RCX, RBX);
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write_RMW_linear_dqword(RCX, RBX);
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assert_ZF();
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}
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else {
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clear_ZF();
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write_RMW_virtual_dqword(op1_64_hi, op1_64_lo);
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write_RMW_linear_dqword(op1_64_hi, op1_64_lo);
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// accumulator <-- dest
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RAX = op1_64_lo;
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RDX = op1_64_hi;
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@ -4525,8 +4525,8 @@ public: // for now...
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BX_SMF Bit32u read_RMW_virtual_dword_64(unsigned seg, Bit64u laddr) BX_CPP_AttrRegparmN(2);
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BX_SMF Bit64u read_RMW_virtual_qword_64(unsigned seg, Bit64u laddr) BX_CPP_AttrRegparmN(2);
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BX_SMF void read_RMW_virtual_dqword_aligned_64(unsigned seg, Bit64u laddr, Bit64u *hi, Bit64u *lo);
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BX_SMF void write_RMW_virtual_dqword(Bit64u hi, Bit64u lo);
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BX_SMF void read_RMW_linear_dqword_aligned_64(unsigned seg, Bit64u laddr, Bit64u *hi, Bit64u *lo);
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BX_SMF void write_RMW_linear_dqword(Bit64u hi, Bit64u lo);
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#endif
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// write of word/dword to new stack could happen only in legacy mode
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