fixed compilation errors with FPU off
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c6969d22cb
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@ -1194,11 +1194,16 @@ void bx_dbg_info_registers_command(int which_regs_mask)
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else
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#endif
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{
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#if BX_SUPPORT_AVX
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if (which_regs_mask & BX_INFO_YMM_REGS) {
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bx_dbg_print_avx_state(BX_VL256);
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}
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else if (which_regs_mask & BX_INFO_SSE_REGS) {
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bx_dbg_print_sse_state();
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else
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#endif
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{
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if (which_regs_mask & BX_INFO_SSE_REGS) {
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bx_dbg_print_sse_state();
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}
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}
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}
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}
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@ -98,9 +98,11 @@ char *resolve_sib_scale(char *disbufptr, const bxInstruction_c *i, const char *r
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{
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unsigned sib_index = i->sibIndex(), sib_scale = i->sibScale();
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#if BX_SUPPORT_AVX
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if (src_index == BX_SRC_VSIB)
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disbufptr = dis_sprintf(disbufptr, "%s%d", intel_vector_reg_name[i->getVL() - 1], sib_index);
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else
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#endif
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disbufptr = dis_sprintf(disbufptr, "%s", regname[sib_index]);
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if (sib_scale)
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@ -403,14 +403,14 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
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/* DE /w */ { BxFPEscape, BX_IA_ERROR, BxOpcodeInfo_FloatingPointDE },
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/* DF /w */ { BxFPEscape, BX_IA_ERROR, BxOpcodeInfo_FloatingPointDF },
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#else
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/* D8 /w */ { 0, BX_IA_FPU_ESC },
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/* D9 /w */ { 0, BX_IA_FPU_ESC },
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/* DA /w */ { 0, BX_IA_FPU_ESC },
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/* DB /w */ { 0, BX_IA_FPU_ESC },
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/* DC /w */ { 0, BX_IA_FPU_ESC },
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/* DD /w */ { 0, BX_IA_FPU_ESC },
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/* DE /w */ { 0, BX_IA_FPU_ESC },
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/* DF /w */ { 0, BX_IA_FPU_ESC },
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/* D8 /w */ { 0, BX_IA_FPUESC },
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/* D9 /w */ { 0, BX_IA_FPUESC },
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/* DA /w */ { 0, BX_IA_FPUESC },
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/* DB /w */ { 0, BX_IA_FPUESC },
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/* DC /w */ { 0, BX_IA_FPUESC },
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/* DD /w */ { 0, BX_IA_FPUESC },
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/* DE /w */ { 0, BX_IA_FPUESC },
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/* DF /w */ { 0, BX_IA_FPUESC },
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#endif
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/* E0 /w */ { BxImmediate_BrOff8, BX_IA_LOOPNE_Op16_Jb },
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/* E1 /w */ { BxImmediate_BrOff8, BX_IA_LOOPE_Op16_Jb },
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@ -948,14 +948,14 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
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/* DE /d */ { BxFPEscape, BX_IA_ERROR, BxOpcodeInfo_FloatingPointDE },
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/* DF /d */ { BxFPEscape, BX_IA_ERROR, BxOpcodeInfo_FloatingPointDF },
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#else
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/* D8 /d */ { 0, BX_IA_FPU_ESC },
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/* D9 /d */ { 0, BX_IA_FPU_ESC },
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/* DA /d */ { 0, BX_IA_FPU_ESC },
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/* DB /d */ { 0, BX_IA_FPU_ESC },
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/* DC /d */ { 0, BX_IA_FPU_ESC },
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/* DD /d */ { 0, BX_IA_FPU_ESC },
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/* DE /d */ { 0, BX_IA_FPU_ESC },
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/* DF /d */ { 0, BX_IA_FPU_ESC },
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/* D8 /d */ { 0, BX_IA_FPUESC },
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/* D9 /d */ { 0, BX_IA_FPUESC },
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/* DA /d */ { 0, BX_IA_FPUESC },
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/* DB /d */ { 0, BX_IA_FPUESC },
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/* DC /d */ { 0, BX_IA_FPUESC },
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/* DD /d */ { 0, BX_IA_FPUESC },
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/* DE /d */ { 0, BX_IA_FPUESC },
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/* DF /d */ { 0, BX_IA_FPUESC },
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#endif
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/* E0 /d */ { BxImmediate_BrOff8, BX_IA_LOOPNE_Op32_Jb },
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/* E1 /d */ { BxImmediate_BrOff8, BX_IA_LOOPE_Op32_Jb },
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@ -1862,7 +1862,11 @@ modrm_done:
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i->setSrcReg(n, rm);
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}
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else {
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i->setSrcReg(n, (type == BX_VMM_REG) ? BX_VECTOR_TMP_REGISTER : BX_TMP_REGISTER);
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unsigned tmpreg = BX_TMP_REGISTER;
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#if BX_SUPPORT_FPU
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if (type == BX_VMM_REG) tmpreg = BX_VECTOR_TMP_REGISTER;
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#endif
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i->setSrcReg(n, tmpreg);
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#if BX_SUPPORT_EVEX
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if (b1 == 0x62 && type == BX_GPR32 && displ8) {
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if (i->as32L())
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