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starting to implement some AVX512 convert opcodes

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This commit is contained in:
Stanislav Shwartsman 2013-12-15 19:20:03 +00:00
parent acd0fe11b5
commit 8707e0626d
4 changed files with 56 additions and 2 deletions
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40
bochs/cpu/avx512_pfp.cc
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@ -272,6 +272,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSD_MASK_VsdHpdWsdR(bxInstruct
BX_NEXT_INSTR(i);
}
// compare
extern float32_compare_method avx_compare32[32];
extern float64_compare_method avx_compare64[32];
@ -363,4 +365,42 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSS_MASK_KGbHssWssIbR(bxInstruc
BX_NEXT_INSTR(i);
}
// convert
#if 0
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTPS2PD_MASK_VpdWpsR(bxInstruction_c *i)
{
BxPackedAvxRegister result;
BxPackedYmmRegister op = BX_READ_YMM_REG(i->src());
unsigned mask = BX_READ_8BIT_OPMASK(i->opmask());
unsigned len = i->getVL();
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
for (unsigned n=0, tmp_mask = mask; n < (2*len); n++, tmp_mask >>= 1) {
if (tmp_mask & 0x1)
result.vmm64u(n) = float32_to_float64(op.ymm32u(n), status);
else
result.vmm64u(n) = 0;
}
check_exceptionsSSE(get_exception_flags(status));
if (! i->isZeroMasking()) {
for (unsigned n=0; n < len; n++, mask >>= 2)
xmm_blendpd(&BX_READ_AVX_REG_LANE(i->dst(), n), &op.vmm128(n), mask);
BX_CLEAR_AVX_REGZ(i->dst(), len);
}
else {
BX_WRITE_AVX_REGZ(i->dst(), op, len);
}
BX_NEXT_INSTR(i);
}
#endif
#endif

3
bochs/cpu/avx_pfp.cc
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@ -135,6 +135,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTSI2SS_VssEdR(bxInstruction_c *
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
op1.xmm32u(0) = int32_to_float32(BX_READ_32BIT_REG(i->src2()), status);
@ -153,6 +154,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTSI2SS_VssEqR(bxInstruction_c *
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
op1.xmm32u(0) = int64_to_float32(BX_READ_64BIT_REG(i->src2()), status);
@ -182,6 +184,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTSI2SD_VsdEqR(bxInstruction_c *
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
op1.xmm64u(0) = int64_to_float64(BX_READ_64BIT_REG(i->src2()), status);

10
bochs/cpu/fetchdecode_evex.h
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@ -142,6 +142,12 @@ static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f29_Mask[2] = {
/* 66 */ { BxVexW1, BX_IA_V512_VMOVAPD_WpdVpd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f2a[3] = {
/* 66 */ { 0, BX_IA_ERROR },
/* F3 */ { BxAliasVexW64, BX_IA_V512_VCVTSI2SS_VssEd },
/* F2 */ { BxAliasVexW64, BX_IA_V512_VCVTSI2SD_VsdEd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f2b[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VMOVNTPS_MpsVps },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVNTPD_MpdVpd }
@ -462,8 +468,8 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 28 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f28_Mask },
/* 29 k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f29 },
/* 29 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f29_Mask },
/* 2A k0 */ { 0, BX_IA_ERROR },
/* 2A */ { 0, BX_IA_ERROR },
/* 2A k0 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2a },
/* 2A */ { 0, BX_IA_ERROR }, // #UD
/* 2B k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2b },
/* 2B */ { 0, BX_IA_ERROR }, // #UD
/* 2C k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2c },

5
bochs/cpu/ia_opcodes.h
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@ -3020,6 +3020,11 @@ bx_define_opcode(BX_IA_V512_VMOVD_VdqEd, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MO
bx_define_opcode(BX_IA_V512_VMOVQ_VdqEq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VdqEqR, BX_ISA_AVX512, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, BX_ISA_AVX512, OP_Ed, OP_Vd, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMOVQ_EqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_EqVqR, BX_ISA_AVX512, OP_Eq, OP_Vq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VCVTSI2SS_VssEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTSI2SS_VssEdR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Ed, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VCVTSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTSI2SS_VssEqR, BX_ISA_AVX512, OP_Vss, OP_Hps, OP_Eq, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VCVTSI2SD_VsdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTSI2SD_VsdEdR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Ed, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST | BX_PREPARE_EVEX_NO_SAE)
bx_define_opcode(BX_IA_V512_VCVTSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTSI2SD_VsdEqR, BX_ISA_AVX512, OP_Vsd, OP_Hpd, OP_Eq, OP_NONE, BX_PREPARE_EVEX_NO_BROADCAST)
// VexW64 aliased
#endif // BX_SUPPORT_EVEX