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split PREFETCH opcode to Group16 for better disasm of bxInstruction_c

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Stanislav Shwartsman 2013-10-15 21:21:28 +00:00
parent 88a1d3f6e7
commit 8bcc8cf073
4 changed files with 26 additions and 5 deletions
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4
bochs/cpu/fetchdecode.cc
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@ -470,7 +470,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 16 /w */ { BxPrefixSSE, BX_IA_MOVHPS_VpsMq, BxOpcodeGroupSSE_0f16 },
/* 0F 17 /w */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupSSE_0f17M },
#if BX_CPU_LEVEL >= 6
/* 0F 18 /w */ { 0, BX_IA_PREFETCH }, // opcode group G16, PREFETCH hints
/* 0F 18 /w */ { BxGroup16, BX_IA_ERROR, BxOpcodeInfoG16 }, // opcode group G16, PREFETCH hints
/* 0F 19 /w */ { 0, BX_IA_NOP }, // multi-byte NOP
/* 0F 1A /w */ { 0, BX_IA_NOP }, // multi-byte NOP
/* 0F 1B /w */ { 0, BX_IA_NOP }, // multi-byte NOP
@ -1015,7 +1015,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 16 /d */ { BxPrefixSSE, BX_IA_MOVHPS_VpsMq, BxOpcodeGroupSSE_0f16 },
/* 0F 17 /d */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupSSE_0f17M },
#if BX_CPU_LEVEL >= 6
/* 0F 18 /d */ { 0, BX_IA_PREFETCH }, // opcode group G16, PREFETCH hints
/* 0F 18 /d */ { BxGroup16, BX_IA_ERROR, BxOpcodeInfoG16 }, // opcode group G16, PREFETCH hints
/* 0F 19 /d */ { 0, BX_IA_NOP }, // multi-byte NOP
/* 0F 1A /d */ { 0, BX_IA_NOP }, // multi-byte NOP
/* 0F 1B /d */ { 0, BX_IA_NOP }, // multi-byte NOP

17
bochs/cpu/fetchdecode.h
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@ -1039,6 +1039,23 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G15q[8*2] = {
};
#endif
/* ******** */
/* Group 16 */
/* ******** */
#if BX_CPU_LEVEL >= 6
static const BxOpcodeInfo_t BxOpcodeInfoG16[8] = {
/* 0 */ { 0, BX_IA_PREFETCHNTA },
/* 1 */ { 0, BX_IA_PREFETCHT0 },
/* 2 */ { 0, BX_IA_PREFETCHT1 },
/* 3 */ { 0, BX_IA_PREFETCHT2 },
/* 4 */ { 0, BX_IA_PREFETCH },
/* 5 */ { 0, BX_IA_PREFETCH },
/* 6 */ { 0, BX_IA_PREFETCH },
/* 7 */ { 0, BX_IA_PREFETCH }
};
#endif
static const BxOpcodeInfo_t BxOpcodeInfoMOV_RdCd[8] = {
/* 0 */ { 0, BX_IA_MOV_RdCR0 },
/* 1 */ { 0, BX_IA_ERROR },

6
bochs/cpu/fetchdecode64.cc
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@ -420,7 +420,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 15 /w */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupSSE_0f15 },
/* 0F 16 /w */ { BxPrefixSSE, BX_IA_MOVHPS_VpsMq, BxOpcodeGroupSSE_0f16 },
/* 0F 17 /w */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupSSE_0f17M },
/* 0F 18 /w */ { 0, BX_IA_PREFETCH }, // opcode group G16, PREFETCH hints
/* 0F 18 /w */ { BxGroup16, BX_IA_ERROR, BxOpcodeInfoG16 }, // opcode group G16, PREFETCH hints
/* 0F 19 /w */ { 0, BX_IA_NOP }, // multi-byte NOP
/* 0F 1A /w */ { 0, BX_IA_NOP }, // multi-byte NOP
/* 0F 1B /w */ { 0, BX_IA_NOP }, // multi-byte NOP
@ -935,7 +935,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 15 /d */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupSSE_0f15 },
/* 0F 16 /d */ { BxPrefixSSE, BX_IA_MOVHPS_VpsMq, BxOpcodeGroupSSE_0f16 },
/* 0F 17 /d */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupSSE_0f17M },
/* 0F 18 /d */ { 0, BX_IA_PREFETCH }, // opcode group G16, PREFETCH hints
/* 0F 18 /d */ { BxGroup16, BX_IA_ERROR, BxOpcodeInfoG16 }, // opcode group G16, PREFETCH hints
/* 0F 19 /d */ { 0, BX_IA_NOP }, // multi-byte NOP
/* 0F 1A /d */ { 0, BX_IA_NOP }, // multi-byte NOP
/* 0F 1B /d */ { 0, BX_IA_NOP }, // multi-byte NOP
@ -1450,7 +1450,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 15 /q */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupSSE_0f15 },
/* 0F 16 /q */ { BxPrefixSSE, BX_IA_MOVHPS_VpsMq, BxOpcodeGroupSSE_0f16 },
/* 0F 17 /q */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupSSE_0f17M },
/* 0F 18 /q */ { 0, BX_IA_PREFETCH }, // opcode group G16, PREFETCH hints
/* 0F 18 /q */ { BxGroup16, BX_IA_ERROR, BxOpcodeInfoG16 }, // opcode group G16, PREFETCH hints
/* 0F 19 /q */ { 0, BX_IA_NOP }, // multi-byte NOP
/* 0F 1A /q */ { 0, BX_IA_NOP }, // multi-byte NOP
/* 0F 1B /q */ { 0, BX_IA_NOP }, // multi-byte NOP

4
bochs/cpu/ia_opcodes.h
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@ -918,6 +918,10 @@ bx_define_opcode(BX_IA_FXRSTOR, &BX_CPU_C::FXRSTOR, &BX_CPU_C::BxError, BX_ISA_S
bx_define_opcode(BX_IA_LDMXCSR, &BX_CPU_C::LDMXCSR, &BX_CPU_C::BxError, BX_ISA_SSE, OP_Md, OP_NONE, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_STMXCSR, &BX_CPU_C::STMXCSR, &BX_CPU_C::BxError, BX_ISA_SSE, OP_Md, OP_NONE, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PREFETCH, &BX_CPU_C::PREFETCH, &BX_CPU_C::NOP, BX_ISA_SSE, OP_Mb, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PREFETCHT0, &BX_CPU_C::PREFETCH, &BX_CPU_C::NOP, BX_ISA_SSE, OP_Mb, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PREFETCHT1, &BX_CPU_C::PREFETCH, &BX_CPU_C::NOP, BX_ISA_SSE, OP_Mb, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PREFETCHT2, &BX_CPU_C::PREFETCH, &BX_CPU_C::NOP, BX_ISA_SSE, OP_Mb, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PREFETCHNTA, &BX_CPU_C::PREFETCH, &BX_CPU_C::NOP, BX_ISA_SSE, OP_Mb, BX_SRC_NNN, OP_NONE, OP_NONE, 0)
// SSE
// SSE and SSE2