mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
10,103 Commits 11 Branches 185 Tags 48 MiB
2dbe81db51
Commit Graph

339 Commits

Author SHA1 Message Date
Stanislav Shwartsman
bd60e0264c change Copyright to Bochs Project 2009-12-04 16:53:12 +00:00
Stanislav Shwartsman
553ca8af01 split more SSE ops 2009-11-25 20:49:47 +00:00
Stanislav Shwartsman
6819ab4eb7 split sse opcodes 2009-11-23 18:21:23 +00:00
Stanislav Shwartsman
5bfbc9df5f RETF bug fuxed 2009-11-19 20:00:35 +00:00
Stanislav Shwartsman
fbd9f291f7 small optimization 2009-11-06 18:19:01 +00:00
Stanislav Shwartsman
6d9271634d bugfix + small optimization 2009-11-05 21:07:18 +00:00
Stanislav Shwartsman
d16afb6d47 ia_opcodes instrumentation 2009-10-31 20:02:44 +00:00
Stanislav Shwartsman
78e4b3d616 split SSE move instructions 2009-10-24 11:17:51 +00:00
Stanislav Shwartsman
8e3276cf14 split opcodes by ModC0 2009-08-22 11:47:42 +00:00
Stanislav Shwartsman
9d4c24b6a3 Split instruction 32/64 2009-04-06 18:44:28 +00:00
Stanislav Shwartsman
e5be60be64 Fixed lazy flags bug I added in one of my prev merges 
ICACHE code reorganization
 2009-03-22 21:12:35 +00:00
Stanislav Shwartsman
9417cbee63 - cpu optimizations 9remove redundant, add new) 2009-03-13 18:02:33 +00:00
Stanislav Shwartsman
6dac964b27 Two more prefix66 opcodes 2009-02-28 09:28:18 +00:00
Stanislav Shwartsman
b9de22961c minimize SSE tables, minor speedup in SSE code 2009-02-26 21:57:01 +00:00
Stanislav Shwartsman
21e2692997 Fixed bug in trace cache mode 2009-02-06 15:03:47 +00:00
Stanislav Shwartsman
f8185a6bc6 Added Intel VMX emulation to Bochs CPU 2009-01-31 10:43:24 +00:00
Stanislav Shwartsman
0325c120b2 Separate PAUSE instruction from regular NOP 2009-01-27 20:29:05 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
0ff68a2aa2 Fixed XSAVE decode in x86-64 mode 2009-01-10 16:01:55 +00:00
Stanislav Shwartsman
a9c77eb75d Try to optimize individual instructions after fetchdecode 2008-09-16 19:20:03 +00:00
Stanislav Shwartsman
7566faf948 A bit simplify FPU decoding 2008-09-16 18:28:53 +00:00
Stanislav Shwartsman
d57a211df9 Fixed handling of prefixes for EMMS 
Small FPU optimization
 2008-09-12 20:59:31 +00:00
Stanislav Shwartsman
b03f940807 optimize seg_override decoding 2008-09-08 16:15:59 +00:00
Stanislav Shwartsman
c1306f7d75 small non-significant speedups 2008-09-06 21:10:40 +00:00
Stanislav Shwartsman
b3b2f77675 Reduce size of Bochs static tables by changing from bx_bool (which is 32bit) to Bit8u 2008-09-06 18:21:29 +00:00
Stanislav Shwartsman
0cd11fd385 Updated instrumentation callbacks - removed fetchdecode_completed callback 2008-09-06 17:49:32 +00:00
Stanislav Shwartsman
a0e395188f Fixed merge error 2008-08-29 20:43:05 +00:00
Stanislav Shwartsman
b96f78dc0a Some kind of big change in fetchdecode tables invented in order to compress the tables for better host data cache utilization 2008-08-29 19:23:03 +00:00
Stanislav Shwartsman
9a2072bba6 More fetchdecode optimization 2008-08-23 22:34:17 +00:00
Stanislav Shwartsman
991ae348cb Clean invalidate_prefetch_q when not needed 2008-08-23 13:55:37 +00:00
Stanislav Shwartsman
a8adb36dc2 Implemented MOVBE Intel Atom(R) instruction 2008-08-11 18:53:24 +00:00
Stanislav Shwartsman
b61017e5b6 Split more opcodes using new LOAD technique 2008-08-10 21:16:12 +00:00
Stanislav Shwartsman
1da5943f1a More use of LOAD_Ex method 2008-08-10 19:34:28 +00:00
Stanislav Shwartsman
0d90ab0478 Completely new way to handle LD+OP cases - allows to significantly reduce number of BX_CPU_C methods 2008-08-09 21:05:07 +00:00
Stanislav Shwartsman
24e0b53720 This more ellegant way to have debug info for BxError and not lose any performace 2008-08-09 19:18:09 +00:00
Stanislav Shwartsman
0127415ba6 Clear some duplicated arithmetic opcodes - difference only in operands order 2008-07-13 09:59:59 +00:00
Stanislav Shwartsman
65275ffc02 Remove repeat speedups from 16-bit address size methods - they not gonna speed up anyway because of segment limit issue 2008-06-25 10:34:21 +00:00
Stanislav Shwartsman
a6fda9a971 Instrumentation code updated, some PANIC messages fixed 2008-06-23 02:56:31 +00:00
Stanislav Shwartsman
678ac970aa Reorganize ctrl_xfer8.cc code, allows to inline branch32 method 2008-06-22 03:45:55 +00:00
Stanislav Shwartsman
7f82a536b3 Fixed code duplication during prefix decoding 2008-06-11 20:58:29 +00:00
Stanislav Shwartsman
aff775bce4 Small code optimization 2008-06-09 19:35:59 +00:00
Stanislav Shwartsman
16d073bf51 Fixed recently introduced PUSH_Eq decoding bug 2008-05-08 21:34:22 +00:00
Stanislav Shwartsman
ed4be45a8b Split shift/rotate opcodes in 32-bit mode and 64-bit mode 2008-05-02 22:47:07 +00:00
Stanislav Shwartsman
81deffd65d More fetchdecode fixes 2008-04-30 21:32:33 +00:00
Stanislav Shwartsman
e5b6f90b62 some fetchdecode fixes 2008-04-30 21:07:12 +00:00
Stanislav Shwartsman
64f2489afb Correctly implement opcode group G11 i.e. instructions C6 and C7 should @UD when modrm nnn field != 0 (1st instr in the group 2008-04-24 21:52:28 +00:00
Stanislav Shwartsman
eea58f04cd Fixed ret_near decoding in 64-bit mode 2008-04-18 13:11:52 +00:00
Stanislav Shwartsman
c611d9aca0 Fixed LEAVE in 64-bit mode 2008-04-16 21:35:43 +00:00
Stanislav Shwartsman
892fa99c6f - prefetch hint should be NOP when use in register mode 
- #GP when trying to set reserved bits of CR4_HI in 64-bit mode
- #GP when trying to set reserved bits of EFER MSR
- clear upper part of RSI/RDI when executing rep instructions with 32-bit asize
  even if no repeat iterations were executed (because of RCX=0 for example)
- write SYSENTER_EIP_MSR and SYSENTER_ESP_MSR as 64-bit when x86_64 supported
- set MSR_FMASK reset value
- MSR_FMASK should be 32-bit only
- check for fetch permissions when doing ITLB lookup
- #GP when trying to write non-canonical address to MSR_CSTAR or MSR_LSTAR
- correct repeat instructions timing
- mark TSS busy in TR after it is loaded
 2008-04-16 16:44:06 +00:00
Stanislav Shwartsman
419dc57dbd Complete MASKMOVDQU decoding fix 2008-04-16 05:56:55 +00:00
Stanislav Shwartsman
4f3f8608f7 Fixed MASKMOVDQU instruction decoding 2008-04-16 05:41:43 +00:00
Stanislav Shwartsman
fab4042cad SYSENTER/SYSEXIT in long mode 2008-04-15 14:41:50 +00:00
Stanislav Shwartsman
1bdddc1f78 Split SHRD/SHLD instructions 2008-04-05 19:08:01 +00:00
Stanislav Shwartsman
5826e2843a Inline pop/push functions 
Store only single byte of opcode in b1() - speedup shift instructions
Code cleanups
 2008-04-05 17:51:55 +00:00
Stanislav Shwartsman
2aaafa76a2 Reorganize fetchdecode tables with another level of redirection - a leap toward future improvements 
Currently no speedup and no slowdown - about the same results on my Bochs benchmarking
A lot of code reorganization in fetchdecode
 2008-04-04 22:39:45 +00:00
Stanislav Shwartsman
62e3728591 preparations for future optimizations - not necessary speedupo now 2008-04-03 17:56:59 +00:00
Stanislav Shwartsman
3f2487a0af Enabled tracing cross repeated instructions 2008-03-31 18:53:08 +00:00
Stanislav Shwartsman
255d512e29 Organize bxInstruction fields differently 2008-03-31 17:33:34 +00:00
Stanislav Shwartsman
14ff07b482 Small code cleanup 2008-03-29 09:58:23 +00:00
Stanislav Shwartsman
e48b398bee Add NIL register and simplify more BxResolve work 2008-03-29 09:34:35 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
7e490699d4 Removing hooks for not-implemented SSE4A from the Bochs code. 2008-03-21 20:04:42 +00:00
Stanislav Shwartsman
946b7a369d Added const to fetchPtr in cpu functions 2008-03-03 15:16:46 +00:00
Stanislav Shwartsman
5e7218b8c3 Fixed problem introduced by prev checkin 
+
Fix beak to debugger when executing HLT instruction
 2008-02-29 05:39:40 +00:00
Stanislav Shwartsman
405fcfd75d Reorganize 3-byte opcode tables - bigger tables but easier to maintain them 2008-02-29 03:02:03 +00:00
Stanislav Shwartsman
cdcd7522aa Added RIP to the GPR register file as lst register 
This allowed to optimize (read - remove) two more BxResolve methods in 64-bit mode
+ Some white space cleanup
 2008-02-15 19:03:54 +00:00
Stanislav Shwartsman
0f44b4f0ec Fixes in MODRM tables 2008-02-15 12:23:49 +00:00
Stanislav Shwartsman
4fc0df26e8 a bit optimize and simplify x87 decoding 2008-02-14 18:59:41 +00:00
Stanislav Shwartsman
fb0ce45d28 Unpack more fields in bxInstruction_c -> this increase bxInstruction size by 4 bytes but I have no way but do it if want to support SSE5 dest override later 2008-02-04 21:28:53 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
37fbb82baa Cleanups. Move bxInstruction_c definition to separate file instr.h 2008-01-29 17:13:10 +00:00
Stanislav Shwartsman
7b80c5f481 I merged and succeded to remove some similar execution functions - less code, less chance for branch misprediction 2008-01-25 19:34:30 +00:00
Stanislav Shwartsman
63d8d50cfc code cleanup 2008-01-20 20:11:17 +00:00
Stanislav Shwartsman
8c9de8b4db speculative tracing on fetchdecode level 2008-01-18 09:36:15 +00:00
Stanislav Shwartsman
d9984bb3a1 Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup ! 2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
eee1a9030d a bit simplify and optimize shift instructions 
print failed segment info in check_cs - more debug info
 2007-12-30 20:16:35 +00:00
Stanislav Shwartsman
c3c9c40674 Move MaxFetch calculation into fetchdecode - simplify the logic 2007-12-22 17:17:40 +00:00
Stanislav Shwartsman
e9a148f9c4 lmost last instruction split -> CMOV in 16/32 bit modes 2007-12-21 18:24:19 +00:00
Stanislav Shwartsman
c9932e97eb Fixes in resolve.cc -> reduce amount of resolve functions even more 2007-12-18 21:41:44 +00:00
Stanislav Shwartsman
fe2e0525da More optimization for string instructions 2007-12-17 19:52:01 +00:00
Stanislav Shwartsman
de5838ce80 cleanups and fixes for Immediate_IbIb of SSE4A 2007-12-16 20:47:10 +00:00
Stanislav Shwartsman
1e843cb462 Decode SSE4A 
Rework immediate bytes decoding to make it faster
 2007-12-15 17:42:24 +00:00
Stanislav Shwartsman
fd73390ca5 Split 64-bit CMOVcc opcode 2007-12-14 22:41:43 +00:00
Stanislav Shwartsman
903f6dea35 Split setCC functions - makes code faster and simpler 2007-12-14 21:29:36 +00:00
Stanislav Shwartsman
05c7a1e61b Fixed problem with trace cache enabled 
String instructions might confise trace cache by finishing instruction execution method without actually completing an instruction (and advancing eip)
 2007-12-13 18:42:31 +00:00
Stanislav Shwartsman
adda3befd3 Trace cache optimization merged 2007-12-09 18:36:05 +00:00
Stanislav Shwartsman
4c16dd71a8 Fixed compilation error in SMP mode 2007-12-07 09:38:42 +00:00
Stanislav Shwartsman
1bcf42baec oops, fixed incorrect checkin 2007-12-01 16:59:36 +00:00
Stanislav Shwartsman
7ca78b88e9 configure/compile changes + small optimizations 2007-12-01 16:45:17 +00:00
Stanislav Shwartsman
8cfd17202a some simple SSE code optimizations 2007-11-27 22:12:45 +00:00
Stanislav Shwartsman
c51888f43f Split last BxLockable opcodes -> this allows to eliminate mod==0xc0 check from fetchdecode of every instruction 
reduce ACPU.CC dependencies - now that file doesn't depend of CPU
 2007-11-25 20:22:10 +00:00
Stanislav Shwartsman
e51184c8cf Eliminate saving of RSP from heart of cpu_loop 
Now save RSP only where it is really required
 2007-11-24 14:22:34 +00:00
Stanislav Shwartsman
3daa468c02 Fixed comments in bit.cc 
Revert back lock prefix changes in fetchdecode - not all lockable instructions are splitted yet ;(
 2007-11-23 16:37:06 +00:00
Stanislav Shwartsman
1dbe51a2fb Split ENTER_IwBw function according to os32. Fixed ENTER/LEAVE in 64-bit mode 2007-11-22 17:33:06 +00:00
Stanislav Shwartsman
0a1063ad77 Split GvEv opcode groups 2007-11-21 22:36:02 +00:00
Stanislav Shwartsman
506dc3d963 Optimize 64-bit fetchdecode prefix handling 
Deparecated set_FLAG() method, setB_FLAG() method was used everywhere
Rename setB_FLAG to set_FLAG, so set_FLAG() will must receive 0/1 inly
 2007-11-20 23:00:44 +00:00
Stanislav Shwartsman
d75a69fd2e Remove BxResolve tables 2007-11-18 22:14:39 +00:00
Stanislav Shwartsman
fb61418307 optimize modrm/sib decoding 2007-11-18 21:38:58 +00:00
Stanislav Shwartsman
30f42d74f1 make sreg index tables static in fetchdecode and remove them from init.cc/cpu.h 2007-11-18 21:07:40 +00:00
Stanislav Shwartsman
1e0db62984 bit.cc speedup (small) 2007-11-18 20:21:34 +00:00
Stanislav Shwartsman
bcaba54489 Merge resolve functions for 32 and 64-bit 2007-11-18 19:46:14 +00:00
Stanislav Shwartsman
57d2d14865 Split POP_Ev opcodes 2007-11-18 18:49:19 +00:00
Stanislav Shwartsman
cdc9a09090 Split more opcodes 2007-11-18 18:24:46 +00:00
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :) 
Also split EqId G1 group for x86-64
 2007-11-17 23:28:33 +00:00
Stanislav Shwartsman
613bad34ee split MOVZX/MOVSX opcodes 2007-11-17 18:29:00 +00:00
Stanislav Shwartsman
5ec15df46d Split more opcodes EbIb opcodes 2007-11-17 18:08:46 +00:00
Stanislav Shwartsman
d5a58e1df2 Split more opcodes - G3 group 2007-11-17 16:20:37 +00:00
Stanislav Shwartsman
d9e58bd598 split11b on opcode tables level - split almost eevery splittable instruction 
will be continued
 2007-11-17 12:44:10 +00:00
Stanislav Shwartsman
abe3f4c5c2 Split one more opcode 2007-11-16 21:43:23 +00:00
Stanislav Shwartsman
b4b922809a Move 3byte opcode decoding under Modrm condition 2007-11-16 20:49:51 +00:00
Stanislav Shwartsman
565e7f9868 Merge common fetchdecode groups. Add more comments to fetchdecode tables 2007-11-16 18:34:14 +00:00
Stanislav Shwartsman
393018cdf8 More split11b 2007-11-16 17:45:58 +00:00
Stanislav Shwartsman
351244d1ea Rename splitmod11b methods 2007-11-16 08:30:22 +00:00
Stanislav Shwartsman
db02731cbf Replace BxAnother attribute in fetchdecode by table lookup like it is done in disasm. This is done in preparation to feature huge fetchdecode change - all fethdecode tables will be duplicated and made separatate table for ModC0 and others. 
So ALL instructions will emjoy SplitMod11b automatically (if they want).
After splitting ALL instruction I hope to get 20% speedup at least.
 2007-11-15 17:57:56 +00:00
Stanislav Shwartsman
9da22f9b65 Remove redundant BxAnother attr from prefixes 
The meaning of BxAnother attr - instryction has modrm byte
 2007-11-14 22:52:16 +00:00
Stanislav Shwartsman
0fa82afe1f Bugfix and optimize BxResolve calls - bugfix in 64-bit mode 2007-11-13 17:30:54 +00:00
Stanislav Shwartsman
edfff23ca0 Split JCC methods to 16 different methods per branch condition 2007-11-12 18:20:15 +00:00
Stanislav Shwartsman
aed6640ef4 speedup JCC for 64-bit -> separate JZ/JNZ for single faster methods 2007-11-11 21:26:10 +00:00
Stanislav Shwartsman
eea5023da8 small simplification for fetchdecode 2007-11-11 20:56:22 +00:00
Stanislav Shwartsman
2653d54e96 split 32-bit modermdata variable in BxInstruction_c to 4 Bit8u variables 
this way it is possible to save shifts and masking when accessing modrm fields
 2007-11-08 18:21:37 +00:00
Stanislav Shwartsman
2f5fa07af3 small speedups 2007-11-07 10:40:40 +00:00
Stanislav Shwartsman
292153b30e Fixed BranchImm cases in 64-bit mode 2007-10-22 17:41:41 +00:00
Stanislav Shwartsman
5445de19d1 Decoding : F2 and F2 prefix could override prefix 66 when determine SSE opcode 2007-10-20 10:56:44 +00:00
Stanislav Shwartsman
be9ad60ef3 cleanups 2007-10-11 22:44:17 +00:00
Stanislav Shwartsman
8adbbcf17c Started first implementation of MONITOR/MWAIT 2007-10-11 21:29:01 +00:00
Stanislav Shwartsman
0dc4badfbb Added SSE4A and SSE4_2 to disassembler 
Implemented POPCNT instruction
 2007-09-19 19:38:10 +00:00
Stanislav Shwartsman
b64fc08c54 implement prefetch hint opcodes 2007-08-23 16:47:51 +00:00
Stanislav Shwartsman
4555cc9be3 ud2b opcode should have modrm byte 2007-08-18 13:51:16 +00:00
Stanislav Shwartsman
5189cfbf10 SSE4 support 2007-04-19 16:12:21 +00:00
Stanislav Shwartsman
223b9fda0e Fixed RIP relative mode when in 32-bit address size 2007-04-09 21:15:00 +00:00
Stanislav Shwartsman
e26609fa97 Support for Intel LSS/LFS/LGS in 64-bit mode 
TODO: have both AMD and Intelk versions
 2007-04-09 20:28:15 +00:00
Stanislav Shwartsman
bdc4905c8a Correctly detect SSE2 and SSE instructions and #UD when SSE2 is OFF for SSE 2007-04-02 10:46:33 +00:00
Stanislav Shwartsman
4bb19c2dc3 Fixed deciding and disasm of CALL in 64-bit mode (no 16-bit calls allowed) 2007-03-28 21:20:09 +00:00
Stanislav Shwartsman
ef542b3790 Learn to decode and disassemble VMX opcodes 
No fetchdecode support but everything is ready
 2007-03-23 14:35:50 +00:00
Stanislav Shwartsman
c24627c00f Implemented CLFLUSH instruction 
Set of minor fixes for correctness
 2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
8221fa6838 - Fixed zero upper 32-bit part of GPR in x86-64 mode 
- CMOV_GdEd should zero upper 32-bit part of GPR register even if the
    'cmov' condition was false !
 2007-01-26 22:12:05 +00:00
Stanislav Shwartsman
f8003098b1 Rename SSE4 to SSE3E to match intel docs. SSE4 coming later ;) 
Fixed "last prefix" for REX in 64-bit mode
 2007-01-25 19:09:41 +00:00
Stanislav Shwartsman
9db896d100 minor x86_64 fixes and cleanups 2007-01-12 22:47:21 +00:00
Stanislav Shwartsman
5c21f7821f Speed simulation between 3 to 5% by eliminating several checks from cpu loop. 
The checks were related to repeat instructions - handle them differently
 2007-01-05 13:40:47 +00:00
Stanislav Shwartsman
3ce7764fce Fixes in 64-bit decoding 2006-08-11 17:23:36 +00:00
Stanislav Shwartsman
45353d5e6f Fixed DR registers handling in x86-64 mode 2006-06-26 21:07:44 +00:00
Stanislav Shwartsman
6c3420a18b Add debug prints before any #GP excepion which only possible to be generated 2006-06-09 22:29:07 +00:00
Stanislav Shwartsman
a4129e5341 Handle NULL_SEG_REG (no segment override) case in fetchdecode.cc 2006-05-24 20:57:37 +00:00
Stanislav Shwartsman
fc799ab623 FetchDecode tables are constant. Marking them const implicitly will help to compiler/linker in optimization. 2006-05-12 18:03:26 +00:00
Stanislav Shwartsman
fe644dfcbf - Code cleanup, remove x86-64 code from functions which cannot be called from x86-64 
- Fix PANIC multiple SSE prefix decoding (fetchdecode and disasm)
- More Bit32u -> bx_phy_address convert
- Lazy flags optimization
 2006-05-12 17:04:19 +00:00
Stanislav Shwartsman
20b14aefa6 Fix in BSWAP 64-bit mode - allow to use additional R8-R15 registers 
Also fixed code duplication story with BSWAP instruction
 2006-05-07 18:58:47 +00:00
Stanislav Shwartsman
d69eba6c07 Split in/out instructions based on operand size 2006-05-07 18:27:36 +00:00
Stanislav Shwartsman
03eac64013 Added decoding of new SSE4 instructions (recently published in Intel docs) 
At least CPUID detects them correctly
The code is never tested (still) ! (but should work fine)
 2006-04-06 18:30:05 +00:00
Stanislav Shwartsman
9dc1790f07 Simplify and optimize fetchdecode methods. 
Now fetchdecode is simpler to understand and easier to modify, for example to support 3-byte opcodes (SSE4)
 2006-04-05 20:52:40 +00:00
Stanislav Shwartsman
f8c3968d42 Changes list made after CVS service crash: 
- Fixed critical bug in CPU code added with one of the prev commits
  - Disasm support for SSE4
  - Rename PNI->SSE3 everywhere in the code
  - Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
  - Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
  - Fixed ENTER and LEAVE instructions in x86-64 mode
  - Added ability to turn ON instruction trace, only GUI support is missed.
    Instruction trace could be enabled if Bochs was compiled with disasm
  - More changes Bit32u -> bx_phy_address
  - Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
  - Small code cleanup
  - Update CHANGES and user docs
 2006-04-05 17:31:35 +00:00