split sse opcodes
This commit is contained in:
Stanislav Shwartsman
parent
8dcdc7f9ef
commit
6819ab4eb7
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.621 2009-11-19 20:00:34 sshwarts Exp $
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// $Id: cpu.h,v 1.622 2009-11-23 18:21:23 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1952,8 +1952,9 @@ public: // for now...
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BX_SMF void ANDNPS_VpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVUPS_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVUPS_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVSS_VssWss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVSS_WssVss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVSS_VssWssM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVSS_WssVssM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVLPS_VpsMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVLPS_MqVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVHPS_VpsMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2013,8 +2014,8 @@ public: // for now...
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/* SSE */
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/* SSE2 */
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BX_SMF void MOVSD_VsdWsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVSD_WsdVsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVSD_WsdVsdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPI2PD_VpdQqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPI2PD_VpdQqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSI2SD_VsdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2061,14 +2062,16 @@ public: // for now...
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BX_SMF void PACKSSDW_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PUNPCKLQDQ_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PUNPCKHQDQ_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVD_VdqEd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVD_VdqEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PSHUFD_VdqWdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PSHUFHW_VdqWdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PCMPEQB_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PCMPEQW_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PCMPEQD_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVD_EdVd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVQ_VqWq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVD_EdVdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVD_EdVdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVQ_VqWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVQ_VqWqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CMPPD_VpdWpdIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CMPSD_VsdWsdIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVNTI_MdGd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2730,10 +2733,10 @@ public: // for now...
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BX_SMF void JRCXZ_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVQ_EqPq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVQ_EqVq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVQ_EqVqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVQ_PqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVQ_PqEqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVQ_VdqEq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVQ_VdqEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVNTI_MqGq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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#endif // #if BX_SUPPORT_X86_64
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.234 2009-11-19 20:00:34 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.235 2009-11-23 18:21:23 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -621,7 +621,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* 0F 6B /wr */ { BxPrefixSSE, BX_IA_PACKSSDW_PqQq, BxOpcodeGroupSSE_0f6b },
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/* 0F 6C /wr */ { BxPrefixSSE66, BX_IA_PUNPCKLQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
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/* 0F 6D /wr */ { BxPrefixSSE66, BX_IA_PUNPCKHQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
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/* 0F 6E /wr */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6e },
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/* 0F 6E /wr */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6eR },
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/* 0F 6F /wr */ { BxPrefixSSE, BX_IA_MOVQ_PqQq, BxOpcodeGroupSSE_0f6fR },
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/* 0F 70 /wr */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PSHUFW_PqQqIb, BxOpcodeGroupSSE_0f70 },
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/* 0F 71 /wr */ { BxGroup12, BX_IA_ERROR, BxOpcodeInfoG12R },
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@ -637,7 +637,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* 0F 7B /wr */ { 0, BX_IA_ERROR },
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/* 0F 7C /wr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
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/* 0F 7D /wr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
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/* 0F 7E /wr */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
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/* 0F 7E /wr */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7eR },
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/* 0F 7F /wr */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7fR },
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/* 0F 80 /wr */ { BxImmediate_BrOff16 | BxTraceJCC, BX_IA_JO_Jw },
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/* 0F 81 /wr */ { BxImmediate_BrOff16 | BxTraceJCC, BX_IA_JNO_Jw },
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@ -1184,7 +1184,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* 0F 6B /dr */ { BxPrefixSSE, BX_IA_PACKSSDW_PqQq, BxOpcodeGroupSSE_0f6b },
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/* 0F 6C /dr */ { BxPrefixSSE66, BX_IA_PUNPCKLQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
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/* 0F 6D /dr */ { BxPrefixSSE66, BX_IA_PUNPCKHQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
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/* 0F 6E /dr */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6e },
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/* 0F 6E /dr */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6eR },
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/* 0F 6F /dr */ { BxPrefixSSE, BX_IA_MOVQ_PqQq, BxOpcodeGroupSSE_0f6fR },
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/* 0F 70 /dr */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PSHUFW_PqQqIb, BxOpcodeGroupSSE_0f70 },
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/* 0F 71 /dr */ { BxGroup12, BX_IA_ERROR, BxOpcodeInfoG12R },
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@ -1200,7 +1200,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
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/* 0F 7B /dr */ { 0, BX_IA_ERROR },
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/* 0F 7C /dr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
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/* 0F 7D /dr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
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/* 0F 7E /dr */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
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/* 0F 7E /dr */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7eR },
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/* 0F 7F /dr */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7fR },
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/* 0F 80 /dr */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jd },
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/* 0F 81 /dr */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jd },
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@ -1754,7 +1754,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* 0F 6B /wm */ { BxPrefixSSE, BX_IA_PACKSSDW_PqQq, BxOpcodeGroupSSE_0f6b },
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/* 0F 6C /wm */ { BxPrefixSSE66, BX_IA_PUNPCKLQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
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/* 0F 6D /wm */ { BxPrefixSSE66, BX_IA_PUNPCKHQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
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/* 0F 6E /wm */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6e },
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/* 0F 6E /wm */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6eM },
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/* 0F 6F /wm */ { BxPrefixSSE, BX_IA_MOVQ_PqQq, BxOpcodeGroupSSE_0f6fM },
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/* 0F 70 /wm */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PSHUFW_PqQqIb, BxOpcodeGroupSSE_0f70 },
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/* 0F 71 /wm */ { 0, BX_IA_ERROR }, // SSE Group G12
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@ -1770,7 +1770,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* 0F 7B /wm */ { 0, BX_IA_ERROR },
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/* 0F 7C /wm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
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/* 0F 7D /wm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
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/* 0F 7E /wm */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
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/* 0F 7E /wm */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7eM },
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/* 0F 7F /wm */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7fM },
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/* 0F 80 /wm */ { BxImmediate_BrOff16 | BxTraceJCC, BX_IA_JO_Jw },
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/* 0F 81 /wm */ { BxImmediate_BrOff16 | BxTraceJCC, BX_IA_JNO_Jw },
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@ -2317,7 +2317,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* 0F 6B /dm */ { BxPrefixSSE, BX_IA_PACKSSDW_PqQq, BxOpcodeGroupSSE_0f6b },
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/* 0F 6C /dm */ { BxPrefixSSE66, BX_IA_PUNPCKLQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
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/* 0F 6D /dm */ { BxPrefixSSE66, BX_IA_PUNPCKHQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
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/* 0F 6E /dm */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6e },
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/* 0F 6E /dm */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6eM },
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/* 0F 6F /dm */ { BxPrefixSSE, BX_IA_MOVQ_PqQq, BxOpcodeGroupSSE_0f6fM },
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/* 0F 70 /dm */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PSHUFW_PqQqIb, BxOpcodeGroupSSE_0f70 },
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/* 0F 71 /dm */ { 0, BX_IA_ERROR }, // SSE Group G12
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@ -2333,7 +2333,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
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/* 0F 7B /dm */ { 0, BX_IA_ERROR },
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/* 0F 7C /dm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
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/* 0F 7D /dm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
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/* 0F 7E /dm */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
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/* 0F 7E /dm */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7eM },
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/* 0F 7F /dm */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7fM },
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/* 0F 80 /dm */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jd },
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/* 0F 81 /dm */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jd },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.h,v 1.91 2009-11-04 15:48:27 sshwarts Exp $
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// $Id: fetchdecode.h,v 1.92 2009-11-23 18:21:23 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2009 Stanislav Shwartsman
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@ -1007,26 +1007,26 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_PAUSE[3] = {
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f10R[3] = {
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/* 66 */ { 0, BX_IA_MOVUPD_VpdWpdR },
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/* F2 */ { 0, BX_IA_MOVSD_VsdWsd },
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/* F3 */ { 0, BX_IA_MOVSS_VssWss }
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/* F2 */ { 0, BX_IA_MOVSD_VsdWsdR },
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/* F3 */ { 0, BX_IA_MOVSS_VssWssR }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f10M[3] = {
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/* 66 */ { 0, BX_IA_MOVUPD_VpdWpdM },
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/* F2 */ { 0, BX_IA_MOVSD_VsdWsd },
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/* F3 */ { 0, BX_IA_MOVSS_VssWss }
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/* F2 */ { 0, BX_IA_MOVSD_VsdWsdM },
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/* F3 */ { 0, BX_IA_MOVSS_VssWssM }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f11R[3] = {
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/* 66 */ { 0, BX_IA_MOVUPD_WpdVpdR },
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/* F2 */ { 0, BX_IA_MOVSD_WsdVsd },
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/* F3 */ { 0, BX_IA_MOVSS_WssVss }
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/* F2 */ { BxArithDstRM, BX_IA_MOVSD_VsdWsdR },
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/* F3 */ { BxArithDstRM, BX_IA_MOVSS_VssWssR }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f11M[3] = {
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/* 66 */ { 0, BX_IA_MOVUPD_WpdVpdM },
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/* F2 */ { 0, BX_IA_MOVSD_WsdVsd },
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/* F3 */ { 0, BX_IA_MOVSS_WssVss }
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/* F2 */ { 0, BX_IA_MOVSD_WsdVsdM },
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/* F3 */ { 0, BX_IA_MOVSS_WssVssM }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f12[3] = {
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@ -1299,15 +1299,27 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f6b[3] = {
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/* F3 */ { 0, BX_IA_ERROR }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f6e[3] = {
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/* 66 */ { 0, BX_IA_MOVD_VdqEd },
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f6eR[3] = {
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/* 66 */ { 0, BX_IA_MOVD_VdqEdR },
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/* F2 */ { 0, BX_IA_ERROR },
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/* F3 */ { 0, BX_IA_ERROR }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f6eM[3] = {
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/* 66 */ { 0, BX_IA_MOVD_VdqEdM },
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/* F2 */ { 0, BX_IA_ERROR },
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/* F3 */ { 0, BX_IA_ERROR }
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};
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#if BX_SUPPORT_X86_64
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f6eQ[3] = {
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/* 66 */ { 0, BX_IA_MOVQ_VdqEq },
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f6eQR[3] = {
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/* 66 */ { 0, BX_IA_MOVQ_VdqEqR },
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/* F2 */ { 0, BX_IA_ERROR },
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/* F3 */ { 0, BX_IA_ERROR }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f6eQM[3] = {
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/* 66 */ { 0, BX_IA_MOVQ_VdqEqM },
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/* F2 */ { 0, BX_IA_ERROR },
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/* F3 */ { 0, BX_IA_ERROR }
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};
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@ -1361,17 +1373,29 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7d[3] = {
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/* F3 */ { 0, BX_IA_ERROR }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7e[3] = {
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/* 66 */ { 0, BX_IA_MOVD_EdVd },
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7eR[3] = {
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/* 66 */ { 0, BX_IA_MOVD_EdVdR },
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/* F2 */ { 0, BX_IA_ERROR },
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/* F3 */ { 0, BX_IA_MOVQ_VqWq }
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/* F3 */ { 0, BX_IA_MOVQ_VqWqR }
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};
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7eM[3] = {
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/* 66 */ { 0, BX_IA_MOVD_EdVdM },
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/* F2 */ { 0, BX_IA_ERROR },
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/* F3 */ { 0, BX_IA_MOVQ_VqWqM }
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};
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#if BX_SUPPORT_X86_64
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7eQ[3] = {
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/* 66 */ { 0, BX_IA_MOVQ_EqVq },
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static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7eQR[3] = {
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/* 66 */ { 0, BX_IA_MOVQ_EqVqR },
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/* F2 */ { 0, BX_IA_ERROR },
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/* F3 */ { 0, BX_IA_MOVQ_VqWq }
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/* F3 */ { 0, BX_IA_MOVQ_VqWqR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f7eQM[3] = {
|
||||
/* 66 */ { 0, BX_IA_MOVQ_EqVqM },
|
||||
/* F2 */ { 0, BX_IA_ERROR },
|
||||
/* F3 */ { 0, BX_IA_MOVQ_VqWqM }
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: fetchdecode64.cc,v 1.236 2009-11-19 20:00:34 sshwarts Exp $
|
||||
// $Id: fetchdecode64.cc,v 1.237 2009-11-23 18:21:23 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -560,7 +560,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F 6B /wr */ { BxPrefixSSE, BX_IA_PACKSSDW_PqQq, BxOpcodeGroupSSE_0f6b },
|
||||
/* 0F 6C /wr */ { BxPrefixSSE66, BX_IA_PUNPCKLQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6D /wr */ { BxPrefixSSE66, BX_IA_PUNPCKHQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6E /wr */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6e },
|
||||
/* 0F 6E /wr */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6eR },
|
||||
/* 0F 6F /wr */ { BxPrefixSSE, BX_IA_MOVQ_PqQq, BxOpcodeGroupSSE_0f6fR },
|
||||
/* 0F 70 /wr */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PSHUFW_PqQqIb, BxOpcodeGroupSSE_0f70 },
|
||||
/* 0F 71 /wr */ { BxGroup12, BX_IA_ERROR, BxOpcodeInfoG12R },
|
||||
@ -576,7 +576,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F 7B /wr */ { 0, BX_IA_ERROR },
|
||||
/* 0F 7C /wr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /wr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /wr */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7E /wr */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7eR },
|
||||
/* 0F 7F /wr */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7fR },
|
||||
/* 0F 80 /wr */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jq },
|
||||
/* 0F 81 /wr */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jq },
|
||||
@ -1087,7 +1087,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F 6B /dr */ { BxPrefixSSE, BX_IA_PACKSSDW_PqQq, BxOpcodeGroupSSE_0f6b },
|
||||
/* 0F 6C /dr */ { BxPrefixSSE66, BX_IA_PUNPCKLQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6D /dr */ { BxPrefixSSE66, BX_IA_PUNPCKHQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6E /dr */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6e },
|
||||
/* 0F 6E /dr */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6eR },
|
||||
/* 0F 6F /dr */ { BxPrefixSSE, BX_IA_MOVQ_PqQq, BxOpcodeGroupSSE_0f6fR },
|
||||
/* 0F 70 /dr */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PSHUFW_PqQqIb, BxOpcodeGroupSSE_0f70 },
|
||||
/* 0F 71 /dr */ { BxGroup12, BX_IA_ERROR, BxOpcodeInfoG12R },
|
||||
@ -1103,7 +1103,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F 7B /dr */ { 0, BX_IA_ERROR },
|
||||
/* 0F 7C /dr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /dr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /dr */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7E /dr */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7eR },
|
||||
/* 0F 7F /dr */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7fR },
|
||||
/* 0F 80 /dr */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jq },
|
||||
/* 0F 81 /dr */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jq },
|
||||
@ -1614,7 +1614,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F 6B /qr */ { BxPrefixSSE, BX_IA_PACKSSDW_PqQq, BxOpcodeGroupSSE_0f6b },
|
||||
/* 0F 6C /qr */ { BxPrefixSSE66, BX_IA_PUNPCKLQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6D /qr */ { BxPrefixSSE66, BX_IA_PUNPCKHQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6E /qr */ { BxPrefixSSE, BX_IA_MOVQ_PqEqR, BxOpcodeGroupSSE_0f6eQ },
|
||||
/* 0F 6E /qr */ { BxPrefixSSE, BX_IA_MOVQ_PqEqR, BxOpcodeGroupSSE_0f6eQR },
|
||||
/* 0F 6F /qr */ { BxPrefixSSE, BX_IA_MOVQ_PqQq, BxOpcodeGroupSSE_0f6fR },
|
||||
/* 0F 70 /qr */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PSHUFW_PqQqIb, BxOpcodeGroupSSE_0f70 },
|
||||
/* 0F 71 /qr */ { BxGroup12, BX_IA_ERROR, BxOpcodeInfoG12R },
|
||||
@ -1630,7 +1630,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
|
||||
/* 0F 7B /qr */ { 0, BX_IA_ERROR },
|
||||
/* 0F 7C /qr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /qr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /qr */ { BxPrefixSSE, BX_IA_MOVQ_EqPq, BxOpcodeGroupSSE_0f7eQ },
|
||||
/* 0F 7E /qr */ { BxPrefixSSE, BX_IA_MOVQ_EqPq, BxOpcodeGroupSSE_0f7eQR },
|
||||
/* 0F 7F /qr */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7fR },
|
||||
/* 0F 80 /qr */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jq },
|
||||
/* 0F 81 /qr */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jq },
|
||||
@ -2147,7 +2147,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 6B /wm */ { BxPrefixSSE, BX_IA_PACKSSDW_PqQq, BxOpcodeGroupSSE_0f6b },
|
||||
/* 0F 6C /wm */ { BxPrefixSSE66, BX_IA_PUNPCKLQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6D /wm */ { BxPrefixSSE66, BX_IA_PUNPCKHQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6E /wm */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6e },
|
||||
/* 0F 6E /wm */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6eM },
|
||||
/* 0F 6F /wm */ { BxPrefixSSE, BX_IA_MOVQ_PqQq, BxOpcodeGroupSSE_0f6fM },
|
||||
/* 0F 70 /wm */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PSHUFW_PqQqIb, BxOpcodeGroupSSE_0f70 },
|
||||
/* 0F 71 /wm */ { 0, BX_IA_ERROR }, // SSE Group G12
|
||||
@ -2163,7 +2163,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 7B /wm */ { 0, BX_IA_ERROR },
|
||||
/* 0F 7C /wm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /wm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /wm */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7E /wm */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7eM },
|
||||
/* 0F 7F /wm */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7fM },
|
||||
/* 0F 80 /wm */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jq },
|
||||
/* 0F 81 /wm */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jq },
|
||||
@ -2674,7 +2674,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 6B /dm */ { BxPrefixSSE, BX_IA_PACKSSDW_PqQq, BxOpcodeGroupSSE_0f6b },
|
||||
/* 0F 6C /dm */ { BxPrefixSSE66, BX_IA_PUNPCKLQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6D /dm */ { BxPrefixSSE66, BX_IA_PUNPCKHQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6E /dm */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6e },
|
||||
/* 0F 6E /dm */ { BxPrefixSSE, BX_IA_MOVD_PqEd, BxOpcodeGroupSSE_0f6eM },
|
||||
/* 0F 6F /dm */ { BxPrefixSSE, BX_IA_MOVQ_PqQq, BxOpcodeGroupSSE_0f6fM },
|
||||
/* 0F 70 /dm */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PSHUFW_PqQqIb, BxOpcodeGroupSSE_0f70 },
|
||||
/* 0F 71 /dm */ { 0, BX_IA_ERROR }, // SSE Group G12
|
||||
@ -2690,7 +2690,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 7B /dm */ { 0, BX_IA_ERROR },
|
||||
/* 0F 7C /dm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /dm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /dm */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7e },
|
||||
/* 0F 7E /dm */ { BxPrefixSSE, BX_IA_MOVD_EdPd, BxOpcodeGroupSSE_0f7eM },
|
||||
/* 0F 7F /dm */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7fM },
|
||||
/* 0F 80 /dm */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jq },
|
||||
/* 0F 81 /dm */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jq },
|
||||
@ -3201,7 +3201,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 6B /qm */ { BxPrefixSSE, BX_IA_PACKSSDW_PqQq, BxOpcodeGroupSSE_0f6b },
|
||||
/* 0F 6C /qm */ { BxPrefixSSE66, BX_IA_PUNPCKLQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6D /qm */ { BxPrefixSSE66, BX_IA_PUNPCKHQDQ_VdqWdq, BxOpcodeGroupSSE_ERR },
|
||||
/* 0F 6E /qm */ { BxPrefixSSE, BX_IA_MOVQ_PqEqM, BxOpcodeGroupSSE_0f6eQ },
|
||||
/* 0F 6E /qm */ { BxPrefixSSE, BX_IA_MOVQ_PqEqM, BxOpcodeGroupSSE_0f6eQM },
|
||||
/* 0F 6F /qm */ { BxPrefixSSE, BX_IA_MOVQ_PqQq, BxOpcodeGroupSSE_0f6fM },
|
||||
/* 0F 70 /qm */ { BxPrefixSSE | BxImmediate_Ib, BX_IA_PSHUFW_PqQqIb, BxOpcodeGroupSSE_0f70 },
|
||||
/* 0F 71 /qm */ { 0, BX_IA_ERROR }, // SSE Group G12
|
||||
@ -3217,7 +3217,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
|
||||
/* 0F 7B /qm */ { 0, BX_IA_ERROR },
|
||||
/* 0F 7C /qm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7c },
|
||||
/* 0F 7D /qm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0f7d },
|
||||
/* 0F 7E /qm */ { BxPrefixSSE, BX_IA_MOVQ_EqPq, BxOpcodeGroupSSE_0f7eQ },
|
||||
/* 0F 7E /qm */ { BxPrefixSSE, BX_IA_MOVQ_EqPq, BxOpcodeGroupSSE_0f7eQM },
|
||||
/* 0F 7F /qm */ { BxPrefixSSE, BX_IA_MOVQ_QqPq, BxOpcodeGroupSSE_0f7fM },
|
||||
/* 0F 80 /qm */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JO_Jq },
|
||||
/* 0F 81 /qm */ { BxImmediate_BrOff32 | BxTraceJCC, BX_IA_JNO_Jq },
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: ia_opcodes.h,v 1.30 2009-10-24 11:17:51 sshwarts Exp $
|
||||
// $Id: ia_opcodes.h,v 1.31 2009-11-23 18:21:23 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2008-2009 Stanislav Shwartsman
|
||||
@ -931,8 +931,9 @@ bx_define_opcode(BX_IA_MOVUPS_VpsWpsR, &BX_CPU_C::MOVAPS_VpsWpsR, NULL)
|
||||
bx_define_opcode(BX_IA_MOVUPS_VpsWpsM, &BX_CPU_C::MOVUPS_VpsWpsM, NULL)
|
||||
bx_define_opcode(BX_IA_MOVUPS_WpsVpsR, &BX_CPU_C::MOVAPS_WpsVpsR, NULL)
|
||||
bx_define_opcode(BX_IA_MOVUPS_WpsVpsM, &BX_CPU_C::MOVUPS_WpsVpsM, NULL)
|
||||
bx_define_opcode(BX_IA_MOVSS_VssWss, &BX_CPU_C::MOVSS_VssWss, NULL)
|
||||
bx_define_opcode(BX_IA_MOVSS_WssVss, &BX_CPU_C::MOVSS_WssVss, NULL)
|
||||
bx_define_opcode(BX_IA_MOVSS_VssWssR, &BX_CPU_C::MOVSS_VssWssR, NULL)
|
||||
bx_define_opcode(BX_IA_MOVSS_VssWssM, &BX_CPU_C::MOVSS_VssWssM, NULL)
|
||||
bx_define_opcode(BX_IA_MOVSS_WssVssM, &BX_CPU_C::MOVSS_WssVssM, NULL)
|
||||
bx_define_opcode(BX_IA_MOVLPS_VpsMq, &BX_CPU_C::MOVLPS_VpsMq, NULL)
|
||||
bx_define_opcode(BX_IA_MOVLPS_MqVps, &BX_CPU_C::MOVLPS_MqVps, NULL)
|
||||
bx_define_opcode(BX_IA_MOVHPS_VpsMq, &BX_CPU_C::MOVHPS_VpsMq, NULL)
|
||||
@ -992,8 +993,9 @@ bx_define_opcode(BX_IA_MASKMOVQ_PqPRq, &BX_CPU_C::MASKMOVQ_PqPRq, NULL)
|
||||
// SSE
|
||||
|
||||
// SSE2
|
||||
bx_define_opcode(BX_IA_MOVSD_VsdWsd, &BX_CPU_C::MOVSD_VsdWsd, NULL)
|
||||
bx_define_opcode(BX_IA_MOVSD_WsdVsd, &BX_CPU_C::MOVSD_WsdVsd, NULL)
|
||||
bx_define_opcode(BX_IA_MOVSD_VsdWsdR, &BX_CPU_C::MOVSD_VsdWsdR, NULL)
|
||||
bx_define_opcode(BX_IA_MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VqWqM, NULL)
|
||||
bx_define_opcode(BX_IA_MOVSD_WsdVsdM, &BX_CPU_C::MOVSD_WsdVsdM, NULL)
|
||||
bx_define_opcode(BX_IA_CVTPI2PD_VpdQqR, &BX_CPU_C::CVTPI2PD_VpdQqR, NULL)
|
||||
bx_define_opcode(BX_IA_CVTPI2PD_VpdQqM, &BX_CPU_C::CVTPI2PD_VpdQqM, NULL)
|
||||
bx_define_opcode(BX_IA_CVTSI2SD_VsdEdR, &BX_CPU_C::CVTSI2SD_VsdEdR, NULL)
|
||||
@ -1074,14 +1076,17 @@ bx_define_opcode(BX_IA_UNPCKHPS_VpsWdq, &BX_CPU_C::UNPCKHPS_VpsWdq, NULL)
|
||||
bx_define_opcode(BX_IA_PACKSSDW_VdqWdq, &BX_CPU_C::PACKSSDW_VdqWdq, NULL)
|
||||
bx_define_opcode(BX_IA_PUNPCKLQDQ_VdqWdq, &BX_CPU_C::PUNPCKLQDQ_VdqWdq, NULL)
|
||||
bx_define_opcode(BX_IA_PUNPCKHQDQ_VdqWdq, &BX_CPU_C::PUNPCKHQDQ_VdqWdq, NULL)
|
||||
bx_define_opcode(BX_IA_MOVD_VdqEd, &BX_CPU_C::MOVD_VdqEd, NULL)
|
||||
bx_define_opcode(BX_IA_MOVD_VdqEdR, &BX_CPU_C::MOVD_VdqEdR, NULL)
|
||||
bx_define_opcode(BX_IA_MOVD_VdqEdM, BX_SSE2_ALIAS(&BX_CPU_C::MOVSS_VssWssM), NULL)
|
||||
bx_define_opcode(BX_IA_PSHUFD_VdqWdqIb, &BX_CPU_C::PSHUFD_VdqWdqIb, NULL)
|
||||
bx_define_opcode(BX_IA_PSHUFHW_VdqWdqIb, &BX_CPU_C::PSHUFHW_VdqWdqIb, NULL)
|
||||
bx_define_opcode(BX_IA_PCMPEQB_VdqWdq, &BX_CPU_C::PCMPEQB_VdqWdq, NULL)
|
||||
bx_define_opcode(BX_IA_PCMPEQW_VdqWdq, &BX_CPU_C::PCMPEQW_VdqWdq, NULL)
|
||||
bx_define_opcode(BX_IA_PCMPEQD_VdqWdq, &BX_CPU_C::PCMPEQD_VdqWdq, NULL)
|
||||
bx_define_opcode(BX_IA_MOVD_EdVd, &BX_CPU_C::MOVD_EdVd, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_VqWq, &BX_CPU_C::MOVQ_VqWq, NULL)
|
||||
bx_define_opcode(BX_IA_MOVD_EdVdR, &BX_CPU_C::MOVD_EdVdR, NULL)
|
||||
bx_define_opcode(BX_IA_MOVD_EdVdM, &BX_CPU_C::MOVD_EdVdM, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_VqWqR, &BX_CPU_C::MOVQ_VqWqR, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqM, NULL)
|
||||
bx_define_opcode(BX_IA_CMPPD_VpdWpdIb, &BX_CPU_C::CMPPD_VpdWpdIb, NULL)
|
||||
bx_define_opcode(BX_IA_CMPSD_VsdWsdIb, &BX_CPU_C::CMPSD_VsdWsdIb, NULL)
|
||||
bx_define_opcode(BX_IA_MOVNTI_MdGd, &BX_CPU_C::MOVNTI_MdGd, NULL)
|
||||
@ -1562,10 +1567,12 @@ bx_define_opcode(BX_IA_LOOPE64_Jb, &BX_CPU_C::LOOPE64_Jb, NULL)
|
||||
bx_define_opcode(BX_IA_LOOP64_Jb, &BX_CPU_C::LOOP64_Jb, NULL)
|
||||
bx_define_opcode(BX_IA_JRCXZ_Jb, &BX_CPU_C::JRCXZ_Jb, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_EqPq, &BX_CPU_C::MOVQ_EqPq, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_EqVq, &BX_CPU_C::MOVQ_EqVq, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_EqVqR, &BX_CPU_C::MOVQ_EqVqR, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_EqVqM, &BX_CPU_C::MOVSD_WsdVsdM, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_PqEqR, &BX_CPU_C::MOVQ_PqEqR, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_PqEqM, &BX_CPU_C::MOVQ_PqEqM, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_VdqEq, &BX_CPU_C::MOVQ_VdqEq, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_VdqEqR, &BX_CPU_C::MOVQ_VdqEqR, NULL)
|
||||
bx_define_opcode(BX_IA_MOVQ_VdqEqM, &BX_CPU_C::MOVQ_VqWqM, NULL)
|
||||
bx_define_opcode(BX_IA_MOVNTI_MqGq, &BX_CPU_C::MOVNTI_MqGq, NULL)
|
||||
bx_define_opcode(BX_IA_POPCNT_GqEqR, &BX_CPU_C::POPCNT_GqEqR, NULL)
|
||||
bx_define_opcode(BX_IA_POPCNT_GqEqM, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::POPCNT_GqEqR)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: sse_move.cc,v 1.103 2009-11-13 09:55:22 sshwarts Exp $
|
||||
// $Id: sse_move.cc,v 1.104 2009-11-23 18:21:23 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2003-2009 Stanislav Shwartsman
|
||||
@ -411,9 +411,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_VpsWpsM(bxInstruction_c *i)
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dqword(i->seg(), eaddr, (Bit8u *) &op);
|
||||
|
||||
/* now write result back to destination */
|
||||
@ -431,11 +429,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_WpsVpsM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_dqword(i->seg(), eaddr, (Bit8u *) &op);
|
||||
#else
|
||||
BX_INFO(("MOVUPS_WpsVps: required SSE, use --enable-sse option"));
|
||||
@ -463,9 +458,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_VpsWpsM(bxInstruction_c *i)
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
read_virtual_dqword_aligned(i->seg(), eaddr, (Bit8u *) &op);
|
||||
|
||||
/* now write result back to destination */
|
||||
@ -483,7 +476,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_WpsVpsR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_WRITE_XMM_REG(i->rm(), BX_READ_XMM_REG(i->nnn()));
|
||||
#else
|
||||
BX_INFO(("MOVAPS_WpsVps: required SSE, use --enable-sse option"));
|
||||
@ -495,11 +487,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_WpsVpsM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_dqword_aligned(i->seg(), eaddr, (Bit8u *) &op);
|
||||
#else
|
||||
BX_INFO(("MOVAPS_WpsVps: required SSE, use --enable-sse option"));
|
||||
@ -508,28 +497,33 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_WpsVpsM(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* F3 0F 10 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWssR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
/* If the source operand is an XMM register, the high-order
|
||||
96 bits of the destination XMM register are not modified. */
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), BX_READ_XMM_REG_LO_DWORD(i->rm()));
|
||||
#else
|
||||
BX_INFO(("MOVSS_VssWss: required SSE, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0())
|
||||
{
|
||||
/* If the source operand is an XMM register, the high-order
|
||||
96 bits of the destination XMM register are not modified. */
|
||||
op.xmm32u(0) = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* If the source operand is a memory location, the high-order
|
||||
96 bits of the destination XMM register are cleared to 0s */
|
||||
op.xmm32u(0) = read_virtual_dword(i->seg(), eaddr);
|
||||
op.xmm32u(1) = 0;
|
||||
op.xmm64u(1) = 0;
|
||||
}
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWssM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
/* If the source operand is a memory location, the high-order
|
||||
96 bits of the destination XMM register are cleared to 0s */
|
||||
op.xmm64u(0) = (Bit64u) read_virtual_dword(i->seg(), eaddr);
|
||||
op.xmm64u(1) = 0;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
@ -540,25 +534,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* F3 0F 11 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_WssVss(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_WssVssM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Bit32u val32 = BX_READ_XMM_REG_LO_DWORD(i->nnn());
|
||||
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0())
|
||||
{
|
||||
/* If the source operand is an XMM register, the high-order
|
||||
96 bits of the destination XMM register are not modified. */
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->rm(), val32);
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_dword(i->seg(), eaddr, val32);
|
||||
}
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
write_virtual_dword(i->seg(), eaddr, BX_READ_XMM_REG_LO_DWORD(i->nnn()));
|
||||
#else
|
||||
BX_INFO(("MOVSS_WssVss: required SSE, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
@ -566,30 +547,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_WssVss(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* F2 0F 10 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_VsdWsd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_VsdWsdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0())
|
||||
{
|
||||
/* If the source operand is an XMM register, the high-order
|
||||
64 bits of the destination XMM register are not modified. */
|
||||
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* If the source operand is a memory location, the high-order
|
||||
64 bits of the destination XMM register are cleared to 0s */
|
||||
op.xmm64u(0) = read_virtual_qword(i->seg(), eaddr);
|
||||
op.xmm64u(1) = 0;
|
||||
}
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
/* If the source operand is an XMM register, the high-order
|
||||
64 bits of the destination XMM register are not modified. */
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), BX_READ_XMM_REG_LO_QWORD(i->rm()));
|
||||
#else
|
||||
BX_INFO(("MOVSD_VsdWsd: required SSE2, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
@ -597,25 +562,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_VsdWsd(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* F2 0F 11 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_WsdVsd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_WsdVsdM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Bit64u val64 = BX_READ_XMM_REG_LO_QWORD(i->nnn());
|
||||
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0())
|
||||
{
|
||||
/* If the source operand is an XMM register, the high-order
|
||||
64 bits of the destination XMM register are not modified. */
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->rm(), val64);
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_qword(i->seg(), eaddr, val64);
|
||||
}
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
write_virtual_qword(i->seg(), eaddr, BX_READ_XMM_REG_LO_QWORD(i->nnn()));
|
||||
#else
|
||||
BX_INFO(("MOVSD_WsdVsd: required SSE2, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
@ -891,29 +843,16 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPD_GdVRpd(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
/* 66 0F 6E */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_VdqEd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_VdqEdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1;
|
||||
Bit32u op2;
|
||||
BxPackedXmmRegister op;
|
||||
op.xmm64u(0) = (Bit64u) BX_READ_32BIT_REG(i->rm());
|
||||
op.xmm64u(1) = 0;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op2 = read_virtual_dword(i->seg(), eaddr);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) = (Bit64u)(op2);
|
||||
op1.xmm64u(1) = 0;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("MOVD_VdqEd: required SSE2, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
@ -923,29 +862,16 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_VdqEd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_X86_64
|
||||
|
||||
/* 66 0F 6E */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VdqEq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VdqEqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op1;
|
||||
Bit64u op2;
|
||||
BxPackedXmmRegister op;
|
||||
op.xmm64u(0) = BX_READ_64BIT_REG(i->rm());
|
||||
op.xmm64u(1) = 0;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_64BIT_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op2 = read_virtual_qword_64(i->seg(), eaddr);
|
||||
}
|
||||
|
||||
op1.xmm64u(0) = op2;
|
||||
op1.xmm64u(1) = 0;
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("MOVQ_VdqEq: required SSE2, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
@ -955,22 +881,23 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VdqEq(bxInstruction_c *i)
|
||||
#endif
|
||||
|
||||
/* 66 0F 7E */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdVd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdVdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), BX_READ_XMM_REG_LO_DWORD(i->nnn()));
|
||||
#else
|
||||
BX_INFO(("MOVD_EdVd: required SSE2, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
Bit32u op2 = BX_READ_XMM_REG_LO_DWORD(i->nnn());
|
||||
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), op2);
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_dword(i->seg(), eaddr, op2);
|
||||
}
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdVdM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
write_virtual_dword(i->seg(), eaddr, BX_READ_XMM_REG_LO_DWORD(i->nnn()));
|
||||
#else
|
||||
BX_INFO(("MOVD_EdVd: required SSE2, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
@ -980,22 +907,11 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdVd(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_X86_64
|
||||
|
||||
/* 66 0F 7E */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_EqVq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_EqVqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
Bit64u op2 = BX_READ_XMM_REG_LO_QWORD(i->nnn());
|
||||
|
||||
/* destination is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), op2);
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_qword_64(i->seg(), eaddr, op2);
|
||||
}
|
||||
BX_WRITE_64BIT_REG(i->rm(), BX_READ_XMM_REG_LO_QWORD(i->nnn()));
|
||||
#else
|
||||
BX_INFO(("MOVQ_EqVq: required SSE2, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
@ -1005,24 +921,34 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_EqVq(bxInstruction_c *i)
|
||||
#endif
|
||||
|
||||
/* F3 0F 7E */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
if (i->modC0()) {
|
||||
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op.xmm64u(0) = read_virtual_qword(i->seg(), eaddr);
|
||||
}
|
||||
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
op.xmm64u(1) = 0; /* zero-extension to 128 bit */
|
||||
|
||||
/* zero-extension to 128 bit */
|
||||
op.xmm64u(1) = 0;
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("MOVQ_VqWq: required SSE2, use --enable-sse option"));
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
op.xmm64u(0) = read_virtual_qword(i->seg(), eaddr);
|
||||
op.xmm64u(1) = 0; /* zero-extension to 128 bit */
|
||||
|
||||
/* now write result back to destination */
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
@ -1038,17 +964,19 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_WqVq(bxInstruction_c *i)
|
||||
#if BX_SUPPORT_SSE >= 2
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
|
||||
Bit64u val64 = BX_READ_XMM_REG_LO_QWORD(i->nnn());
|
||||
|
||||
if (i->modC0())
|
||||
{
|
||||
BxPackedXmmRegister op;
|
||||
op.xmm64u(0) = val64;
|
||||
op.xmm64u(1) = 0; /* zero-extension to 128 bits */
|
||||
BX_WRITE_XMM_REG(i->rm(), op);
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
write_virtual_qword(i->seg(), eaddr, op.xmm64u(0));
|
||||
write_virtual_qword(i->seg(), eaddr, val64);
|
||||
}
|
||||
#else
|
||||
BX_INFO(("MOVQ_WqVq: required SSE2, use --enable-sse option"));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user