mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Correctly detect SSE2 and SSE instructions and #UD when SSE2 is OFF for SSE

Browse Source
This commit is contained in:
Stanislav Shwartsman 2007-04-02 10:46:33 +00:00
parent abd7cbda87
commit bdc4905c8a
2 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
bochs/cpu/fetchdecode64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode64.cc,v 1.107 2007-03-28 21:20:09 sshwarts Exp $
// $Id: fetchdecode64.cc,v 1.108 2007-04-02 10:46:32 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -2620,7 +2620,6 @@ modrm_done:
if (instruction->os32L()) {
if ((ilen+3) < remain) {
instruction->modRMForm.Id = FetchDWORD(iptr);
iptr += 4;
ilen += 4;
}
else return(0);
@ -2628,7 +2627,6 @@ modrm_done:
else {
if ((ilen+1) < remain) {
instruction->modRMForm.Iw = FetchWORD(iptr);
iptr += 2;
ilen += 2;
}
else return(0);

10
bochs/cpu/sse.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse.cc,v 1.44 2007-03-23 21:27:12 sshwarts Exp $
// $Id: sse.cc,v 1.45 2007-04-02 10:46:33 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -1418,7 +1418,7 @@ void BX_CPU_C::ANDNPS_VpsWps(bxInstruction_c *i)
/* 66 0F E0 */
void BX_CPU_C::PAVGB_VdqWdq(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 2
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
@ -1439,7 +1439,7 @@ void BX_CPU_C::PAVGB_VdqWdq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PAVGB_VdqWdq: required SSE2, use --enable-sse option"));
BX_INFO(("PAVGB_VdqWdq: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
#endif
}
@ -1557,7 +1557,7 @@ void BX_CPU_C::PSRAD_VdqWdq(bxInstruction_c *i)
/* 66 0F E3 */
void BX_CPU_C::PAVGW_VdqWdq(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 2
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
@ -1583,7 +1583,7 @@ void BX_CPU_C::PAVGW_VdqWdq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PAVGW_VdqWdq: required SSE2, use --enable-sse option"));
BX_INFO(("PAVGW_VdqWdq: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
#endif
}