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276 Commits

Author SHA1 Message Date
Stanislav Shwartsman
5e7218b8c3 Fixed problem introduced by prev checkin 
+
Fix beak to debugger when executing HLT instruction
 2008-02-29 05:39:40 +00:00
Stanislav Shwartsman
405fcfd75d Reorganize 3-byte opcode tables - bigger tables but easier to maintain them 2008-02-29 03:02:03 +00:00
Stanislav Shwartsman
cdcd7522aa Added RIP to the GPR register file as lst register 
This allowed to optimize (read - remove) two more BxResolve methods in 64-bit mode
+ Some white space cleanup
 2008-02-15 19:03:54 +00:00
Stanislav Shwartsman
0f44b4f0ec Fixes in MODRM tables 2008-02-15 12:23:49 +00:00
Stanislav Shwartsman
4fc0df26e8 a bit optimize and simplify x87 decoding 2008-02-14 18:59:41 +00:00
Stanislav Shwartsman
fb0ce45d28 Unpack more fields in bxInstruction_c -> this increase bxInstruction size by 4 bytes but I have no way but do it if want to support SSE5 dest override later 2008-02-04 21:28:53 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
37fbb82baa Cleanups. Move bxInstruction_c definition to separate file instr.h 2008-01-29 17:13:10 +00:00
Stanislav Shwartsman
7b80c5f481 I merged and succeded to remove some similar execution functions - less code, less chance for branch misprediction 2008-01-25 19:34:30 +00:00
Stanislav Shwartsman
63d8d50cfc code cleanup 2008-01-20 20:11:17 +00:00
Stanislav Shwartsman
8c9de8b4db speculative tracing on fetchdecode level 2008-01-18 09:36:15 +00:00
Stanislav Shwartsman
d9984bb3a1 Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup ! 2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
eee1a9030d a bit simplify and optimize shift instructions 
print failed segment info in check_cs - more debug info
 2007-12-30 20:16:35 +00:00
Stanislav Shwartsman
c3c9c40674 Move MaxFetch calculation into fetchdecode - simplify the logic 2007-12-22 17:17:40 +00:00
Stanislav Shwartsman
e9a148f9c4 lmost last instruction split -> CMOV in 16/32 bit modes 2007-12-21 18:24:19 +00:00
Stanislav Shwartsman
c9932e97eb Fixes in resolve.cc -> reduce amount of resolve functions even more 2007-12-18 21:41:44 +00:00
Stanislav Shwartsman
fe2e0525da More optimization for string instructions 2007-12-17 19:52:01 +00:00
Stanislav Shwartsman
de5838ce80 cleanups and fixes for Immediate_IbIb of SSE4A 2007-12-16 20:47:10 +00:00
Stanislav Shwartsman
1e843cb462 Decode SSE4A 
Rework immediate bytes decoding to make it faster
 2007-12-15 17:42:24 +00:00
Stanislav Shwartsman
fd73390ca5 Split 64-bit CMOVcc opcode 2007-12-14 22:41:43 +00:00
Stanislav Shwartsman
903f6dea35 Split setCC functions - makes code faster and simpler 2007-12-14 21:29:36 +00:00
Stanislav Shwartsman
05c7a1e61b Fixed problem with trace cache enabled 
String instructions might confise trace cache by finishing instruction execution method without actually completing an instruction (and advancing eip)
 2007-12-13 18:42:31 +00:00
Stanislav Shwartsman
adda3befd3 Trace cache optimization merged 2007-12-09 18:36:05 +00:00
Stanislav Shwartsman
4c16dd71a8 Fixed compilation error in SMP mode 2007-12-07 09:38:42 +00:00
Stanislav Shwartsman
1bcf42baec oops, fixed incorrect checkin 2007-12-01 16:59:36 +00:00
Stanislav Shwartsman
7ca78b88e9 configure/compile changes + small optimizations 2007-12-01 16:45:17 +00:00
Stanislav Shwartsman
8cfd17202a some simple SSE code optimizations 2007-11-27 22:12:45 +00:00
Stanislav Shwartsman
c51888f43f Split last BxLockable opcodes -> this allows to eliminate mod==0xc0 check from fetchdecode of every instruction 
reduce ACPU.CC dependencies - now that file doesn't depend of CPU
 2007-11-25 20:22:10 +00:00
Stanislav Shwartsman
e51184c8cf Eliminate saving of RSP from heart of cpu_loop 
Now save RSP only where it is really required
 2007-11-24 14:22:34 +00:00
Stanislav Shwartsman
3daa468c02 Fixed comments in bit.cc 
Revert back lock prefix changes in fetchdecode - not all lockable instructions are splitted yet ;(
 2007-11-23 16:37:06 +00:00
Stanislav Shwartsman
1dbe51a2fb Split ENTER_IwBw function according to os32. Fixed ENTER/LEAVE in 64-bit mode 2007-11-22 17:33:06 +00:00
Stanislav Shwartsman
0a1063ad77 Split GvEv opcode groups 2007-11-21 22:36:02 +00:00
Stanislav Shwartsman
506dc3d963 Optimize 64-bit fetchdecode prefix handling 
Deparecated set_FLAG() method, setB_FLAG() method was used everywhere
Rename setB_FLAG to set_FLAG, so set_FLAG() will must receive 0/1 inly
 2007-11-20 23:00:44 +00:00
Stanislav Shwartsman
d75a69fd2e Remove BxResolve tables 2007-11-18 22:14:39 +00:00
Stanislav Shwartsman
fb61418307 optimize modrm/sib decoding 2007-11-18 21:38:58 +00:00
Stanislav Shwartsman
30f42d74f1 make sreg index tables static in fetchdecode and remove them from init.cc/cpu.h 2007-11-18 21:07:40 +00:00
Stanislav Shwartsman
1e0db62984 bit.cc speedup (small) 2007-11-18 20:21:34 +00:00
Stanislav Shwartsman
bcaba54489 Merge resolve functions for 32 and 64-bit 2007-11-18 19:46:14 +00:00
Stanislav Shwartsman
57d2d14865 Split POP_Ev opcodes 2007-11-18 18:49:19 +00:00
Stanislav Shwartsman
cdc9a09090 Split more opcodes 2007-11-18 18:24:46 +00:00
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :) 
Also split EqId G1 group for x86-64
 2007-11-17 23:28:33 +00:00
Stanislav Shwartsman
613bad34ee split MOVZX/MOVSX opcodes 2007-11-17 18:29:00 +00:00
Stanislav Shwartsman
5ec15df46d Split more opcodes EbIb opcodes 2007-11-17 18:08:46 +00:00
Stanislav Shwartsman
d5a58e1df2 Split more opcodes - G3 group 2007-11-17 16:20:37 +00:00
Stanislav Shwartsman
d9e58bd598 split11b on opcode tables level - split almost eevery splittable instruction 
will be continued
 2007-11-17 12:44:10 +00:00
Stanislav Shwartsman
abe3f4c5c2 Split one more opcode 2007-11-16 21:43:23 +00:00
Stanislav Shwartsman
b4b922809a Move 3byte opcode decoding under Modrm condition 2007-11-16 20:49:51 +00:00
Stanislav Shwartsman
565e7f9868 Merge common fetchdecode groups. Add more comments to fetchdecode tables 2007-11-16 18:34:14 +00:00
Stanislav Shwartsman
393018cdf8 More split11b 2007-11-16 17:45:58 +00:00
Stanislav Shwartsman
351244d1ea Rename splitmod11b methods 2007-11-16 08:30:22 +00:00
Stanislav Shwartsman
db02731cbf Replace BxAnother attribute in fetchdecode by table lookup like it is done in disasm. This is done in preparation to feature huge fetchdecode change - all fethdecode tables will be duplicated and made separatate table for ModC0 and others. 
So ALL instructions will emjoy SplitMod11b automatically (if they want).
After splitting ALL instruction I hope to get 20% speedup at least.
 2007-11-15 17:57:56 +00:00
Stanislav Shwartsman
9da22f9b65 Remove redundant BxAnother attr from prefixes 
The meaning of BxAnother attr - instryction has modrm byte
 2007-11-14 22:52:16 +00:00
Stanislav Shwartsman
0fa82afe1f Bugfix and optimize BxResolve calls - bugfix in 64-bit mode 2007-11-13 17:30:54 +00:00
Stanislav Shwartsman
edfff23ca0 Split JCC methods to 16 different methods per branch condition 2007-11-12 18:20:15 +00:00
Stanislav Shwartsman
aed6640ef4 speedup JCC for 64-bit -> separate JZ/JNZ for single faster methods 2007-11-11 21:26:10 +00:00
Stanislav Shwartsman
eea5023da8 small simplification for fetchdecode 2007-11-11 20:56:22 +00:00
Stanislav Shwartsman
2653d54e96 split 32-bit modermdata variable in BxInstruction_c to 4 Bit8u variables 
this way it is possible to save shifts and masking when accessing modrm fields
 2007-11-08 18:21:37 +00:00
Stanislav Shwartsman
2f5fa07af3 small speedups 2007-11-07 10:40:40 +00:00
Stanislav Shwartsman
292153b30e Fixed BranchImm cases in 64-bit mode 2007-10-22 17:41:41 +00:00
Stanislav Shwartsman
5445de19d1 Decoding : F2 and F2 prefix could override prefix 66 when determine SSE opcode 2007-10-20 10:56:44 +00:00
Stanislav Shwartsman
be9ad60ef3 cleanups 2007-10-11 22:44:17 +00:00
Stanislav Shwartsman
8adbbcf17c Started first implementation of MONITOR/MWAIT 2007-10-11 21:29:01 +00:00
Stanislav Shwartsman
0dc4badfbb Added SSE4A and SSE4_2 to disassembler 
Implemented POPCNT instruction
 2007-09-19 19:38:10 +00:00
Stanislav Shwartsman
b64fc08c54 implement prefetch hint opcodes 2007-08-23 16:47:51 +00:00
Stanislav Shwartsman
4555cc9be3 ud2b opcode should have modrm byte 2007-08-18 13:51:16 +00:00
Stanislav Shwartsman
5189cfbf10 SSE4 support 2007-04-19 16:12:21 +00:00
Stanislav Shwartsman
223b9fda0e Fixed RIP relative mode when in 32-bit address size 2007-04-09 21:15:00 +00:00
Stanislav Shwartsman
e26609fa97 Support for Intel LSS/LFS/LGS in 64-bit mode 
TODO: have both AMD and Intelk versions
 2007-04-09 20:28:15 +00:00
Stanislav Shwartsman
bdc4905c8a Correctly detect SSE2 and SSE instructions and #UD when SSE2 is OFF for SSE 2007-04-02 10:46:33 +00:00
Stanislav Shwartsman
4bb19c2dc3 Fixed deciding and disasm of CALL in 64-bit mode (no 16-bit calls allowed) 2007-03-28 21:20:09 +00:00
Stanislav Shwartsman
ef542b3790 Learn to decode and disassemble VMX opcodes 
No fetchdecode support but everything is ready
 2007-03-23 14:35:50 +00:00
Stanislav Shwartsman
c24627c00f Implemented CLFLUSH instruction 
Set of minor fixes for correctness
 2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
8221fa6838 - Fixed zero upper 32-bit part of GPR in x86-64 mode 
- CMOV_GdEd should zero upper 32-bit part of GPR register even if the
    'cmov' condition was false !
 2007-01-26 22:12:05 +00:00
Stanislav Shwartsman
f8003098b1 Rename SSE4 to SSE3E to match intel docs. SSE4 coming later ;) 
Fixed "last prefix" for REX in 64-bit mode
 2007-01-25 19:09:41 +00:00
Stanislav Shwartsman
9db896d100 minor x86_64 fixes and cleanups 2007-01-12 22:47:21 +00:00
Stanislav Shwartsman
5c21f7821f Speed simulation between 3 to 5% by eliminating several checks from cpu loop. 
The checks were related to repeat instructions - handle them differently
 2007-01-05 13:40:47 +00:00
Stanislav Shwartsman
3ce7764fce Fixes in 64-bit decoding 2006-08-11 17:23:36 +00:00
Stanislav Shwartsman
45353d5e6f Fixed DR registers handling in x86-64 mode 2006-06-26 21:07:44 +00:00
Stanislav Shwartsman
6c3420a18b Add debug prints before any #GP excepion which only possible to be generated 2006-06-09 22:29:07 +00:00
Stanislav Shwartsman
a4129e5341 Handle NULL_SEG_REG (no segment override) case in fetchdecode.cc 2006-05-24 20:57:37 +00:00
Stanislav Shwartsman
fc799ab623 FetchDecode tables are constant. Marking them const implicitly will help to compiler/linker in optimization. 2006-05-12 18:03:26 +00:00
Stanislav Shwartsman
fe644dfcbf - Code cleanup, remove x86-64 code from functions which cannot be called from x86-64 
- Fix PANIC multiple SSE prefix decoding (fetchdecode and disasm)
- More Bit32u -> bx_phy_address convert
- Lazy flags optimization
 2006-05-12 17:04:19 +00:00
Stanislav Shwartsman
20b14aefa6 Fix in BSWAP 64-bit mode - allow to use additional R8-R15 registers 
Also fixed code duplication story with BSWAP instruction
 2006-05-07 18:58:47 +00:00
Stanislav Shwartsman
d69eba6c07 Split in/out instructions based on operand size 2006-05-07 18:27:36 +00:00
Stanislav Shwartsman
03eac64013 Added decoding of new SSE4 instructions (recently published in Intel docs) 
At least CPUID detects them correctly
The code is never tested (still) ! (but should work fine)
 2006-04-06 18:30:05 +00:00
Stanislav Shwartsman
9dc1790f07 Simplify and optimize fetchdecode methods. 
Now fetchdecode is simpler to understand and easier to modify, for example to support 3-byte opcodes (SSE4)
 2006-04-05 20:52:40 +00:00
Stanislav Shwartsman
f8c3968d42 Changes list made after CVS service crash: 
- Fixed critical bug in CPU code added with one of the prev commits
  - Disasm support for SSE4
  - Rename PNI->SSE3 everywhere in the code
  - Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
  - Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
  - Fixed ENTER and LEAVE instructions in x86-64 mode
  - Added ability to turn ON instruction trace, only GUI support is missed.
    Instruction trace could be enabled if Bochs was compiled with disasm
  - More changes Bit32u -> bx_phy_address
  - Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
  - Small code cleanup
  - Update CHANGES and user docs
 2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
f347ab97bf Fixed CALL/JMP far through call gate 64 
Decode SWAPGS and RDTSCP instructions
Indent changes in fetchdecode
 2006-03-22 20:47:11 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU 
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
 2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
c8cd1f805a Enabled LAHF/SAHF for x86-64 mode 2006-01-17 19:50:42 +00:00
Stanislav Shwartsman
e2a5b9c338 MOV to/from test register are UD in x86-64 2005-11-11 22:02:42 +00:00
Stanislav Shwartsman
cb4ec526ab Fix comments and cleanup ... 
No functional change
 2005-11-11 21:34:57 +00:00
Stanislav Shwartsman
38a7e0abea 0f 0d (3dnow prefetch instruction) should execute as NOP when running on Intel EM64T CPU and as prefetch on AMD 2005-11-11 21:09:02 +00:00
Stanislav Shwartsman
d1c722211e Fix duplicate opcodes, fix opcode names and disasm bugs 2005-09-23 16:45:41 +00:00
Stanislav Shwartsman
37bd193337 Split PUSHF/POPF to 3 different methods according to op size. 
By the way fix VIP/VIF flags handling in POPF/PUSHF (future fix for VME)
 2005-08-08 19:56:11 +00:00
Stanislav Shwartsman
f096a80716 Fix code duplication for check_cs descriptor 
The function will execute
 - segment is executable code segment
 - conforming/non-conforming segment priviledge checks
 - segment is present
 2005-08-01 21:40:17 +00:00
Stanislav Shwartsman
954aae3f99 Speedup push/pop operations, they actually not needed to do can_push/can_pop checkes, the same checkes already done in read/write_virtial methods 
Split push_seg_reg methods according to op size
 2005-07-31 17:57:27 +00:00
Stanislav Shwartsman
2b5a812674 Split last bit.cc methods according to os16/32/64 2005-07-25 04:18:20 +00:00
Stanislav Shwartsman
ce8f1ade07 Some not really significant speedups 2005-06-21 17:01:21 +00:00
Stanislav Shwartsman
015ad92958 Added SMP status to TODO file 
Removed abusive BX_INFO from WBINVD instruction
The PREFETCHW (3DNow!) instruction should not #UD in x86-64 even on Intel w/o 3DNow!
 2005-05-27 01:53:38 +00:00
Stanislav Shwartsman
663f7d5ef3 CMPXCHG16B instruction implemented 2005-05-19 20:25:16 +00:00
Stanislav Shwartsman
a86002a8bc Improve Bochs instrumentation 
Small changes in APIC timer, should fix the bug report
[ 957660 ] >>PANIC<< APIC: R(curr timer count): delta < initial
 2005-04-29 21:28:59 +00:00
Stanislav Shwartsman
619942cf9a Enable SYSENTER/SYSEXIT together with x86-64 support, these instructions used by gentoo amd64 LiveCD image (at least it WRMSR to SYSENTER MSRs). 
SYSENTER/SYSEXIT is not recognized in long mode but it could be used i any other mode without problem
 2005-03-29 21:59:44 +00:00
Stanislav Shwartsman
e6e9dd3825 Extend Bochs instrumentation 
Compatability fixes
 2005-03-17 20:50:57 +00:00
Stanislav Shwartsman
709b218c10 Reduce metaInfo initialization in fetchDecode 2005-03-01 21:44:01 +00:00
Stanislav Shwartsman
2bfc842c09 CPU fixes by Kevin Lawton 2005-02-16 21:27:21 +00:00
Stanislav Shwartsman
9492942ae6 In 64-bit mode, the CS, DS, ES, and SS segment overrides are ignored. 2005-02-12 19:25:33 +00:00
Stanislav Shwartsman
f375203fdb preparations for x86-64 support in disasm 2004-12-12 22:12:43 +00:00
Stanislav Shwartsman
46bb3d8853 remove duplicated data arrays from CPU 2004-12-11 20:51:13 +00:00
Stanislav Shwartsman
5213e903bd mov duplicate opcode groups from fectchdecode*.cc to .h 
use common register accessor macroses instead of direct register file structure access
 2004-11-26 20:21:28 +00:00
Stanislav Shwartsman
69c0b06955 fixes in disassembler 
split REPEAT instructions according to opsize to speedup execution
now each REPEATABLE instruction splitted to 3 different instructions, one for 16-bit operand size, one for 32-bit and one for 64-bit. Choosing of correct instruction occure in fetchdecode step.
 2004-11-20 23:26:32 +00:00
Stanislav Shwartsman
730b8c0243 Fix this pointers in the code 2004-11-14 21:25:42 +00:00
Stanislav Shwartsman
4f1f070c37 Fix comments for code 2004-10-08 19:29:04 +00:00
Stanislav Shwartsman
3adc5c8659 Fix lock prefix for XOR instruction in 64-bit mode 2004-10-08 19:07:18 +00:00
Stanislav Shwartsman
760a195c9d * Fix LOCK prefix handling for x86-64 
* Split BT*_EvGv functions to 3 different function according to exec mode
 2004-09-17 20:47:19 +00:00
Stanislav Shwartsman
fc631037ff remove obsolete comments from fetchdecode 2004-09-06 20:22:39 +00:00
Stanislav Shwartsman
279d207d45 Fix fetchdecode bugs reported by Gilbert Netzer 
(opcode patches for x86_64 cpu)
 2004-05-03 17:58:36 +00:00
Stanislav Shwartsman
0eb71999db Added missed 287 opcodes which should be executed as NOP in 387+ 2003-12-28 18:19:41 +00:00
Stanislav Shwartsman
9ccb363ec3 bochs style decode/execute of FPU instructions. 
With this coding style each instruction could be implemented separatelly even not together with current Bochs FPU emulator.
Step-by-step I am going to transfer all FPU instructions from current Bochs FPU emulator to new style and remove an old bugged emulator.
Anyway, now I could implement all currently missed FPU instructions without hacking wm-fpu-emu.
 2003-12-27 13:50:06 +00:00
Stanislav Shwartsman
ac20b6405a - FXSAVE/FXRSTOR instructions should be available in P6 mode 
- Added second UD2 opcode to fetchdecode
- Added RDPMC instruction to fetchdecode
- 'changes' updated
 2003-10-24 18:34:16 +00:00
Stanislav Shwartsman
7f570b0150 Added PNI new streaming extensions instructions 
PNI could be enabled by setting BX_SUPPORT_PNI in config.h
After the feature will be fully validation I'll also add configure option.

The implemntation is ~complete. I've missed only three FPU new opcodes of FUSTTP instruction and MONITOR/WAIT instructions.

Enjoy ! ;)
 2003-08-29 21:20:52 +00:00
Stanislav Shwartsman
254ad17328 Changes method of resolving opcode/attributes from group table 
New method more flexible and easy to understanding.
Reorganizing fetchdecode code and make it more easy and understandable
 2003-08-28 19:25:23 +00:00
Stanislav Shwartsman
f6711d51f2 Fixed very serious bug in x86-64 with wrong decoding of opcodes with two immediates 2003-08-15 13:17:16 +00:00
Stanislav Shwartsman
3c00944998 I hope this is the last one ... 2003-05-29 19:44:59 +00:00
Stanislav Shwartsman
56cc6469e3 Ops, missed one ... 2003-05-29 17:19:38 +00:00
Stanislav Shwartsman
f933d604d3 Fixed missed BxLockable for XCHG instruction 2003-05-29 17:15:08 +00:00
Stanislav Shwartsman
140ff2541b Ability to configure x86-64 without 3DNOW 2003-05-21 15:20:51 +00:00
Stanislav Shwartsman
1d45167e5b Merged NEW-INSTRUCTIONS branch 2003-05-15 16:41:17 +00:00
Christophe Bothamy
83b8bbedff - fix REX MOVB immediate for x86_64 (patch by Arnd Bergmann) 
(bug [ 720776 ] REX MOVB immediate broken for x86_64)
 2003-04-26 10:02:03 +00:00
Stanislav Shwartsman
446fca9ed0 Superfluous braces in initializers in fetchdecode.cc 2003-04-23 17:52:59 +00:00
Stanislav Shwartsman
40bd4f138b Little style changes 
Elliminated i387_t alimit field (not used in FPU)
 2003-04-16 18:38:53 +00:00
Stanislav Shwartsman
1d54caca9b Fixed compilation error 2003-04-09 19:20:05 +00:00
Stanislav Shwartsman
7db893970c Read attributes bits even for BxSplit11b opcodes 
Move lock prefix check later in fetchdecode function when all attributes is ready.
 2003-04-06 19:08:31 +00:00
Stanislav Shwartsman
1e71c9e56e Merged patch-unallowed-lock-cases patch. 
According to the Intel manuals:

  The  LOCK  prefix  can be prepended only to the following instructions
  and  only  to  those  forms  of the instructions where the destination
  operand  is  a  memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG,
  CMPXCH8B,  DEC,  INC,  NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If
  the  LOCK prefix is used with one of these instructions and the source
  operand  is a memory operand, an undefined opcode exception (#UD) will
  be  generated. An undefined opcode exception will also be generated if
  the  LOCK  prefix  is used with any instruction not in the above list.

 Checking of the LOCK prefix done in fetchDecode state and not overloads
 Bochs's execution.
 2003-04-05 12:16:53 +00:00
Christophe Bothamy
1a518b81fe - add __attribute__((regparm(X))) performance trick with gcc on x86 
on some cpu instructions (patch from Conn Clark)
- performance improvement is 1% on win95 boot
 2003-03-17 00:41:01 +00:00
Peter Tattam
2f9088a223 x86-64 emulation. 
Fixed IRETD in 64 bit mode
 2003-03-13 00:45:44 +00:00
Stanislav Shwartsman
cdfc3cbce4 instrumentation enchancements: 
* renamed CPU_ID to BX_CPU_ID.
  with this new name there is no possibility for name contentions and BX_CPU_ID
  definition could be moved out to NEED_CPU_REG_SHORTCUTS block

* returned back `unsigned BX_CPU::which_cpu(void)` function

* added BX_CPU_ID parameter for
	BX_INSTR_PHY_READ(a20addr, len);
	BX_INSTR_PHY_WRITE(a20addr, len);
    now it will be
	BX_INSTR_PHY_READ(cpu_id, a20addr, len);
	BX_INSTR_PHY_WRITE(cpu_id, a20addr, len);
 2003-02-13 15:04:11 +00:00
Peter Tattam
22d855a6c0 Fixed wrong RETF instructions for 64 bit mode. 2003-02-08 05:51:38 +00:00
Stanislav Shwartsman
4b59ecbc62 Implemented SSE/SSE2 duplicate opcodes in more intellegent way ... 2002-12-22 21:48:23 +00:00
Stanislav Shwartsman
e73df72525 implementation of additional SSE/SSE2 instructions 2002-12-22 20:42:56 +00:00
Stanislav Shwartsman
4906ffef7c Clean Peter's commit with MOVNTDQ instruction implementation 2002-12-20 09:11:39 +00:00
Peter Tattam
c173034663 Patches to round off the x86-64 emulation to get the Linux x86-64 kernel and 
sash to run.

1) fixed fetchdecode64.cc to fix the operand size at 64 bits in long mode for moves
   to/from CRx

2) minor patches to sse2.cc to fix unimplemented and 64 bit variants of sse2
instructions.
 2002-12-20 07:11:29 +00:00
Bryce Denney
9b2914fd1d - Temporarily revert Stanislav's changes between 2002-12-18 and 2002-12-19. 
Because source files were added/removed it would require an update
  of the windows and macos project files, so I want to wait until after 2.0.
    M Makefile.in         1.51 back to 1.50
    M cpu.h               1.121 back to 1.120
    M fetchdecode.cc      1.37 back to 1.36
    M fetchdecode64.cc    1.33 back to 1.32
    M sse.cc              1.17 back to 1.16
    A sse2.cc             1.27 back to 1.26  (added back)
    R sse_move.cc         removed
    R sse_pfp.cc          removed
- to bring these changes back again, all we have to do is
  "cvs update -j tmp-before1 -j tmp-after1"
 2002-12-19 05:53:18 +00:00
Stanislav Shwartsman
aa361badf2 Reorganized SSE/SSE2 code 
sse.cc -> general SSE stuff and SSE integer (MMX extensions)
sse_move.cc -> memory transfer and shuffle opcodes
sse_pfp.cc -> packed floating point operations
 2002-12-18 22:33:44 +00:00
Stanislav Shwartsman
bcd57bdcaf *** Current duplicate SSE/SSE2 instructions list *** 
MOVUPS_VpsWps  (0f 10) = MOVUPD_VpdWpd  (66 0f 10) = MOVDQU_VdqWdq (f3 0f 6f)
MOVUPS_WpsVps  (0f 11) = MOVUPD_WpdVpd  (66 0f 11) = MOVDQU_WdqVdq (f3 0f 7f)
MOVAPS_VpsWps  (0f 28) = MOVAPD_VpdWpd  (66 0f 28) = MOVDQA_VdqWdq (66 0f 6f)
MOVAPS_WpsVps  (0f 29) = MOVAPD_WpdVpd  (66 0f 29) = MOVDQA_WdqVdq (66 0f 7f)

MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)

ANDPS_VpsWps   (0f 54) = ANDPD_VpdWpd   (66 0f 54) = PAND_VpdWpd   (66 0f db)
ANDNPS_VpsWps  (0f 55) = ANDNPD_VpdWpd  (66 0f 55) = PANDN_VpdWpd  (66 0f df)
ORPS_VpsWps    (0f 56) = ORPD_VpdWpd    (66 0f 56) = POR_VpdWpd    (66 0f eb)
XORPS_VpsWps   (0f 57) = XORPD_VpdWpd   (66 0f 57) = PXOR_VpdWpd   (66 0f ef)

Removed dupes
 2002-11-25 21:58:55 +00:00
Bryce Denney
0a7cb3a43c - apply patch.ifdef-disabled-options. Comments from that patch are below: 
For a whole lot of configure options, I put #if...#endif around code that
  is specific to the option, even in files which are normally only compiled
  when the option is on.  This allows me to create a MS Visual C++ 6.0
  workspace that supports many of these options.  The workspace will basically
  compile every file all the time, but the code for disabled options will
  be commented out by the #if...#endif.

  This may one day lead to simplification of the Makefiles and configure
  scripts, but for the moment I'm leaving Makefiles and configure scripts
  alone.

  Affected options:
    BX_SUPPORT_APIC (cpu/apic.cc)
    BX_SUPPORT_X86_64 (cpu/*64.cc)
    BX_DEBUGGER (debug/*)
    BX_DISASM (disasm/*)
    BX_WITH_nameofgui (gui/*)
    BX_SUPPORT_CDROM (iodev/cdrom.cc)
    BX_NE2K_SUPPORT (iodev/eth*.cc, iodev/ne2k.cc)
    BX_SUPPORT_APIC (iodev/ioapic.cc)
    BX_IODEBUG_SUPPORT (iodev/iodebug.cc)
    BX_PCI_SUPPORT (iodev/pci*.cc)
    BX_SUPPORT_SB16 (iodev/sb*.cc)

Modified Files:
  cpu/apic.cc cpu/arith64.cc cpu/ctrl_xfer64.cc
  cpu/data_xfer64.cc cpu/fetchdecode64.cc cpu/logical64.cc
  cpu/mult64.cc cpu/resolve64.cc cpu/shift64.cc cpu/stack64.cc
  debug/Makefile.in debug/crc.cc debug/dbg_main.cc debug/lexer.l
  debug/linux.cc debug/parser.c debug/parser.y
  disasm/dis_decode.cc disasm/dis_groups.cc gui/amigaos.cc
  gui/beos.cc gui/carbon.cc gui/macintosh.cc gui/rfb.cc
  gui/sdl.cc gui/term.cc gui/win32.cc gui/wx.cc gui/wxdialog.cc
  gui/wxmain.cc gui/x.cc iodev/cdrom.cc iodev/eth.cc
  iodev/eth_arpback.cc iodev/eth_fbsd.cc iodev/eth_linux.cc
  iodev/eth_null.cc iodev/eth_packetmaker.cc iodev/eth_tap.cc
  iodev/eth_tuntap.cc iodev/eth_win32.cc iodev/ioapic.cc
  iodev/iodebug.cc iodev/ne2k.cc iodev/pci.cc iodev/pci2isa.cc
  iodev/sb16.cc iodev/soundlnx.cc iodev/soundwin.cc
 2002-11-19 05:47:45 +00:00
Stanislav Shwartsman
ccbc8e0ef7 MOVAPS/MOVAPD have a different exceptions 2002-11-15 12:44:39 +00:00
Stanislav Shwartsman
7ccf1de78f According to the Intel (and AMD) manuals a lot different SSE/SSE2 opcodes has EXACTLY the same operation. 
Deleted first three redundant opcodes (move integer data):
   MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
   MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
   MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
   MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)

Until under examination:
XORPS,XORPD
ORPS,ORPD
ANDPS,ANDPD
ANDNPS,ANDNPD
MOVUPS,MOVUPD
 2002-11-13 22:24:03 +00:00
Stanislav Shwartsman
968b2744f4 According to the Intel (and AMD) manuals a lot different SSE/SSE2 opcodes 
has EXACTLY the same operation.

Deleted first three redundant opcodes:
   MOVAPS_VpsWps  (0f 28) = MOVAPD_VpdWpd  (66 0f 28)
   MOVAPS_WpsVps  (0f 29) = MOVAPD_WpdVpd  (66 0f 29)
   MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)

Until checking:
XORPS,XORPD
ORPS,ORPD
ANDPS,ANDPD
ANDNPS,ANDNPD
MOVUPS,MOVUPD
MOVLPS,MOVLPD
MOVHPS,MOVHPD
 2002-11-13 21:35:17 +00:00
Stanislav Shwartsman
4363745725 Implemented SSE2 integer instructions: 
PACKSSDW_VdqWdq
PUNPCKHDQ_VdqWq
PUNPCKHWD_VdqWq
PUNPCKHBW_VdqWq
PUNPCKHQDQ_VdqWq
MOVD_EdVd
MOVD_VdqEd
 2002-11-08 12:47:24 +00:00