implementation of additional SSE/SSE2 instructions
This commit is contained in:
Stanislav Shwartsman
parent
1cd38bb7dd
commit
e73df72525
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.39 2002-12-20 09:11:37 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.40 2002-12-22 20:42:56 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -235,6 +235,12 @@ ANDNPS_VpsWps (0f 55) = ANDNPD_VpdWpd (66 0f 55) = PANDN_VdqWdq (66 0f df)
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ORPS_VpsWps (0f 56) = ORPD_VpdWpd (66 0f 56) = POR_VdqWdq (66 0f eb)
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XORPS_VpsWps (0f 57) = XORPD_VpdWpd (66 0f 57) = PXOR_VdqWdq (66 0f ef)
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UNPCKHPS_VpsWq (0f 15) = PUNPCKHDQ_VdqWq (66 0f 6a)
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UNPCKLPS_VpsWq (0f 14) = PUNPCKLDQ_VdqWq (66 0f 62)
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UNPCKHPD_VpsWq (66 0f 15) = PUNPCKHQDQ_VdqWq (66 0f 6d)
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UNPCKLPD_VpsWq (66 0f 14) = PUNPCKLQDQ_VdqWq (66 0f 6c)
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*/
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f10[4] = {
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@ -266,15 +272,15 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f13[4] = {
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f14[4] = {
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/* -- */ { 0, &BX_CPU_C::UNPCKLPS_VpsWq },
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/* 66 */ { 0, &BX_CPU_C::UNPCKLPD_VpdWq },
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/* -- */ { 0, &BX_CPU_C::PUNPCKLDQ_VdqWq },
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/* 66 */ { 0, &BX_CPU_C::PUNPCKLQDQ_VdqWq },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f15[4] = {
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/* -- */ { 0, &BX_CPU_C::UNPCKHPS_VpsWq },
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/* 66 */ { 0, &BX_CPU_C::UNPCKHPD_VpdWq },
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/* -- */ { 0, &BX_CPU_C::PUNPCKHDQ_VdqWq },
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/* 66 */ { 0, &BX_CPU_C::PUNPCKHQDQ_VdqWq },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.36 2002-12-20 09:11:38 sshwarts Exp $
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// $Id: fetchdecode64.cc,v 1.37 2002-12-22 20:42:56 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -303,6 +303,12 @@ ANDNPS_VpsWps (0f 55) = ANDNPD_VpdWpd (66 0f 55) = PANDN_VdqWdq (66 0f df)
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ORPS_VpsWps (0f 56) = ORPD_VpdWpd (66 0f 56) = POR_VdqWdq (66 0f eb)
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XORPS_VpsWps (0f 57) = XORPD_VpdWpd (66 0f 57) = PXOR_VdqWdq (66 0f ef)
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UNPCKHPS_VpsWq (0f 15) = PUNPCKHDQ_VdqWq (66 0f 6a)
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UNPCKLPS_VpsWq (0f 14) = PUNPCKLDQ_VdqWq (66 0f 62)
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UNPCKHPD_VpsWq (66 0f 15) = PUNPCKHQDQ_VdqWq (66 0f 6d)
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UNPCKLPD_VpsWq (66 0f 14) = PUNPCKLQDQ_VdqWq (66 0f 6c)
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*/
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f10[4] = {
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@ -334,15 +340,15 @@ static BxOpcodeInfo_t BxOpcodeGroupSSE_0f13[4] = {
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f14[4] = {
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/* -- */ { 0, &BX_CPU_C::UNPCKLPS_VpsWq },
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/* 66 */ { 0, &BX_CPU_C::UNPCKLPD_VpdWq },
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/* -- */ { 0, &BX_CPU_C::PUNPCKLDQ_VdqWq },
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/* 66 */ { 0, &BX_CPU_C::PUNPCKLQDQ_VdqWq },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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static BxOpcodeInfo_t BxOpcodeGroupSSE_0f15[4] = {
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/* -- */ { 0, &BX_CPU_C::UNPCKHPS_VpsWq },
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/* 66 */ { 0, &BX_CPU_C::UNPCKHPD_VpdWq },
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/* -- */ { 0, &BX_CPU_C::PUNPCKHDQ_VdqWq },
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/* 66 */ { 0, &BX_CPU_C::PUNPCKHQDQ_VdqWq },
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/* F2 */ { 0, &BX_CPU_C::BxError },
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/* F3 */ { 0, &BX_CPU_C::BxError }
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};
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@ -28,6 +28,8 @@
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/* SSE: MEMORY MOVE OPERATIONS */
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/* *************************** */
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/* All these opcodes never generate SIMD floating point exections */
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/* MOVUPS: 0F 10 */
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/* MOVUPD: 66 0F 10 */
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/* MOVDQU: F3 0F 6F */
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@ -421,54 +423,6 @@ void BX_CPU_C::SHUFPD_VpdWpdIb(bxInstruction_c *i)
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#endif
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}
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void BX_CPU_C::UNPCKLPS_VpsWq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("UNPCKLPS_VpsWq: SSE instruction still not implemented"));
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#else
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BX_INFO(("UNPCKLPS_VpsWq: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::UNPCKHPS_VpsWq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("UNPCKHPS_VpsWq: SSE instruction still not implemented"));
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#else
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BX_INFO(("UNPCKHPS_VpsWq: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::UNPCKLPD_VpdWq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("UNPCKLPD_VpdWq: SSE2 instruction still not implemented"));
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#else
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BX_INFO(("UNPCKLPD_VpdWq: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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void BX_CPU_C::UNPCKHPD_VpdWq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("UNPCKHPD_VpdWq: SSE2 instruction still not implemented"));
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#else
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BX_INFO(("UNPCKHPD_VpdWq: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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/* 66 0F 60 */
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void BX_CPU_C::PUNPCKLBW_VdqWq(bxInstruction_c *i)
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{
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@ -545,10 +499,12 @@ void BX_CPU_C::PUNPCKLWD_VdqWq(bxInstruction_c *i)
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#endif
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}
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/* 66 0F 62 */
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/* UNPCKLPS: 0F 14 */
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/* PUNPCKLDQ: 66 0F 62 */
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void BX_CPU_C::PUNPCKLDQ_VdqWq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
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@ -570,7 +526,7 @@ void BX_CPU_C::PUNPCKLDQ_VdqWq(bxInstruction_c *i)
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/* now write result back to destination */
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BX_WRITE_XMM_REG(i->nnn(), result);
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#else
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BX_INFO(("PUNPCKLDQ_VdqWq: SSE2 not supported in current configuration"));
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BX_INFO(("UNPCKLPS/PUNPCKLDQ_VdqWq: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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@ -651,10 +607,12 @@ void BX_CPU_C::PUNPCKHWD_VdqWq(bxInstruction_c *i)
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#endif
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}
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/* 66 0F 6A */
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/* UNPCKHPS: 0F 15 */
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/* PUNPCKHDQ: 66 0F 6A */
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void BX_CPU_C::PUNPCKHDQ_VdqWq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
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@ -676,12 +634,14 @@ void BX_CPU_C::PUNPCKHDQ_VdqWq(bxInstruction_c *i)
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/* now write result back to destination */
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BX_WRITE_XMM_REG(i->nnn(), result);
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#else
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BX_INFO(("PUNPCKHDQ_VdqWq: SSE2 not supported in current configuration"));
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BX_INFO(("UNPCKHPS/PUNPCKHDQ_VdqWq: SSE not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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/* 66 0F 6C */
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/* UNPCKLPD: 66 0F 14 */
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/* PUNPCKLQDQ: 66 0F 6C */
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void BX_CPU_C::PUNPCKLQDQ_VdqWq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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@ -703,12 +663,14 @@ void BX_CPU_C::PUNPCKLQDQ_VdqWq(bxInstruction_c *i)
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/* now write result back to destination */
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BX_WRITE_XMM_REG(i->nnn(), op1);
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#else
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BX_INFO(("PUNPCKLQDQ_VdqWq: SSE2 not supported in current configuration"));
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BX_INFO(("UNPCKLPD/PUNPCKLQDQ_VdqWq: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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/* 66 0F 6D */
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/* UNPCKHPD: 66 0F 15 */
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/* PUNPCKHQDQ: 66 0F 6D */
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void BX_CPU_C::PUNPCKHQDQ_VdqWq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE >= 2
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@ -731,7 +693,7 @@ void BX_CPU_C::PUNPCKHQDQ_VdqWq(bxInstruction_c *i)
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/* now write result back to destination */
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BX_WRITE_XMM_REG(i->nnn(), result);
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#else
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BX_INFO(("PUNPCKHQDQ_VdqWq: SSE2 not supported in current configuration"));
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BX_INFO(("UNPCKHPD/PUNPCKHQDQ_VdqWq: SSE2 not supported in current configuration"));
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UndefinedOpcode(i);
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#endif
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}
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@ -864,7 +826,7 @@ void BX_CPU_C::MOVNTPS_MdqVps(bxInstruction_c *i)
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BX_CPU_THIS_PTR prepareSSE();
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if (i->modC0()) {
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BX_INFO(("MOVNTPS_MdqVps: must be memory reference"));
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BX_INFO(("MOVNTPS/PD/MOVNTDQ_MdqVdq: must be memory reference"));
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UndefinedOpcode(i);
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}
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