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Patches to round off the x86-64 emulation to get the Linux x86-64 kernel and 

sash to run.

1) fixed fetchdecode64.cc to fix the operand size at 64 bits in long mode for moves
   to/from CRx

2) minor patches to sse2.cc to fix unimplemented and 64 bit variants of sse2
instructions.
This commit is contained in:
Peter Tattam 2002-12-20 07:11:29 +00:00
parent 18bceefb93
commit c173034663
2 changed files with 25 additions and 6 deletions
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10
bochs/cpu/fetchdecode64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode64.cc,v 1.34 2002-12-19 05:53:17 bdenney Exp $
// $Id: fetchdecode64.cc,v 1.35 2002-12-20 07:11:29 ptrumpet Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1691,9 +1691,9 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 1D */ { 0, &BX_CPU_C::BxError },
/* 0F 1E */ { 0, &BX_CPU_C::BxError },
/* 0F 1F */ { 0, &BX_CPU_C::BxError },
/* 0F 20 */ { BxAnother, &BX_CPU_C::MOV_RdCd },
/* 0F 20 */ { BxAnother, &BX_CPU_C::MOV_RqCq },
/* 0F 21 */ { BxAnother, &BX_CPU_C::MOV_RdDd },
/* 0F 22 */ { BxAnother, &BX_CPU_C::MOV_CdRd },
/* 0F 22 */ { BxAnother, &BX_CPU_C::MOV_CqRq },
/* 0F 23 */ { BxAnother, &BX_CPU_C::MOV_DdRd },
/* 0F 24 */ { BxAnother, &BX_CPU_C::MOV_RdTd },
/* 0F 25 */ { 0, &BX_CPU_C::BxError },
@ -2209,9 +2209,9 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F 1D */ { 0, &BX_CPU_C::BxError },
/* 0F 1E */ { 0, &BX_CPU_C::BxError },
/* 0F 1F */ { 0, &BX_CPU_C::BxError },
/* 0F 20 */ { BxAnother, &BX_CPU_C::MOV_RdCd },
/* 0F 20 */ { BxAnother, &BX_CPU_C::MOV_RqCq },
/* 0F 21 */ { BxAnother, &BX_CPU_C::MOV_RdDd },
/* 0F 22 */ { BxAnother, &BX_CPU_C::MOV_CdRd },
/* 0F 22 */ { BxAnother, &BX_CPU_C::MOV_CqRq },
/* 0F 23 */ { BxAnother, &BX_CPU_C::MOV_DdRd },
/* 0F 24 */ { BxAnother, &BX_CPU_C::MOV_RdTd },
/* 0F 25 */ { 0, &BX_CPU_C::BxError },

21
bochs/cpu/sse2.cc
View File

@ -1200,8 +1200,19 @@ void BX_CPU_C::MOVNTI_MdGd(bxInstruction_c *i)
UndefinedOpcode(i);
}
#if BX_SUPPORT_X86_64
if (i->os64L()) {
Bit64u val64 = BX_READ_64BIT_REG(i->nnn());
write_virtual_qword(i->seg(), RMAddr(i), &val64);
}
else {
Bit32u val32 = BX_READ_32BIT_REG(i->nnn());
write_virtual_dword(i->seg(), RMAddr(i), &val32);
}
#else
Bit32u val32 = BX_READ_32BIT_REG(i->nnn());
write_virtual_dword(i->seg(), RMAddr(i), &val32);
#endif
#else
BX_INFO(("MOVNTI_MdGd: SSE2 not supported in current configuration"));
@ -2042,7 +2053,15 @@ void BX_CPU_C::MOVNTDQ_MdqVdq(bxInstruction_c *i)
#if BX_SUPPORT_SSE >= 2
BX_CPU_THIS_PTR prepareSSE();
BX_INFO(("MOVNTDQ_MdqVdq: SSE2 not supported in current configuration"));
if (i->modC0()) {
BX_INFO(("MOVNTDQ_MqPq: must be memory reference"));
UndefinedOpcode(i);
}
BxPackedXmmRegister reg = BX_READ_XMM_REG(i->nnn());
writeVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &reg);
//BX_INFO(("MOVNTDQ_MdqVdq: SSE2 not supported in current configuration"));
#else
BX_INFO(("MOVNTDQ_MdqVdq: SSE2 not supported in current configuration"));
UndefinedOpcode(i);