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3185 Commits

Author SHA1 Message Date
Stanislav Shwartsman
bc5af269b7 Fix some more code duplication with sclaar_arith.h 
Do not clear IA32_FEATURE_CTRL MSR on soft reset (will clear the VMX lock bit)
On real HW XSAVE/XRSTOR which is not 4-byte aligned cause #AC(0) intead of #GP(0) when alignment check is enabled
 2014-03-02 16:40:13 +00:00
Stanislav Shwartsman
402b2c01c9 Implemented AVX-512 conflict detection instructions (VPCONFLICT, VPLZCNT, VPBROADCASTMB2Q, VPBROADCASTMW2D) 
Only missed AVX-512 opcodes are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD
 2014-02-27 21:12:02 +00:00
Stanislav Shwartsman
695d245116 Implemented VRNDSCALE AVX-512 instructions. 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD
 2014-02-27 18:27:57 +00:00
Stanislav Shwartsman
f282fc4e75 use names instead of magic numbers 2014-02-26 20:49:23 +00:00
Stanislav Shwartsman
2f906d844c fix vmexit reason descriptions 2014-02-25 19:56:10 +00:00
Stanislav Shwartsman
01af7f5346 Implemented VRSQRT14 AVX-512 instructions & optimized legacy SSE RSQRTSS/PS instructions handling 
//
// The table lookup was reverse-engineered from VRSQRT14SS instruction implementation available
// in the Intel Software Development Emulator rev6.20 (released February 13, 2014)
// http://software.intel.com/en-us/articles/intel-software-development-emulator/
//

// TODO: find better way to emulate these instructions, I am sure the HW doesn't have 64K entry lookup tables

Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
 2014-02-25 18:57:49 +00:00
Stanislav Shwartsman
47b56a2174 regen dependencies in Makefile 2014-02-24 21:36:11 +00:00
Stanislav Shwartsman
38bcc164a7 Implemented VRCP14 AVX-512 instructions. 
//
// The table lookup was reverse-engineered from VRCP14SS instruction implementation available
// in the Intel Software Development Emulator rev6.20 (released February 13, 2014)
// http://software.intel.com/en-us/articles/intel-software-development-emulator/
//

// TODO: find better way to emulate these instructions, I am sure the HW doesn't have 64K entry lookup table

Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
 2014-02-24 21:31:52 +00:00
Stanislav Shwartsman
648221d419 rewritten xsave/xrestor for more modular functionality. todo: replace walk through state using simple for loop 2014-02-22 21:00:47 +00:00
Stanislav Shwartsman
0a1b4f1c7e added template for missing avx-512 instructions 2014-02-17 20:21:58 +00:00
Stanislav Shwartsman
5ab2bb363c fix of compilation err 2014-02-17 16:19:43 +00:00
Stanislav Shwartsman
7775483d5e Implemented VCVTPS2PH AVX-512 instruction 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
 2014-02-15 19:21:08 +00:00
Stanislav Shwartsman
b572e80818 bugfix and code cleanup 2014-02-12 20:31:22 +00:00
Stanislav Shwartsman
09414f2f4b implemented access to opmask AVX-512 registers from debugger, fixed enhdbg buffer overflow with EVEX enabled 2014-02-11 20:51:18 +00:00
Stanislav Shwartsman
41f926628c fixed bug in LOAD_BROADCAST_MASK_Half_VectorD method 2014-02-11 20:13:42 +00:00
Stanislav Shwartsman
9d97013067 bugfixes in softfloat unsigned conversions 2014-02-11 18:03:51 +00:00
Stanislav Shwartsman
18e9f1e70e bugfix 2014-02-11 17:47:52 +00:00
Stanislav Shwartsman
b510cf794b complete compressed displ feature support, bugfixes in AVX-512 code 2014-02-11 16:10:31 +00:00
Stanislav Shwartsman
ca4d2b5e6f cover some more opcodes with compressed displ 2014-02-10 21:49:41 +00:00
Stanislav Shwartsman
d257bf3e7d cover some more opcodes with compressed displ 2014-02-10 21:34:26 +00:00
Stanislav Shwartsman
9613e4b402 implementation of AVX-512 compressed displacement feature which is required for AVX-512 emu correctness (first step). todo: fix rest of EVEX opcodes 2014-02-10 21:12:08 +00:00
Stanislav Shwartsman
37330682ad remove code duplication, prepare for 512-bit evrsion of cvtps2ph 2014-02-08 19:18:17 +00:00
Stanislav Shwartsman
550e6bd307 moved (c) to year 2014 for few files 2014-02-06 17:06:25 +00:00
Stanislav Shwartsman
aea9ae1976 added definitions (CPUID bit, VMX fields and VMXEXIT reasons, etc) from recently published Intel SDM rev049 2014-02-06 17:05:20 +00:00
Stanislav Shwartsman
7a6727da34 implemented AVX-512 version of VCVTPH2PS 2014-02-04 20:32:54 +00:00
Stanislav Shwartsman
f047fef2a6 fixed gcc warning 2014-02-03 21:12:24 +00:00
Stanislav Shwartsman
ea390abd3c bugfixes in new GETMANT* instrs 2014-02-03 21:10:44 +00:00
Stanislav Shwartsman
b33f93b9f3 Implemented VGETMANT* AVX-512 instructions 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
 2014-02-03 20:40:46 +00:00
Stanislav Shwartsman
ac06ee46ae Implemented VPMOVSX*/VPMOVZX* AVX-512 instructions 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 26 VGETMANTPS
512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
NDS.LIG.66.0F3A.W1 27 VGETMANTSD
 2014-02-02 19:56:08 +00:00
Stanislav Shwartsman
55e1d53a48 implement DPPS/DPPD ops using existing primitives; added some missing defs 2014-02-02 18:57:25 +00:00
Stanislav Shwartsman
ca1b496efc small optimization 2014-02-01 19:23:41 +00:00
Stanislav Shwartsman
ef130ca145 convert some defines to enum 2014-01-31 19:40:34 +00:00
Stanislav Shwartsman
6eb1c7d255 fixed swapped sources of VEXTRACTF* with mask 2014-01-30 21:46:25 +00:00
Stanislav Shwartsman
ccb003b0e1 fixed swapped sources of VEXTRACTF* 2014-01-30 20:48:41 +00:00
Stanislav Shwartsman
41e13703a3 Implemented VEXTRACT* AVX-512 instructions 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.WIG 21 VPMOVSXBD
512.66.0F38.WIG 22 VPMOVSXBQ
512.66.0F38.WIG 23 VPMOVSXWD
512.66.0F38.WIG 24 VPMOVSXWQ
512.66.0F38.W0  25 VPMOVSXDQ

512.66.0F38.WIG 31 VPMOVSZBD
512.66.0F38.WIG 32 VPMOVSZBQ
512.66.0F38.WIG 33 VPMOVSZWD
512.66.0F38.WIG 34 VPMOVSZWQ
512.66.0F38.W0  35 VPMOVSzDQ

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 26 VGETMANTPS
512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
NDS.LIG.66.0F3A.W1 27 VGETMANTSD
 2014-01-30 20:31:08 +00:00
Stanislav Shwartsman
d990911cea bugfix 2014-01-28 19:52:51 +00:00
Stanislav Shwartsman
63e99da4af Implemented VALIGN* AVX-512 instructions 
Now only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.WIG 21 VPMOVSXBD
512.66.0F38.WIG 22 VPMOVSXBQ
512.66.0F38.WIG 23 VPMOVSXWD
512.66.0F38.WIG 24 VPMOVSXWQ
512.66.0F38.W0  25 VPMOVSXDQ

512.66.0F38.WIG 31 VPMOVSZBD
512.66.0F38.WIG 32 VPMOVSZBQ
512.66.0F38.WIG 33 VPMOVSZWD
512.66.0F38.WIG 34 VPMOVSZWQ
512.66.0F38.W0  35 VPMOVSzDQ

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 19 VEXTRACTF32x4
512.66.0F3A.W1 1B VEXTRACTF64x4
512.66.0F3A.W0 39 VEXTRACTI32x4
512.66.0F3A.W1 3B VEXTRACTI64x4

512.66.0F3A.W0 26 VGETMANTPS
512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
NDS.LIG.66.0F3A.W1 27 VGETMANTSD
 2014-01-28 19:36:46 +00:00
Stanislav Shwartsman
36ba25847f Implemented last missed AVX-512 unsigned convert instructions 
The only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.WIG 21 VPMOVSXBD
512.66.0F38.WIG 22 VPMOVSXBQ
512.66.0F38.WIG 23 VPMOVSXWD
512.66.0F38.WIG 24 VPMOVSXWQ
512.66.0F38.W0  25 VPMOVSXDQ

512.66.0F38.WIG 31 VPMOVSZBD
512.66.0F38.WIG 32 VPMOVSZBQ
512.66.0F38.WIG 33 VPMOVSZWD
512.66.0F38.WIG 34 VPMOVSZWQ
512.66.0F38.W0  35 VPMOVSzDQ

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
 512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
 NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
 512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
 NDS.LIG.66.0F38.W1 4F VRSQRT14SD

NDS.512.66.0F3A.W0 03 VALIGND
NDS.512.66.0F3A.W1 03 VALIGNQ

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 19 VEXTRACTF32x4
512.66.0F3A.W1 1B VEXTRACTF64x4
512.66.0F3A.W0 39 VEXTRACTI32x4
512.66.0F3A.W1 3B VEXTRACTI64x4

512.66.0F3A.W0 26 VGETMANTPS
 512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
 NDS.LIG.66.0F3A.W1 27 VGETMANTSD
 2014-01-28 12:57:38 +00:00
Stanislav Shwartsman
15979a52b6 implemented avx-512 getexp instructions 2014-01-27 21:25:07 +00:00
Stanislav Shwartsman
3798ed66b5 new function for disasm. todo: support it independently of CPU 2014-01-26 20:01:50 +00:00
Stanislav Shwartsman
2379590dde do not compile AVX objects if AVX support is not enabled in configure 2014-01-26 19:20:44 +00:00
Stanislav Shwartsman
4d4d194c16 implemented missed vpmul* avx-512 opcodes 2014-01-24 20:04:36 +00:00
Stanislav Shwartsman
8d6c6a4545 added one more missed perm* avx-512 opcode 2014-01-24 19:42:08 +00:00
Stanislav Shwartsman
7beb85b850 implemented vperm* avx-512 opcodes 2014-01-24 19:23:19 +00:00
Stanislav Shwartsman
fd8ddd8069 downgrade VMEXIT message to BX_DEBUG 2014-01-24 18:58:57 +00:00
Stanislav Shwartsman
407681c98a implemented some more avx-512 opcodes 2014-01-24 12:02:47 +00:00
Stanislav Shwartsman
fa60a654c8 bugfix for avx-512 2014-01-23 19:59:39 +00:00
Stanislav Shwartsman
79c11cacbe fixed compilation err without avx 2014-01-23 17:08:30 +00:00
Stanislav Shwartsman
33889cd02e implemented avx-512 vpermq opcode 2014-01-22 21:21:32 +00:00
Stanislav Shwartsman
99f7107dd1 code reorg 2014-01-22 19:59:13 +00:00
Stanislav Shwartsman
a21f03e69b implemented few more avx-512 cvt opcodes 2014-01-21 21:00:40 +00:00
Stanislav Shwartsman
d591c1dd34 implemented few more avx-512 cvt opcodes 2014-01-21 20:31:10 +00:00
Stanislav Shwartsman
9e90d9d9ae bugfix in cvtpd2udq opcode decoding with kmask 2014-01-20 22:07:35 +00:00
Stanislav Shwartsman
2ed0e91dfe fixed writing half vector for avx-512 2014-01-20 21:52:48 +00:00
Stanislav Shwartsman
4705ed6bdd more fixes for uint conversions based on latest QEMU patches by Tom Musta 2014-01-20 21:22:29 +00:00
Stanislav Shwartsman
649075527e fixes for convert to unsigned functions 2014-01-20 20:50:28 +00:00
Stanislav Shwartsman
cc112767a2 bugfixes 2014-01-19 21:19:41 +00:00
Stanislav Shwartsman
ee8d500ec0 fix for float32/64_to_uint32 cvt functions in softfloat 2014-01-19 20:47:48 +00:00
Stanislav Shwartsman
086fefeb29 cleanups 2014-01-19 20:30:40 +00:00
Stanislav Shwartsman
a63280a6d1 implemented few more AVX-512 cvt opcodes 2014-01-19 20:23:14 +00:00
Stanislav Shwartsman
ba52890538 implemented few more AVX-512 floating point convert instructions 2014-01-18 20:10:05 +00:00
Stanislav Shwartsman
a1e397b5a2 fixed decoding bug in avx-512 instruction tables 2014-01-12 13:37:29 +00:00
Stanislav Shwartsman
ce8c520c09 fixed operands for new instructions 2014-01-12 13:20:41 +00:00
Stanislav Shwartsman
5cdcd7bef7 Implemented AVX-512 VPMOV* down-conversion stores 2014-01-12 13:08:16 +00:00
Stanislav Shwartsman
72c710947c code cleanups 2014-01-12 09:31:22 +00:00
Stanislav Shwartsman
af29c8bd60 infrastructure change for avx-512: before going to more new instructions modelling 2014-01-10 19:40:38 +00:00
Stanislav Shwartsman
58470763fa implement few more avx-512 opcodes 2013-12-31 23:51:25 +00:00
Stanislav Shwartsman
350e3544ae fixed #UD condition for multi-byte prefix opcodes VEX/EVEX/XOP 2013-12-28 12:57:21 +00:00
Stanislav Shwartsman
e902a83a60 fixed segfault in AVX emulation 2013-12-22 21:16:10 +00:00
Stanislav Shwartsman
ada455c4b9 just coding style 2013-12-22 20:48:26 +00:00
Stanislav Shwartsman
e200d04ad5 implemented two AVX512 unsigned CVT instructions 2013-12-22 19:53:03 +00:00
Stanislav Shwartsman
776cabf4fe move canonical check of high part of page split access to another function to fix code duplication 2013-12-21 21:56:55 +00:00
Stanislav Shwartsman
543b6c8254 compilation fix 2013-12-21 21:08:35 +00:00
Stanislav Shwartsman
979e10b725 added simd_int.h functions for future use 2013-12-21 20:46:27 +00:00
Stanislav Shwartsman
8c3309bac0 regen dependencies for CPU sources 2013-12-17 21:15:15 +00:00
Stanislav Shwartsman
e30e66e481 insertf64x4 decode fix 2013-12-17 21:00:19 +00:00
Stanislav Shwartsman
da0cec4300 implemented AVX-512 VINSERTF*/VINSERTI* opcodes 2013-12-17 20:38:19 +00:00
Volker Ruppert
58019a1649 Renamed "ltdl.h" to "ltdl-bochs.h" to avoid conflicts with the include file 
that is a part of the libtool package. Updated Makefile dependencies.
TODO: check if we can get rid of the ltdl*.* files (this would be possible if
the ltdl library is always available if libtool is present).
 2013-12-17 19:57:40 +00:00
Stanislav Shwartsman
fc2cc377f8 fixes for AVX-512 2013-12-17 19:16:08 +00:00
Stanislav Shwartsman
734d1c7af8 implemented VFIXUPIMM AVX-512 opcodes 2013-12-17 16:44:46 +00:00
Stanislav Shwartsman
cdbc8a3f6f remove accidentally committed code 2013-12-15 20:50:02 +00:00
Stanislav Shwartsman
18f6a67d9d bugfix 2013-12-15 20:33:24 +00:00
Stanislav Shwartsman
51d0161148 implement few AVX-512 unsigned convert instructions 2013-12-15 20:07:57 +00:00
Stanislav Shwartsman
d3107f9f25 remove statement with no effect 2013-12-15 19:58:15 +00:00
Stanislav Shwartsman
7f98bbaea0 fix for float32_to_uint32_round_to_zero 2013-12-15 19:45:23 +00:00
Stanislav Shwartsman
8707e0626d starting to implement some AVX512 convert opcodes 2013-12-15 19:20:03 +00:00
Stanislav Shwartsman
a9b4513b8a insert/extractps do not support EVEX.b 2013-12-14 12:48:26 +00:00
Stanislav Shwartsman
cbcf30e911 implement EVEX SAE (suppress all exceptions) contol, implement AVX512 INSTERT/EXTRACTPS opcodes 2013-12-14 12:45:06 +00:00
Stanislav Shwartsman
15756a31cd implemented EVEX MOVD/MOVQ opcodes, fixes in softfloat 2013-12-13 12:05:47 +00:00
Stanislav Shwartsman
374b8f615a softloat: implemented some more unsigned integer vs float conversions 2013-12-12 21:00:59 +00:00
Stanislav Shwartsman
9c179bade8 fixed evex.b validation condition 2013-12-10 21:48:17 +00:00
Stanislav Shwartsman
258a60f3fa Implemented AVX512 EXPAND/COMPRESS instructions 
Fixed memory access size for AVX shift instructions with shift count in memory
Do not allow to encode with EVEX.b instructions which do not support implicit broadcast 
softfloat: prepare float32/64 to uint32 conversion functions
 2013-12-10 21:09:46 +00:00
Stanislav Shwartsman
9a4d947a28 implemented avx-512 cvt*2si instructions 2013-12-09 20:52:39 +00:00
Stanislav Shwartsman
ccb1d86d6e code cleanups 2013-12-09 20:36:24 +00:00
Stanislav Shwartsman
d20c81417c Implemented VSHUFF32x4/64x2, VSHUFI32x4/64x2 AVX512 instructions 
Implemented AVX512 blend instructions
Do not allow setting of EVEX.b in reg form when no floating point exceptions could be generated by instruction
 2013-12-09 19:09:37 +00:00
Stanislav Shwartsman
4c78ca8c1c implemented mask load for most of the load+op instructions. all take care for instructions which do not support maksing of memory exceptions (shuffle and permutes) 2013-12-08 21:54:59 +00:00
Stanislav Shwartsman
8836d1aa2d added mask destination to disasm 2013-12-08 17:01:30 +00:00
Stanislav Shwartsman
0621f2a983 extend movddup/sldup/shdup to 512-bit vlen 2013-12-07 20:58:32 +00:00
Stanislav Shwartsman
d681bd868f fixed typo bug in xmm accessor definition 2013-12-07 20:48:41 +00:00
Stanislav Shwartsman
1e474ede51 fixed corrupted fetchdecode from svn rev12001 2013-12-07 20:30:27 +00:00
Stanislav Shwartsman
7ed017a56d implemented avx-512 gather/scatter 2013-12-07 20:15:56 +00:00
Stanislav Shwartsman
3154c3682e fixed decoding of RDRAND instructions 2013-12-07 07:17:04 +00:00
Stanislav Shwartsman
8c3d0aed7a added #UD condition for wrong EVEX.LL setting 2013-12-05 20:40:53 +00:00
Stanislav Shwartsman
ca2793ac76 Debugger: fixed param tree access to 64-bit variables (need to use get64() instead of get()) 
Debugger: if AVX-512 if not supported by current configuration do not print high256 of vector registers and zmm15..zmm31 in AVX command
Implement VBROADCASTF64x4, VBROADCASTF32x4, VBROADCASTFI64x4, VBROADCASTI32x4 AVX-512 instructions
Fetchdecode optimizations and bugfixes
 2013-12-05 19:17:16 +00:00
Stanislav Shwartsman
cfc8a0ad38 get rid of BX_MEM_NO_VVV decoding form (by splitting just two opcode groups using Split11B) 2013-12-04 20:15:22 +00:00
Stanislav Shwartsman
401caf168d Implemented VPERMILPS/PD AVX512 instructions 
Implemented VPTERNLOGD/Q AVX512 instructions
Implemented VPBROADCASTD/Q, VPBROADCASTPS/PD AVX512 instructions
Implemented VTEST* AVX512 instructions
Bugfixes in EVEX decoding tables
 2013-12-04 18:30:44 +00:00
Stanislav Shwartsman
a5153c348f fixed bugs in vcmp* avx512 opcodes 2013-12-03 22:16:22 +00:00
Stanislav Shwartsman
ccdd21a76b small diet to the avx-512 files - remove code duplication 2013-12-03 21:32:04 +00:00
Stanislav Shwartsman
18922fa1a3 added sanity check assert 2013-12-03 17:41:13 +00:00
Stanislav Shwartsman
6d9b16e0f7 Implemented VCMPPS/PD/SS/SD AVX512 instructions 
Implemented AVX512 shift/rotate instructions
 2013-12-03 15:44:23 +00:00
Stanislav Shwartsman
ba505677d2 bugfix for avx-512 masked load with mask all-zero 2013-12-02 20:46:26 +00:00
Stanislav Shwartsman
a85a9081b7 use shorter opcode names in the debug prints (skip the BX_IA_ prefix) 2013-12-02 20:06:59 +00:00
Stanislav Shwartsman
0683b00535 implemented more avx-512 opcodes 2013-12-02 19:16:48 +00:00
Stanislav Shwartsman
79456eb7e1 Implemented VPCMP* AVX512 instructions 
Implemented VMOVNTPS/PD/DQ AVX512 instructions
Implemented VMOVNTDQA AVX512 instruction
Bugfixes for AVX-512
 2013-12-02 18:05:18 +00:00
Stanislav Shwartsman
b78489628d make use of new accessor 2013-12-01 22:21:55 +00:00
Stanislav Shwartsman
287523e19a add dedicated 8bit low register accessor 2013-12-01 22:18:38 +00:00
Stanislav Shwartsman
4aa5199d0c added missing decoding for avx-512 fma flavor 2013-12-01 21:50:19 +00:00
Stanislav Shwartsman
4f158aef5f Fixed 8-bit opmask read 
Added opmask printout for AVX dump in dbg_main.cc
 2013-12-01 20:50:01 +00:00
Stanislav Shwartsman
c7b03eb00b implement avx-512 vpabsd/q instructions 2013-12-01 20:10:39 +00:00
Stanislav Shwartsman
2b83146ae2 more avx-512 instructions implemented 2013-12-01 19:39:18 +00:00
Stanislav Shwartsman
37d6403681 typo fix 2 2013-11-30 19:57:03 +00:00
Stanislav Shwartsman
32c91015a7 typo fix 2013-11-30 19:55:10 +00:00
Stanislav Shwartsman
fb2521a1fe implemented avx-512 vsqrt instructions 2013-11-30 19:33:08 +00:00
Stanislav Shwartsman
7db6c647b0 fixed memory access decoding in presence of evex prefix 2013-11-30 18:51:27 +00:00
Stanislav Shwartsman
ac82b38736 fixed typos causing compilation err 2013-11-30 18:39:22 +00:00
Stanislav Shwartsman
d082c6a0f9 implemented avx-512 masked load instructions 2013-11-30 18:37:25 +00:00
Stanislav Shwartsman
f76c85dca9 fixed 512-bit VL encoding in EVEX 2013-11-29 21:05:29 +00:00
Stanislav Shwartsman
b820b7af57 fixed zmm reg name in disasm 2013-11-29 20:52:34 +00:00
Stanislav Shwartsman
61deec2689 fixed zmm reg name in disasm 2013-11-29 20:48:31 +00:00
Stanislav Shwartsman
11f082af82 Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions 
Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions
Fix vector length values for AVX-512 (512-bit vector should have length 4)
support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions
move AVX512 load/store and register move operations into dedicated file avx512_move.cc
 2013-11-29 20:22:31 +00:00
Stanislav Shwartsman
031583dbd9 moved avx masked load/store operations to separate functions 2013-11-29 18:15:48 +00:00
Stanislav Shwartsman
21bb1363ac avx512 move functions introduced 2013-11-29 11:10:34 +00:00
Stanislav Shwartsman
1a735e9fdf bugfix for decoding segment prefix with EVEX 2013-11-28 21:28:50 +00:00
Stanislav Shwartsman
4680c22d0e implemented avx-512 masked register moves 2013-11-28 20:58:31 +00:00
Stanislav Shwartsman
b7f950aa5c more coding for avx512 2013-11-26 19:22:31 +00:00
Stanislav Shwartsman
1beeb33b51 implemented avx-512 fma instructions (in seperate file), fixes in avx-512 decoding tables 2013-11-25 20:42:24 +00:00
Stanislav Shwartsman
eb9778220d fixed decoding of 0f3a opcode map 2013-11-20 20:46:03 +00:00
Stanislav Shwartsman
b553591bb4 fixed compilation error under AVX 2013-11-20 17:33:57 +00:00
Stanislav Shwartsman
7f8429c643 fix code duplication in fetchdecode modules 2013-11-20 16:00:24 +00:00
Stanislav Shwartsman
9b22ba7edf softfloat: added float to uint64 conversion operations (based on QEMU patch by Tom Musta) 2013-11-10 19:08:12 +00:00
Stanislav Shwartsman
3be7e5884b added lock prefix used info into bx_Instriction_c and use it in disasm 2013-11-08 21:43:21 +00:00
Stanislav Shwartsman
4b03247287 fixed compilation error with vs2008 2013-10-25 05:36:10 +00:00
Stanislav Shwartsman
d9fc472ba7 Added VMEXIT instrumentation callback 
Fixed possible RSP corruption in SMP mode - the speculative_rsp variable might be not reset properly
 2013-10-23 21:18:19 +00:00
Stanislav Shwartsman
d52adaa0ee improve debug print to the log file which is printed in case of triple fault - tell VMX host/guest info 2013-10-20 16:41:34 +00:00
Stanislav Shwartsman
39f2f172b5 fixed PAUSE/NOP decoding bug in prev commit 2013-10-16 05:46:57 +00:00
Stanislav Shwartsman
8bcc8cf073 split PREFETCH opcode to Group16 for better disasm of bxInstruction_c 2013-10-15 21:21:28 +00:00
Stanislav Shwartsman
940c2a1c8e fixes for disasm 2013-10-15 17:19:18 +00:00
Stanislav Shwartsman
e1012f1165 add vmcs revision id interface to CPUID class 2013-10-14 18:35:56 +00:00
Stanislav Shwartsman
9fb7384e6b finish sse tables cleanup in disasm and fetchdecode 2013-10-11 20:09:51 +00:00
Stanislav Shwartsman
05d2bb2b9a fixed typo bug caused spurios #UD on SSE shift 2013-10-11 06:20:42 +00:00
Stanislav Shwartsman
5fc491e9b6 resolve aliases after actually decoding base instr 2013-10-11 05:58:30 +00:00
Stanislav Shwartsman
34025e469f resolve aliases after actually decoding base instr 2013-10-11 05:54:18 +00:00
Stanislav Shwartsman
582bf84bae apply same optimization to disasm as well 2013-10-10 21:00:26 +00:00
Stanislav Shwartsman
46e36b463b size-optimization for SSE opcode tables 2013-10-10 20:21:15 +00:00
Stanislav Shwartsman
2ec138f96e Apply patch from developers mailing list: 
bx_debug: allow expressions instead of numerals, where relevant
by Samium Gromoff

fix code duplication in fma handlers
 2013-10-09 20:04:05 +00:00
Stanislav Shwartsman
0b2e533a55 more avx512 instructions done 2013-10-09 19:45:36 +00:00
Stanislav Shwartsman
d6d1c707df implemented set of integer avx512 instructions 2013-10-08 19:44:52 +00:00
Stanislav Shwartsman
70230049fa opmask_ok support in fetchdecode32.cc 2013-10-08 18:40:10 +00:00
Stanislav Shwartsman
09254eb474 avx512 implementation fixes and next steps 2013-10-08 18:31:18 +00:00
Stanislav Shwartsman
8446685ba2 fixed FPU and MMX disasm 2013-10-07 20:55:43 +00:00
Stanislav Shwartsman
5724013e7d updates to AVX512 decoding and CPUID 2013-10-07 20:39:34 +00:00
Stanislav Shwartsman
cb0eee9456 disasm fixes 2013-10-07 19:02:53 +00:00
Stanislav Shwartsman
059769e2a6 disasm bug fixes 2013-10-06 20:42:13 +00:00
Stanislav Shwartsman
f0b917ca15 disasm fixes 2013-10-06 19:27:40 +00:00
Stanislav Shwartsman
e55611df21 disasm fixes 2013-10-06 19:04:52 +00:00
Stanislav Shwartsman
add8eea761 disasm bug fixes 2013-10-06 18:37:56 +00:00
Stanislav Shwartsman
f1f35a236c disasm: Id form in 32-bit should be sign-extended to 64-bit 2013-10-06 18:10:58 +00:00
Stanislav Shwartsman
a392612b03 fixed compilation err in cpu-level=3 config 2013-10-06 18:01:25 +00:00
Stanislav Shwartsman
e1512ccaf8 fixed warning under new MSDEV compiler 2013-10-05 19:35:00 +00:00
Stanislav Shwartsman
fd370a4d41 fixes in disasm, added example of using bxInstruction_c disasm into dbg_main.cc (commented out for now) 2013-10-05 19:32:09 +00:00
Stanislav Shwartsman
b1d703e47c fixed compilation with x86-64 off 2013-10-05 18:51:28 +00:00
Stanislav Shwartsman
67bce7af97 fixed memref disasm 2013-10-05 11:00:31 +00:00
Stanislav Shwartsman
d4bfbffdbb disasm fixes 2013-10-05 08:34:09 +00:00
Stanislav Shwartsman
c9a1f259cb fixed compilation error in new disasm module under SMP config 2013-10-04 18:14:54 +00:00
Stanislav Shwartsman
ba1249ed15 disasm fixes 2013-10-04 17:26:56 +00:00
Stanislav Shwartsman
85b0402668 fixes for disasm 2013-10-02 19:23:34 +00:00
Stanislav Shwartsman
8c60799e72 fix for new disasm interface 2013-10-01 20:17:21 +00:00
Stanislav Shwartsman
e592f81209 updates to internal disasm 2013-10-01 18:47:55 +00:00
Stanislav Shwartsman
147d788022 few fixes in new disasm module 2013-09-30 20:16:52 +00:00
Stanislav Shwartsman
fd383435f0 - Initial code for bx_Instruction_c disassembler which (together with Bochs decoder) will replace Bochs disasm module someday (very soon). 
The code already knows to disasm most of the opcodes with their operands.

- Split according to OSIZE opcodes RDFSBASE/WRFSBASE / RDGSBASE/WRGSBASE both for disasm and performance

- Minimize amount of opcode forms in ia_opcodes.h again.
  For example Udq means the same as Wdq but with no memory form.
 2013-09-30 19:01:42 +00:00
Stanislav Shwartsman
fa06b26c88 Make possible to deliver instruction name for disasm directly from bx_ia_opcode_name (some opcodes were renamed). 
Fixed bug in stack optimization in 64-bit mode (should result in some speedup)
ia_opcode.h - eliminate some OP_M cases when they actually meant "value of specific type in the memory"
example: "MOVBE Md, Gd" actually means "MOVBE Ed, Gd"which just not have reg/reg form.
 2013-09-26 18:54:32 +00:00
Stanislav Shwartsman
839b841c38 added register type to register source information in decoder 2013-09-24 09:50:25 +00:00
Stanislav Shwartsman
ff79cbd596 Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm) 
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.

Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
 2013-09-24 05:21:00 +00:00
Stanislav Shwartsman
f791802286 infrastructure change for several AVX handlers to support any VL and only 128/256 2013-09-21 20:40:57 +00:00
Stanislav Shwartsman
404b8b1475 move end of trace indication to separate 'flags' field of bx_ia_opcode. this saves a lot of code duplication and simplifies the decode tables. also on the way found missing SVM opcodes that missed 'end of trace' mark 2013-09-21 18:58:01 +00:00
Stanislav Shwartsman
047b17d415 fixed typo in makefile 2013-09-21 10:52:18 +00:00
Stanislav Shwartsman
cd55ace8c8 fixed compilation err, rename opcode and handler functions for PUSHA/POPA instructions 2013-09-21 10:03:49 +00:00
Stanislav Shwartsman
2526282ed9 small additions for avx512 2013-09-20 18:27:33 +00:00
Stanislav Shwartsman
3803ac7fbe fixed evex override mscsr controls 2013-09-19 21:38:25 +00:00
Stanislav Shwartsman
0441f82b02 implement more AVX512 instructions 2013-09-19 20:35:55 +00:00
Stanislav Shwartsman
55f9155bc5 add new file 2013-09-19 18:32:39 +00:00
Stanislav Shwartsman
8b3a0acde9 implement first EVEX instructions - VADDPS/PD/SS/SD 2013-09-19 18:31:30 +00:00
Stanislav Shwartsman
8e71a86542 seve vex prefix value to the indication of vex prefix used 2013-09-18 18:01:48 +00:00
Stanislav Shwartsman
da0e2baf22 avoid segfault when decoding incorrectly encoded kmask op 2013-09-17 21:01:24 +00:00
Stanislav Shwartsman
d169860f6c added masked operations to simd_pfp.h, optimize simd_int.h, rewrite dpps instr using new masked op from simd_pfp.h 2013-09-17 20:49:26 +00:00
Stanislav Shwartsman
aa25c1db6a name convention change - search and replace 2013-09-17 17:34:20 +00:00
Stanislav Shwartsman
b6c39a3176 merge AVX and SSE .bochsrc options to single SIMD option which will configure SSE and AVX together 2013-09-16 19:50:36 +00:00
Stanislav Shwartsman
1cebe5f83d rellback part of commit with xmm register access interface changes - doesn't work for big endian hosts 2013-09-16 19:10:42 +00:00
Stanislav Shwartsman
0cb0acc30f added evex decode tables - next step to populate them :) 2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
1e1fa45cac fixed makefile after file rename 2013-09-08 20:16:38 +00:00