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404 Commits

Author SHA1 Message Date
Stanislav Shwartsman
beafa7c88b improved x86 hw code bp handling 2011-06-24 13:38:34 +00:00
Stanislav Shwartsman
29e3f6e762 remove trace cache disabled mode from the code. next step going to be - introducing new optimization features based on trace cache 2011-06-01 20:34:04 +00:00
Stanislav Shwartsman
a02ddb36d2 undo a change from 2 weeks ago that cause correctness failure 2011-05-06 08:03:45 +00:00
Stanislav Shwartsman
c44f82f4ac small cleanup 2011-04-25 20:26:22 +00:00
Stanislav Shwartsman
024a1ace38 move X2APIC to be .bochsrc option, rework of the cpuid code 2011-04-21 13:27:42 +00:00
Stanislav Shwartsman
69b829a935 small fixes 2011-04-12 06:05:31 +00:00
Stanislav Shwartsman
4de76b0571 introduced victim cache for a trace cache structure. 
Allows to significantly  cut trace cache miss latenct and find data in victim cahe instead of redoding it 
8 entries VC in parallel with direct map 64K entries
 2011-03-25 23:06:34 +00:00
Stanislav Shwartsman
7664c55b08 first fixups after AVX 
(and for AVX)
 2011-03-20 18:27:31 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
acb83acfa7 Fixed decoding of CRC32 instr 2011-02-26 20:43:11 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
2d3f3668c7 Fixed IRET 64-bit mode bug 
Support for 32 float copare methods for AVX
ckeanups in fetchdecode
 2011-02-13 06:10:11 +00:00
Stanislav Shwartsman
12005d92cf split more SSE ops 2011-01-21 19:46:44 +00:00
Stanislav Shwartsman
0de2b305bc split SSE opcode 2011-01-21 19:21:16 +00:00
Stanislav Shwartsman
a31103e7d8 optimize fetchdecode tables - part2 2011-01-21 16:07:51 +00:00
Stanislav Shwartsman
fbc9b8b190 phase1 of opcode tables optimization 2011-01-20 16:24:42 +00:00
Stanislav Shwartsman
8c5c078b13 optimize sse and mmx code 2011-01-16 20:42:28 +00:00
Stanislav Shwartsman
a80b44b6db split more sse ops 2011-01-09 20:18:02 +00:00
Stanislav Shwartsman
a1bc92a46b split more SSE opcodes 2011-01-08 11:20:29 +00:00
Stanislav Shwartsman
205351f44e Split R/M all SSE fetchdecode tables 
- next step optimize tables
 2011-01-08 09:53:52 +00:00
Stanislav Shwartsman
f9f868247a split more SSE ops 2010-12-30 20:35:10 +00:00
Stanislav Shwartsman
25b1e2e58d split more SSE ops 2010-12-26 20:41:47 +00:00
Stanislav Shwartsman
c005444d5b split more SSE opcodes 2010-12-25 07:59:15 +00:00
Stanislav Shwartsman
040a8e1a3a split bunch of SSE opcodes 2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
43600f3756 complete rework of SSE code 
next step - split all SSE opcodes by ModC0
 2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
29a674e520 split rd/wr CR opcodes for simplicity 2010-12-19 22:36:19 +00:00
Stanislav Shwartsman
d60b7c0919 rename accessor for opcodeReg() in instruction 2010-12-06 21:45:56 +00:00
Stanislav Shwartsman
49c85b07f6 Fixed address size wrap 2010-10-18 22:19:45 +00:00
Stanislav Shwartsman
f655e33779 imm mode2 could be only with imm_mode1 2010-09-25 10:17:04 +00:00
Stanislav Shwartsman
75f2ae9c18 fetchdecode simplification rework 2010-09-25 09:55:40 +00:00
Stanislav Shwartsman
369aba757d style change 2010-09-23 20:38:02 +00:00
Stanislav Shwartsman
a0705392d3 Fixed failure on BE hosts 2010-09-12 17:33:34 +00:00
Stanislav Shwartsman
1107ce138e small fetchdecode optimization 2010-09-07 19:54:50 +00:00
Stanislav Shwartsman
55cb12badf fixed missed canonical failure on system access 2010-07-22 20:12:25 +00:00
Stanislav Shwartsman
91ac0df65c implemented GS/FS BASE access instructions published in _319433-007.pdf document 2010-07-22 16:41:59 +00:00
Stanislav Shwartsman
67aec1dc22 warning fix 2010-05-26 18:37:54 +00:00
Stanislav Shwartsman
84880793f3 optimize for speed 2010-05-26 18:34:25 +00:00
Stanislav Shwartsman
8d8d1590f5 fetchdecide rework for AVX (0xF3 SSE prefix encoded as 2 in VEX) 2010-05-23 19:17:41 +00:00
Stanislav Shwartsman
1c00193616 cleanup 2010-05-22 10:43:39 +00:00
Stanislav Shwartsman
fff0a79aea a little simpler fetchdecode 2010-05-21 21:17:32 +00:00
Stanislav Shwartsman
3dfcfd0ccd Split shift opcodes | optimize SAR opcode 2010-05-18 07:28:05 +00:00
Stanislav Shwartsman
9c69b15ecb fetchdecode tables reorg phase1 2010-05-13 05:38:24 +00:00
Stanislav Shwartsman
1f0d4f9663 compilation fix 2010-04-29 21:04:23 +00:00
Stanislav Shwartsman
43bc0f1f2b optimize some of x87 tables 2010-04-16 19:52:44 +00:00
Stanislav Shwartsman
689ecc57dd split 2 more SSE opcodes 2010-04-08 17:35:32 +00:00
Stanislav Shwartsman
62d316e5cf fix 2010-03-31 14:03:07 +00:00
Stanislav Shwartsman
845af0dc24 decode fix 2010-03-30 16:39:57 +00:00
Stanislav Shwartsman
26688136a7 bugfix 2010-03-30 15:01:09 +00:00
Stanislav Shwartsman
e88e168081 bswap undefined behavior 2010-03-19 10:00:48 +00:00
Stanislav Shwartsman
033a20b3b2 allow to configure CPU features at runtime - implemened on example of SSE/AES/MOVBE/POPCNT 2010-02-25 22:04:31 +00:00
Stanislav Shwartsman
70dc124b3a 1st step of moving CPU options to runtime 2010-02-24 19:27:51 +00:00
Stanislav Shwartsman
5f89b554aa split few more opcodes 2010-02-10 17:21:15 +00:00
Stanislav Shwartsman
c841eaa953 fixes and cleanups in disasm and decoder 2010-02-09 19:44:25 +00:00
Stanislav Shwartsman
be646e042b cleanup 2010-02-08 14:54:26 +00:00
Stanislav Shwartsman
4217d76d26 fetchdecode code duplication cleanup 2010-02-06 17:14:07 +00:00
Stanislav Shwartsman
856e2491ba undo the change 2010-02-06 10:15:26 +00:00
Stanislav Shwartsman
4a70e73b9d compilation fix + code duplication fix 2010-02-06 09:59:52 +00:00
Stanislav Shwartsman
26c7abf988 decode tables opt 2010-02-01 07:59:22 +00:00
Stanislav Shwartsman
da93b6c3a6 undo wrong change 2010-01-31 19:39:46 +00:00
Stanislav Shwartsman
c3a73d3579 comment out CS.LIMIT demotion fix - it causes too big slowdown. 
Need to think about better solution
+ small optimization
 2010-01-31 18:06:45 +00:00
Stanislav Shwartsman
eae084920a optimized decode tables 2010-01-31 09:45:27 +00:00
Stanislav Shwartsman
dc02d836ce Fix POPCNT decode tables 2010-01-29 10:16:28 +00:00
Stanislav Shwartsman
cf6a4f5417 added ia_opcode into bxInstruction class 2010-01-09 15:11:32 +00:00
Stanislav Shwartsman
30c9eef6f9 small optimization 2009-12-21 13:38:06 +00:00
Stanislav Shwartsman
edaf19f0a1 Split MOVQ_PqQq opcode 2009-12-14 11:55:42 +00:00
Stanislav Shwartsman
bd60e0264c change Copyright to Bochs Project 2009-12-04 16:53:12 +00:00
Stanislav Shwartsman
553ca8af01 split more SSE ops 2009-11-25 20:49:47 +00:00
Stanislav Shwartsman
6819ab4eb7 split sse opcodes 2009-11-23 18:21:23 +00:00
Stanislav Shwartsman
5bfbc9df5f RETF bug fuxed 2009-11-19 20:00:35 +00:00
Stanislav Shwartsman
fbd9f291f7 small optimization 2009-11-06 18:19:01 +00:00
Stanislav Shwartsman
6d9271634d bugfix + small optimization 2009-11-05 21:07:18 +00:00
Stanislav Shwartsman
d16afb6d47 ia_opcodes instrumentation 2009-10-31 20:02:44 +00:00
Stanislav Shwartsman
78e4b3d616 split SSE move instructions 2009-10-24 11:17:51 +00:00
Stanislav Shwartsman
8e3276cf14 split opcodes by ModC0 2009-08-22 11:47:42 +00:00
Stanislav Shwartsman
9d4c24b6a3 Split instruction 32/64 2009-04-06 18:44:28 +00:00
Stanislav Shwartsman
e5be60be64 Fixed lazy flags bug I added in one of my prev merges 
ICACHE code reorganization
 2009-03-22 21:12:35 +00:00
Stanislav Shwartsman
9417cbee63 - cpu optimizations 9remove redundant, add new) 2009-03-13 18:02:33 +00:00
Stanislav Shwartsman
6dac964b27 Two more prefix66 opcodes 2009-02-28 09:28:18 +00:00
Stanislav Shwartsman
b9de22961c minimize SSE tables, minor speedup in SSE code 2009-02-26 21:57:01 +00:00
Stanislav Shwartsman
21e2692997 Fixed bug in trace cache mode 2009-02-06 15:03:47 +00:00
Stanislav Shwartsman
f8185a6bc6 Added Intel VMX emulation to Bochs CPU 2009-01-31 10:43:24 +00:00
Stanislav Shwartsman
0325c120b2 Separate PAUSE instruction from regular NOP 2009-01-27 20:29:05 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
0ff68a2aa2 Fixed XSAVE decode in x86-64 mode 2009-01-10 16:01:55 +00:00
Stanislav Shwartsman
a9c77eb75d Try to optimize individual instructions after fetchdecode 2008-09-16 19:20:03 +00:00
Stanislav Shwartsman
7566faf948 A bit simplify FPU decoding 2008-09-16 18:28:53 +00:00
Stanislav Shwartsman
d57a211df9 Fixed handling of prefixes for EMMS 
Small FPU optimization
 2008-09-12 20:59:31 +00:00
Stanislav Shwartsman
b03f940807 optimize seg_override decoding 2008-09-08 16:15:59 +00:00
Stanislav Shwartsman
c1306f7d75 small non-significant speedups 2008-09-06 21:10:40 +00:00
Stanislav Shwartsman
b3b2f77675 Reduce size of Bochs static tables by changing from bx_bool (which is 32bit) to Bit8u 2008-09-06 18:21:29 +00:00
Stanislav Shwartsman
0cd11fd385 Updated instrumentation callbacks - removed fetchdecode_completed callback 2008-09-06 17:49:32 +00:00
Stanislav Shwartsman
a0e395188f Fixed merge error 2008-08-29 20:43:05 +00:00
Stanislav Shwartsman
b96f78dc0a Some kind of big change in fetchdecode tables invented in order to compress the tables for better host data cache utilization 2008-08-29 19:23:03 +00:00
Stanislav Shwartsman
9a2072bba6 More fetchdecode optimization 2008-08-23 22:34:17 +00:00
Stanislav Shwartsman
991ae348cb Clean invalidate_prefetch_q when not needed 2008-08-23 13:55:37 +00:00
Stanislav Shwartsman
a8adb36dc2 Implemented MOVBE Intel Atom(R) instruction 2008-08-11 18:53:24 +00:00
Stanislav Shwartsman
b61017e5b6 Split more opcodes using new LOAD technique 2008-08-10 21:16:12 +00:00
Stanislav Shwartsman
1da5943f1a More use of LOAD_Ex method 2008-08-10 19:34:28 +00:00
Stanislav Shwartsman
0d90ab0478 Completely new way to handle LD+OP cases - allows to significantly reduce number of BX_CPU_C methods 2008-08-09 21:05:07 +00:00
Stanislav Shwartsman
24e0b53720 This more ellegant way to have debug info for BxError and not lose any performace 2008-08-09 19:18:09 +00:00
Stanislav Shwartsman
0127415ba6 Clear some duplicated arithmetic opcodes - difference only in operands order 2008-07-13 09:59:59 +00:00
Stanislav Shwartsman
65275ffc02 Remove repeat speedups from 16-bit address size methods - they not gonna speed up anyway because of segment limit issue 2008-06-25 10:34:21 +00:00
Stanislav Shwartsman
a6fda9a971 Instrumentation code updated, some PANIC messages fixed 2008-06-23 02:56:31 +00:00
Stanislav Shwartsman
678ac970aa Reorganize ctrl_xfer8.cc code, allows to inline branch32 method 2008-06-22 03:45:55 +00:00
Stanislav Shwartsman
7f82a536b3 Fixed code duplication during prefix decoding 2008-06-11 20:58:29 +00:00
Stanislav Shwartsman
aff775bce4 Small code optimization 2008-06-09 19:35:59 +00:00
Stanislav Shwartsman
16d073bf51 Fixed recently introduced PUSH_Eq decoding bug 2008-05-08 21:34:22 +00:00
Stanislav Shwartsman
ed4be45a8b Split shift/rotate opcodes in 32-bit mode and 64-bit mode 2008-05-02 22:47:07 +00:00
Stanislav Shwartsman
81deffd65d More fetchdecode fixes 2008-04-30 21:32:33 +00:00
Stanislav Shwartsman
e5b6f90b62 some fetchdecode fixes 2008-04-30 21:07:12 +00:00
Stanislav Shwartsman
64f2489afb Correctly implement opcode group G11 i.e. instructions C6 and C7 should @UD when modrm nnn field != 0 (1st instr in the group 2008-04-24 21:52:28 +00:00
Stanislav Shwartsman
eea58f04cd Fixed ret_near decoding in 64-bit mode 2008-04-18 13:11:52 +00:00
Stanislav Shwartsman
c611d9aca0 Fixed LEAVE in 64-bit mode 2008-04-16 21:35:43 +00:00
Stanislav Shwartsman
892fa99c6f - prefetch hint should be NOP when use in register mode 
- #GP when trying to set reserved bits of CR4_HI in 64-bit mode
- #GP when trying to set reserved bits of EFER MSR
- clear upper part of RSI/RDI when executing rep instructions with 32-bit asize
  even if no repeat iterations were executed (because of RCX=0 for example)
- write SYSENTER_EIP_MSR and SYSENTER_ESP_MSR as 64-bit when x86_64 supported
- set MSR_FMASK reset value
- MSR_FMASK should be 32-bit only
- check for fetch permissions when doing ITLB lookup
- #GP when trying to write non-canonical address to MSR_CSTAR or MSR_LSTAR
- correct repeat instructions timing
- mark TSS busy in TR after it is loaded
 2008-04-16 16:44:06 +00:00
Stanislav Shwartsman
419dc57dbd Complete MASKMOVDQU decoding fix 2008-04-16 05:56:55 +00:00
Stanislav Shwartsman
4f3f8608f7 Fixed MASKMOVDQU instruction decoding 2008-04-16 05:41:43 +00:00
Stanislav Shwartsman
fab4042cad SYSENTER/SYSEXIT in long mode 2008-04-15 14:41:50 +00:00
Stanislav Shwartsman
1bdddc1f78 Split SHRD/SHLD instructions 2008-04-05 19:08:01 +00:00
Stanislav Shwartsman
5826e2843a Inline pop/push functions 
Store only single byte of opcode in b1() - speedup shift instructions
Code cleanups
 2008-04-05 17:51:55 +00:00
Stanislav Shwartsman
2aaafa76a2 Reorganize fetchdecode tables with another level of redirection - a leap toward future improvements 
Currently no speedup and no slowdown - about the same results on my Bochs benchmarking
A lot of code reorganization in fetchdecode
 2008-04-04 22:39:45 +00:00
Stanislav Shwartsman
62e3728591 preparations for future optimizations - not necessary speedupo now 2008-04-03 17:56:59 +00:00
Stanislav Shwartsman
3f2487a0af Enabled tracing cross repeated instructions 2008-03-31 18:53:08 +00:00
Stanislav Shwartsman
255d512e29 Organize bxInstruction fields differently 2008-03-31 17:33:34 +00:00
Stanislav Shwartsman
14ff07b482 Small code cleanup 2008-03-29 09:58:23 +00:00
Stanislav Shwartsman
e48b398bee Add NIL register and simplify more BxResolve work 2008-03-29 09:34:35 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
7e490699d4 Removing hooks for not-implemented SSE4A from the Bochs code. 2008-03-21 20:04:42 +00:00
Stanislav Shwartsman
946b7a369d Added const to fetchPtr in cpu functions 2008-03-03 15:16:46 +00:00
Stanislav Shwartsman
5e7218b8c3 Fixed problem introduced by prev checkin 
+
Fix beak to debugger when executing HLT instruction
 2008-02-29 05:39:40 +00:00
Stanislav Shwartsman
405fcfd75d Reorganize 3-byte opcode tables - bigger tables but easier to maintain them 2008-02-29 03:02:03 +00:00
Stanislav Shwartsman
cdcd7522aa Added RIP to the GPR register file as lst register 
This allowed to optimize (read - remove) two more BxResolve methods in 64-bit mode
+ Some white space cleanup
 2008-02-15 19:03:54 +00:00
Stanislav Shwartsman
0f44b4f0ec Fixes in MODRM tables 2008-02-15 12:23:49 +00:00
Stanislav Shwartsman
4fc0df26e8 a bit optimize and simplify x87 decoding 2008-02-14 18:59:41 +00:00
Stanislav Shwartsman
fb0ce45d28 Unpack more fields in bxInstruction_c -> this increase bxInstruction size by 4 bytes but I have no way but do it if want to support SSE5 dest override later 2008-02-04 21:28:53 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
37fbb82baa Cleanups. Move bxInstruction_c definition to separate file instr.h 2008-01-29 17:13:10 +00:00
Stanislav Shwartsman
7b80c5f481 I merged and succeded to remove some similar execution functions - less code, less chance for branch misprediction 2008-01-25 19:34:30 +00:00
Stanislav Shwartsman
63d8d50cfc code cleanup 2008-01-20 20:11:17 +00:00
Stanislav Shwartsman
8c9de8b4db speculative tracing on fetchdecode level 2008-01-18 09:36:15 +00:00
Stanislav Shwartsman
d9984bb3a1 Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup ! 2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
eee1a9030d a bit simplify and optimize shift instructions 
print failed segment info in check_cs - more debug info
 2007-12-30 20:16:35 +00:00
Stanislav Shwartsman
c3c9c40674 Move MaxFetch calculation into fetchdecode - simplify the logic 2007-12-22 17:17:40 +00:00
Stanislav Shwartsman
e9a148f9c4 lmost last instruction split -> CMOV in 16/32 bit modes 2007-12-21 18:24:19 +00:00
Stanislav Shwartsman
c9932e97eb Fixes in resolve.cc -> reduce amount of resolve functions even more 2007-12-18 21:41:44 +00:00
Stanislav Shwartsman
fe2e0525da More optimization for string instructions 2007-12-17 19:52:01 +00:00
Stanislav Shwartsman
de5838ce80 cleanups and fixes for Immediate_IbIb of SSE4A 2007-12-16 20:47:10 +00:00
Stanislav Shwartsman
1e843cb462 Decode SSE4A 
Rework immediate bytes decoding to make it faster
 2007-12-15 17:42:24 +00:00
Stanislav Shwartsman
fd73390ca5 Split 64-bit CMOVcc opcode 2007-12-14 22:41:43 +00:00
Stanislav Shwartsman
903f6dea35 Split setCC functions - makes code faster and simpler 2007-12-14 21:29:36 +00:00
Stanislav Shwartsman
05c7a1e61b Fixed problem with trace cache enabled 
String instructions might confise trace cache by finishing instruction execution method without actually completing an instruction (and advancing eip)
 2007-12-13 18:42:31 +00:00