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implemented AVX instructions support

Browse Source 
many changes - some cleanup will follow
please report ay found bugs !
This commit is contained in:
Stanislav Shwartsman 2011-03-19 20:09:34 +00:00
parent 16021a0ddb
commit 7ced718040
52 changed files with 8047 additions and 1100 deletions
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4
bochs/CHANGES
View File

@ -2,6 +2,10 @@ Changes after 2.4.6 release:
Bochs repository moved to the SVN version control !
- CPU
- Added support of AVX instruction set emulation, to enable configure with
--enable-avx option
- Configure and compile
- Added ability to configure CPUID family through .bochsrc.
The default family value determined by configure option --enable-cpu-level.

98
bochs/bx_debug/dbg_main.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
// Copyright (C) 2001-2011 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -600,6 +600,14 @@ void bx_dbg_lin_memory_access(unsigned cpu, bx_address lin, bx_phy_address phy,
dbg_printf(": 0x%08X 0x%08X 0x%08X 0x%08X",
xmmdata->xmm32u(3), xmmdata->xmm32u(2), xmmdata->xmm32u(1), xmmdata->xmm32u(0));
}
#if BX_SUPPORT_AVX
else if (len == 32) {
const BxPackedAvxRegister *xmmdata = (const BxPackedAvxRegister*)(data);
dbg_printf(": 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X",
xmmdata->avx32u(7), xmmdata->avx32u(6), xmmdata->avx32u(5), xmmdata->avx32u(4),
xmmdata->avx32u(3), xmmdata->avx32u(2), xmmdata->avx32u(1), xmmdata->avx32u(0));
}
#endif
#endif
else {
for (int i=len-1;i >= 0;i--) {
@ -672,6 +680,14 @@ void bx_dbg_phy_memory_access(unsigned cpu, bx_phy_address phy, unsigned len, un
dbg_printf(": 0x%08X 0x%08X 0x%08X 0x%08X",
xmmdata->xmm32u(3), xmmdata->xmm32u(2), xmmdata->xmm32u(1), xmmdata->xmm32u(0));
}
#if BX_SUPPORT_AVX
else if (len == 32) {
const BxPackedAvxRegister *xmmdata = (const BxPackedAvxRegister*)(data);
dbg_printf(": 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X",
xmmdata->avx32u(7), xmmdata->avx32u(6), xmmdata->avx32u(5), xmmdata->avx32u(4),
xmmdata->avx32u(3), xmmdata->avx32u(2), xmmdata->avx32u(1), xmmdata->avx32u(0));
}
#endif
#endif
else {
for (int i=len-1;i >= 0;i--) {
@ -700,30 +716,37 @@ void bx_dbg_exit(int code)
// functions for browsing of cpu state
//
void bx_dbg_print_mxcsr_state(void)
{
#if BX_CPU_LEVEL >= 6
Bit32u mxcsr = SIM->get_param_num("SSE.mxcsr", dbg_cpu_list)->get();
dbg_printf("MXCSR: 0x%05x: %s %s RC:%d %s %s %s %s %s %s %s %s %s %s %s %s %s\n", mxcsr,
(mxcsr & (1<<17)) ? "ULE" : "ule",
(mxcsr & (1<<15)) ? "FUZ" : "fuz",
(mxcsr >> 13) & 3,
(mxcsr & (1<<12)) ? "PM" : "pm",
(mxcsr & (1<<11)) ? "UM" : "um",
(mxcsr & (1<<10)) ? "OM" : "om",
(mxcsr & (1<<9)) ? "ZM" : "zm",
(mxcsr & (1<<8)) ? "DM" : "dm",
(mxcsr & (1<<7)) ? "IM" : "im",
(mxcsr & (1<<6)) ? "DAZ" : "daz",
(mxcsr & (1<<5)) ? "PE" : "pe",
(mxcsr & (1<<4)) ? "UE" : "ue",
(mxcsr & (1<<3)) ? "OE" : "oe",
(mxcsr & (1<<2)) ? "ZE" : "ze",
(mxcsr & (1<<1)) ? "DE" : "de",
(mxcsr & (1<<0)) ? "IE" : "ie");
#endif
}
void bx_dbg_print_sse_state(void)
{
#if BX_CPU_LEVEL >= 6
Bit32u isa_extensions_bitmask = SIM->get_param_num("isa_extensions_bitmask", dbg_cpu_list)->get();
if ((isa_extensions_bitmask & BX_CPU_SSE) != 0) {
Bit32u mxcsr = SIM->get_param_num("SSE.mxcsr", dbg_cpu_list)->get();
dbg_printf("MXCSR: 0x%05x: %s %s RC:%d %s %s %s %s %s %s %s %s %s %s %s %s %s\n", mxcsr,
(mxcsr & (1<<17)) ? "ULE" : "ule",
(mxcsr & (1<<15)) ? "FUZ" : "fuz",
(mxcsr >> 13) & 3,
(mxcsr & (1<<12)) ? "PM" : "pm",
(mxcsr & (1<<11)) ? "UM" : "um",
(mxcsr & (1<<10)) ? "OM" : "om",
(mxcsr & (1<<9)) ? "ZM" : "zm",
(mxcsr & (1<<8)) ? "DM" : "dm",
(mxcsr & (1<<7)) ? "IM" : "im",
(mxcsr & (1<<6)) ? "DAZ" : "daz",
(mxcsr & (1<<5)) ? "PE" : "pe",
(mxcsr & (1<<4)) ? "UE" : "ue",
(mxcsr & (1<<3)) ? "OE" : "oe",
(mxcsr & (1<<2)) ? "ZE" : "ze",
(mxcsr & (1<<1)) ? "DE" : "de",
(mxcsr & (1<<0)) ? "IE" : "ie");
bx_dbg_print_mxcsr_state();
char param_name[20];
for(unsigned i=0;i<BX_XMM_REGISTERS;i++) {
@ -742,6 +765,36 @@ void bx_dbg_print_sse_state(void)
}
}
void bx_dbg_print_avx_state(unsigned vlen)
{
#if BX_SUPPORT_AVX
Bit32u isa_extensions_bitmask = SIM->get_param_num("isa_extensions_bitmask", dbg_cpu_list)->get();
if ((isa_extensions_bitmask & BX_CPU_AVX) != 0) {
bx_dbg_print_mxcsr_state();
char param_name[20];
for(unsigned i=0;i<BX_XMM_REGISTERS;i++) {
dbg_printf("VMM[%02u]: ", i);
for (int j=vlen;j >= 0; j--) {
sprintf(param_name, "SSE.xmm%02d_%d", i, j*2+1);
Bit64u hi = SIM->get_param_num(param_name, dbg_cpu_list)->get64();
sprintf(param_name, "SSE.xmm%02d_%d", i, j*2);
Bit64u lo = SIM->get_param_num(param_name, dbg_cpu_list)->get64();
if (j!=(int)vlen) dbg_printf("_");
dbg_printf("%08x_%08x_%08x_%08x", GET32H(hi), GET32L(hi), GET32H(lo), GET32L(lo));
}
dbg_printf("\n");
}
}
else
#endif
{
dbg_printf("The CPU doesn't support AVX state !\n");
}
}
void bx_dbg_print_mmx_state(void)
{
#if BX_CPU_LEVEL >= 5
@ -985,7 +1038,7 @@ void bx_dbg_info_registers_command(int which_regs_mask)
reg = BX_CPU(dbg_cpu)->get_reg64(BX_64BIT_REG_R14);
dbg_printf("r14: 0x%08x_%08x ", GET32H(reg), GET32L(reg));
reg = BX_CPU(dbg_cpu)->get_reg64(BX_64BIT_REG_R15);
dbg_printf("r15: 0x%08x+%08x\n", GET32H(reg), GET32L(reg));
dbg_printf("r15: 0x%08x_%08x\n", GET32H(reg), GET32L(reg));
reg = bx_dbg_get_instruction_pointer();
dbg_printf("rip: 0x%08x_%08x\n", GET32H(reg), GET32L(reg));
#endif
@ -1004,7 +1057,10 @@ void bx_dbg_info_registers_command(int which_regs_mask)
bx_dbg_print_mmx_state();
}
if (which_regs_mask & BX_INFO_SSE_REGS) {
if (which_regs_mask & BX_INFO_AVX_REGS) {
bx_dbg_print_avx_state(BX_VLMAX-1);
}
else if (which_regs_mask & BX_INFO_SSE_REGS) {
bx_dbg_print_sse_state();
}
}

3
bochs/bx_debug/debug.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
// Copyright (C) 2001-2011 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -262,6 +262,7 @@ void bx_dbg_quit_command(void);
#define BX_INFO_FPU_REGS 0x02
#define BX_INFO_MMX_REGS 0x04
#define BX_INFO_SSE_REGS 0x08
#define BX_INFO_AVX_REGS 0x10
void bx_dbg_info_registers_command(int);
void bx_dbg_info_ivt_command(unsigned from, unsigned to);
void bx_dbg_info_idt_command(unsigned from, unsigned to);

4
bochs/bx_debug/lexer.l
View File

@ -78,8 +78,8 @@ r { bxlval.sval = strdup(bxtext); return(BX_TOKEN_R); }
reg|regs |
registers { bxlval.sval = strdup(bxtext); return(BX_TOKEN_REGS); }
fp|fpu { bxlval.sval = strdup(bxtext); return(BX_TOKEN_FPU); }
sse |
xmm { bxlval.sval = strdup(bxtext); return(BX_TOKEN_SSE); }
sse|xmm { bxlval.sval = strdup(bxtext); return(BX_TOKEN_SSE); }
ymm { bxlval.sval = strdup(bxtext); return(BX_TOKEN_AVX); }
mmx { bxlval.sval = strdup(bxtext); return(BX_TOKEN_MMX); }
cpu { bxlval.sval = strdup(bxtext); return(BX_TOKEN_CPU); }
idt { bxlval.sval = strdup(bxtext); return(BX_TOKEN_IDT); }

21
bochs/bx_debug/parser.y
View File

@ -55,8 +55,9 @@
%token <sval> BX_TOKEN_REGS
%token <sval> BX_TOKEN_CPU
%token <sval> BX_TOKEN_FPU
%token <sval> BX_TOKEN_SSE
%token <sval> BX_TOKEN_MMX
%token <sval> BX_TOKEN_SSE
%token <sval> BX_TOKEN_AVX
%token <sval> BX_TOKEN_IDT
%token <sval> BX_TOKEN_IVT
%token <sval> BX_TOKEN_GDT
@ -151,6 +152,7 @@ command:
| fpu_regs_command
| mmx_regs_command
| sse_regs_command
| avx_regs_command
| segment_regs_command
| debug_regs_command
| control_regs_command
@ -567,7 +569,7 @@ info_command:
}
| BX_TOKEN_INFO BX_TOKEN_CPU '\n'
{
bx_dbg_info_registers_command(BX_INFO_GENERAL_PURPOSE_REGS | BX_INFO_FPU_REGS | BX_INFO_SSE_REGS);
bx_dbg_info_registers_command(-1);
free($1); free($2);
}
| BX_TOKEN_INFO BX_TOKEN_IDT optional_numeric optional_numeric '\n'
@ -688,6 +690,14 @@ sse_regs_command:
}
;
avx_regs_command:
BX_TOKEN_AVX '\n'
{
bx_dbg_info_registers_command(BX_INFO_AVX_REGS);
free($1);
}
;
segment_regs_command:
BX_TOKEN_SEGMENT_REGS '\n'
{
@ -1036,7 +1046,12 @@ help_command:
}
| BX_TOKEN_HELP BX_TOKEN_SSE '\n'
{
dbg_printf("sse|xmm - print SSE state\n");
dbg_printf("xmm|sse - print SSE state\n");
free($1);free($2);
}
| BX_TOKEN_HELP BX_TOKEN_AVX '\n'
{
dbg_printf("ymm - print AVX state\n");
free($1);free($2);
}
| BX_TOKEN_HELP BX_TOKEN_SEGMENT_REGS '\n'

1
bochs/config.h.in
View File

@ -659,6 +659,7 @@ typedef
#define BX_SUPPORT_MISALIGNED_SSE 0
#define BX_SUPPORT_MONITOR_MWAIT 0
#define BX_SUPPORT_VMX 0
#define BX_SUPPORT_AVX 0
#if BX_SUPPORT_VMX >= 2 && BX_SUPPORT_X86_64 == 0
#error "VMXx2 require x86-64 support"

1201
bochs/configure vendored
View File

File diff suppressed because it is too large Load Diff

21
bochs/configure.in
View File

@ -1415,6 +1415,10 @@ AC_ARG_ENABLE(vmx,
]
)
if test "$support_avx" -gt 0 -a "$bx_cpu_level" -lt 6; then
AC_MSG_ERROR([for AVX support the CPU level must be set to 6])
fi
if test "$support_vmx" -gt 0 -a "$bx_cpu_level" -lt 6; then
AC_MSG_ERROR([for VMX support the CPU level must be set to 6])
fi
@ -1496,6 +1500,23 @@ AC_ARG_ENABLE(monitor_mwait,
]
)
AC_MSG_CHECKING(for AVX instructions support)
AC_ARG_ENABLE(avx,
[ --enable-avx support for AVX instructions],
[if test "$enableval" = yes; then
AC_MSG_RESULT(yes)
AC_DEFINE(BX_SUPPORT_AVX, 1)
elif test "$enableval" = no; then
AC_MSG_RESULT(no)
AC_DEFINE(BX_SUPPORT_AVX, 0)
fi
],
[
AC_MSG_RESULT(no)
AC_DEFINE(BX_SUPPORT_AVX, 0)
]
)
AC_MSG_CHECKING(for x86 debugger support)
AC_ARG_ENABLE(x86-debugger,
[ --enable-x86-debugger x86 debugger support],

24
bochs/cpu/Makefile.in
View File

@ -61,6 +61,8 @@ OBJS = \
sse_pfp.o \
sse_rcp.o \
sse_string.o \
avx.o \
avx_pfp.o \
xsave.o \
aes.o \
vmx.o \
@ -393,7 +395,7 @@ fetchdecode.o: fetchdecode.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h \
../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h fetchdecode.h \
fetchdecode_x87.h fetchdecode_sse.h
fetchdecode_x87.h fetchdecode_sse.h fetchdecode_avx.h
fetchdecode64.o: fetchdecode64.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../bxversion.h \
../gui/siminterface.h ../gui/paramtree.h ../memory/memory.h \
@ -402,7 +404,7 @@ fetchdecode64.o: fetchdecode64.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h \
../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h fetchdecode.h \
fetchdecode_x87.h fetchdecode_sse.h
fetchdecode_x87.h fetchdecode_sse.h fetchdecode_avx.h
flag_ctrl.o: flag_ctrl.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../bxversion.h \
../gui/siminterface.h ../gui/paramtree.h ../memory/memory.h \
@ -696,6 +698,24 @@ sse_string.o: sse_string.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h \
../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h
avx.o: avx.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../bxversion.h \
../gui/siminterface.h ../gui/paramtree.h ../memory/memory.h \
../pc_system.h ../plugin.h ../extplugin.h ../gui/gui.h \
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h \
../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h ../fpu/softfloat-compare.h \
../fpu/softfloat.h ../fpu/softfloat-specialize.h
avx_pfp.o: avx_pfp.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../bxversion.h \
../gui/siminterface.h ../gui/paramtree.h ../memory/memory.h \
../pc_system.h ../plugin.h ../extplugin.h ../gui/gui.h \
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h \
descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h apic.h \
../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h ../fpu/softfloat-compare.h \
../fpu/softfloat.h ../fpu/softfloat-specialize.h
stack16.o: stack16.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
../bx_debug/debug.h ../config.h ../osdep.h ../bxversion.h \
../gui/siminterface.h ../gui/paramtree.h ../memory/memory.h \

6
bochs/cpu/access.cc
View File

@ -66,7 +66,7 @@ BX_CPU_C::write_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned le
BX_ERROR(("write_virtual_checks(): write beyond limit, r/w"));
return 0;
}
if (seg->cache.u.segment.limit_scaled >= 15) {
if (seg->cache.u.segment.limit_scaled >= 31) {
// Mark cache as being OK type for succeeding read/writes. The limit
// checks still needs to be done though, but is more simple. We
// could probably also optimize that out with a flag for the case
@ -124,7 +124,7 @@ BX_CPU_C::read_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned len
BX_ERROR(("read_virtual_checks(): read beyond limit"));
return 0;
}
if (seg->cache.u.segment.limit_scaled >= 15) {
if (seg->cache.u.segment.limit_scaled >= 31) {
// Mark cache as being OK type for succeeding reads. See notes for
// write checks; similar code.
seg->cache.valid |= SegAccessROK;
@ -184,7 +184,7 @@ BX_CPU_C::execute_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned
BX_ERROR(("execute_virtual_checks(): read beyond limit"));
return 0;
}
if (seg->cache.u.segment.limit_scaled >= 15) {
if (seg->cache.u.segment.limit_scaled >= 31) {
// Mark cache as being OK type for succeeding reads. See notes for
// write checks; similar code.
seg->cache.valid |= SegAccessROK;

221
bochs/cpu/access32.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2010 Stanislav Shwartsman
// Copyright (c) 2008-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -349,6 +349,117 @@ accessOK:
goto accessOK;
}
#if BX_SUPPORT_AVX
void BX_CPU_C::write_virtual_vector_32(unsigned s, Bit32u offset, unsigned elements, const BxPackedAvxRegister *data)
{
BX_ASSERT(elements > 0);
Bit32u laddr;
unsigned len = elements << 2;
bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, len, BX_WRITE);
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
if (seg->cache.valid & SegAccessWOK) {
if (offset < (seg->cache.u.segment.limit_scaled-len)) {
accessOK:
laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, len-1);
Bit32u lpf = LPFOf(laddr);
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (! (tlbEntry->accessBits & (0x2 | USER_PL))) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
bx_phy_address pAddr = tlbEntry->ppf | pageOffset;
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, pAddr, len, BX_WRITE);
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, pAddr, len, CPL, BX_WRITE, (Bit8u*) data);
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
pageWriteStampTable.decWriteStamp(pAddr, len);
for (unsigned n=0; n < elements; n++) {
WriteHostDWordToLittleEndian(hostAddr, data->avx32u(n));
hostAddr++;
}
return;
}
}
access_write_linear(laddr, len, CPL, (void *) data);
return;
}
else {
BX_ERROR(("write_virtual_vector_32(): segment limit violation"));
exception(int_number(s), 0);
}
}
if (!write_virtual_checks(seg, offset, len))
exception(int_number(s), 0);
goto accessOK;
}
void BX_CPU_C::write_virtual_vector_aligned_32(unsigned s, Bit32u offset, unsigned elements, const BxPackedAvxRegister *data)
{
BX_ASSERT(elements > 0);
unsigned len = elements << 2;
bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, len, BX_WRITE);
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
Bit32u laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
// must check alignment here because #GP on misaligned access is higher
// priority than other segment related faults
if (laddr & (len-1)) {
BX_ERROR(("write_virtual_vector_aligned_32(): #GP misaligned access"));
exception(BX_GP_EXCEPTION, 0);
}
if (seg->cache.valid & SegAccessWOK) {
if (offset < (seg->cache.u.segment.limit_scaled-len)) {
accessOK:
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
Bit32u lpf = LPFOf(laddr);
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (! (tlbEntry->accessBits & (0x2 | USER_PL))) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
bx_phy_address pAddr = tlbEntry->ppf | pageOffset;
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, pAddr, len, BX_WRITE);
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, pAddr, len, CPL, BX_WRITE, (Bit8u*) data);
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
pageWriteStampTable.decWriteStamp(pAddr, len);
for (unsigned n=0; n < elements; n++) {
WriteHostDWordToLittleEndian(hostAddr, data->avx32u(n));
hostAddr++;
}
return;
}
}
access_write_linear(laddr, len, CPL, (void *) data);
return;
}
else {
BX_ERROR(("write_virtual_vector_aligned_32(): segment limit violation"));
exception(int_number(s), 0);
}
}
if (!write_virtual_checks(seg, offset, len))
exception(int_number(s), 0);
goto accessOK;
}
#endif // BX_SUPPORT_AVX
#endif
Bit8u BX_CPP_AttrRegparmN(2)
@ -671,6 +782,114 @@ accessOK:
goto accessOK;
}
#if BX_SUPPORT_AVX
void BX_CPU_C::read_virtual_vector_32(unsigned s, Bit32u offset, unsigned elements, BxPackedAvxRegister *data)
{
BX_ASSERT(elements > 0);
Bit32u laddr;
unsigned len = elements << 2;
bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, len, BX_READ);
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
if (seg->cache.valid & SegAccessROK) {
if (offset < (seg->cache.u.segment.limit_scaled-len)) {
accessOK:
laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, len-1);
Bit32u lpf = LPFOf(laddr);
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (! (tlbEntry->accessBits & USER_PL)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
for (unsigned n=0; n < elements; n++) {
ReadHostDWordFromLittleEndian(hostAddr, data->avx32u(n));
hostAddr++;
}
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, len, BX_READ);
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
tlbEntry->ppf | pageOffset, len, CPL, BX_READ, (Bit8u*) data);
return;
}
}
access_read_linear(laddr, len, CPL, BX_READ, (void *) data);
return;
}
else {
BX_ERROR(("read_virtual_vector_32(): segment limit violation"));
exception(int_number(s), 0);
}
}
if (!read_virtual_checks(seg, offset, len))
exception(int_number(s), 0);
goto accessOK;
}
void BX_CPU_C::read_virtual_vector_aligned_32(unsigned s, Bit32u offset, unsigned elements, BxPackedAvxRegister *data)
{
BX_ASSERT(elements > 0);
unsigned len = elements << 2;
bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, len, BX_READ);
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
Bit32u laddr = BX_CPU_THIS_PTR get_laddr32(s, offset);
// must check alignment here because #GP on misaligned access is higher
// priority than other segment related faults
if (laddr & (len-1)) {
BX_ERROR(("read_virtual_vector_aligned_32(): #GP misaligned access"));
exception(BX_GP_EXCEPTION, 0);
}
if (seg->cache.valid & SegAccessROK) {
if (offset < (seg->cache.u.segment.limit_scaled-len)) {
accessOK:
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
Bit32u lpf = LPFOf(laddr);
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (! (tlbEntry->accessBits & USER_PL)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
for (unsigned n=0; n < elements; n++) {
ReadHostDWordFromLittleEndian(hostAddr, data->avx32u(n));
hostAddr++;
}
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, len, BX_READ);
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
tlbEntry->ppf | pageOffset, len, CPL, BX_READ, (Bit8u*) data);
return;
}
}
access_read_linear(laddr, len, CPL, BX_READ, (void *) data);
return;
}
else {
BX_ERROR(("read_virtual_vector_aligned_32(): segment limit violation"));
exception(int_number(s), 0);
}
}
if (!read_virtual_checks(seg, offset, len))
exception(int_number(s), 0);
goto accessOK;
}
#endif
#endif
//////////////////////////////////////////////////////////////

176
bochs/cpu/access64.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2010 Stanislav Shwartsman
// Copyright (c) 2008-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -299,6 +299,95 @@ BX_CPU_C::write_virtual_dqword_aligned_64(unsigned s, Bit64u offset, const BxPac
access_write_linear(laddr, 16, CPL, (void *) data);
}
#if BX_SUPPORT_AVX
void BX_CPU_C::write_virtual_vector_64(unsigned s, Bit64u offset, unsigned elements, const BxPackedAvxRegister *data)
{
BX_ASSERT(elements > 0);
unsigned len = elements << 2;
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64);
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, len, BX_WRITE);
Bit64u laddr = BX_CPU_THIS_PTR get_laddr64(s, offset);
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, len-1);
Bit64u lpf = LPFOf(laddr);
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (! (tlbEntry->accessBits & (0x2 | USER_PL))) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
bx_phy_address pAddr = tlbEntry->ppf | pageOffset;
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, pAddr, len, BX_WRITE);
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, pAddr, len, CPL, BX_WRITE, (Bit8u*) data);
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
pageWriteStampTable.decWriteStamp(pAddr, len);
for (unsigned n = 0; n < elements; n++) {
WriteHostDWordToLittleEndian(hostAddr, data->avx32u(n));
hostAddr++;
}
return;
}
}
if (! IsCanonical(laddr) || ! IsCanonical(laddr+len-1)) {
BX_ERROR(("write_virtual_vector_64(): canonical failure"));
exception(int_number(s), 0);
}
access_write_linear(laddr, len, CPL, (void *) data);
}
void BX_CPU_C::write_virtual_vector_aligned_64(unsigned s, Bit64u offset, unsigned elements, const BxPackedAvxRegister *data)
{
BX_ASSERT(elements > 0);
unsigned len = elements << 2;
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64);
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, len, BX_WRITE);
Bit64u laddr = BX_CPU_THIS_PTR get_laddr64(s, offset);
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
Bit64u lpf = AlignedAccessLPFOf(laddr, len-1);
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us write access
// from this CPL.
if (! (tlbEntry->accessBits & (0x2 | USER_PL))) {
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
bx_phy_address pAddr = tlbEntry->ppf | pageOffset;
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, pAddr, len, BX_WRITE);
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, pAddr, len, CPL, BX_WRITE, (Bit8u*) data);
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
pageWriteStampTable.decWriteStamp(pAddr, len);
for (unsigned n = 0; n < elements; n++) {
WriteHostDWordToLittleEndian(hostAddr, data->avx32u(n));
hostAddr++;
}
return;
}
}
if (laddr & (len-1)) {
BX_ERROR(("write_virtual_vector_aligned_64(): #GP misaligned access"));
exception(BX_GP_EXCEPTION, 0);
}
if (! IsCanonical(laddr) || ! IsCanonical(laddr+len-1)) {
BX_ERROR(("write_virtual_vector_aligned_64(): canonical failure"));
exception(int_number(s), 0);
}
access_write_linear(laddr, len, CPL, (void *) data);
}
#endif
Bit8u BX_CPP_AttrRegparmN(2)
BX_CPU_C::read_virtual_byte_64(unsigned s, Bit64u offset)
{
@ -566,6 +655,91 @@ BX_CPU_C::read_virtual_dqword_aligned_64(unsigned s, Bit64u offset, BxPackedXmmR
access_read_linear(laddr, 16, CPL, BX_READ, (void *) data);
}
#if BX_SUPPORT_AVX
void BX_CPU_C::read_virtual_vector_64(unsigned s, Bit64u offset, unsigned elements, BxPackedAvxRegister *data)
{
BX_ASSERT(elements > 0);
unsigned len = elements << 2;
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64);
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, len, BX_READ);
Bit64u laddr = BX_CPU_THIS_PTR get_laddr64(s, offset);
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, len-1);
Bit64u lpf = LPFOf(laddr);
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (! (tlbEntry->accessBits & USER_PL)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
for (unsigned n=0; n < elements; n++) {
ReadHostDWordFromLittleEndian(hostAddr, data->avx32u(n));
hostAddr++;
}
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, len, BX_READ);
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
tlbEntry->ppf | pageOffset, len, CPL, BX_READ, (Bit8u*) data);
return;
}
}
if (! IsCanonical(laddr) || ! IsCanonical(laddr+len-1)) {
BX_ERROR(("read_virtual_vector_64(): canonical failure"));
exception(int_number(s), 0);
}
access_read_linear(laddr, len, CPL, BX_READ, (void *) data);
}
void BX_CPU_C::read_virtual_vector_aligned_64(unsigned s, Bit64u offset, unsigned elements, BxPackedAvxRegister *data)
{
BX_ASSERT(elements > 0);
unsigned len = elements << 2;
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64);
BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, len, BX_READ);
Bit64u laddr = BX_CPU_THIS_PTR get_laddr64(s, offset);
unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
Bit64u lpf = AlignedAccessLPFOf(laddr, len-1);
bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex];
if (tlbEntry->lpf == lpf) {
// See if the TLB entry privilege level allows us read access
// from this CPL.
if (! (tlbEntry->accessBits & USER_PL)) { // Read this pl OK.
bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr;
Bit32u pageOffset = PAGE_OFFSET(laddr);
Bit32u *hostAddr = (Bit32u*) (hostPageAddr | pageOffset);
for (unsigned n=0; n < elements; n++) {
ReadHostDWordFromLittleEndian(hostAddr, data->avx32u(n));
hostAddr++;
}
BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, len, BX_READ);
BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
tlbEntry->ppf | pageOffset, len, CPL, BX_READ, (Bit8u*) data);
return;
}
}
if (laddr & (len-1)) {
BX_ERROR(("read_virtual_vector_aligned_64(): #GP misaligned access"));
exception(BX_GP_EXCEPTION, 0);
}
if (! IsCanonical(laddr) || ! IsCanonical(laddr+len-1)) {
BX_ERROR(("read_virtual_vector_aligned_64(): canonical failure"));
exception(int_number(s), 0);
}
access_read_linear(laddr, len, CPL, BX_READ, (void *) data);
}
#endif
//////////////////////////////////////////////////////////////
// special Read-Modify-Write operations //
// address translation info is kept across read/write calls //

26
bochs/cpu/aes.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2010 Stanislav Shwartsman
// Copyright (c) 2008-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -297,7 +297,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESIMC_VdqWdqR(bxInstruction_c *i)
AES_InverseMixColumns(op);
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
#endif
}
@ -305,7 +305,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESIMC_VdqWdqR(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENC_VdqWdqR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
AES_ShiftRows(op1);
AES_SubstituteBytes(op1);
@ -314,7 +314,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENC_VdqWdqR(bxInstruction_c *i)
op1.xmm64u(0) ^= op2.xmm64u(0);
op1.xmm64u(1) ^= op2.xmm64u(1);
BX_WRITE_XMM_REG(i->nnn(), op1);
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
#endif
}
@ -322,7 +322,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENC_VdqWdqR(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENCLAST_VdqWdqR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
AES_ShiftRows(op1);
AES_SubstituteBytes(op1);
@ -330,7 +330,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENCLAST_VdqWdqR(bxInstruction_c *i)
op1.xmm64u(0) ^= op2.xmm64u(0);
op1.xmm64u(1) ^= op2.xmm64u(1);
BX_WRITE_XMM_REG(i->nnn(), op1);
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
#endif
}
@ -338,7 +338,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENCLAST_VdqWdqR(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDEC_VdqWdqR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
AES_InverseShiftRows(op1);
AES_InverseSubstituteBytes(op1);
@ -347,7 +347,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDEC_VdqWdqR(bxInstruction_c *i)
op1.xmm64u(0) ^= op2.xmm64u(0);
op1.xmm64u(1) ^= op2.xmm64u(1);
BX_WRITE_XMM_REG(i->nnn(), op1);
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
#endif
}
@ -355,7 +355,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDEC_VdqWdqR(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDECLAST_VdqWdqR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
AES_InverseShiftRows(op1);
AES_InverseSubstituteBytes(op1);
@ -363,7 +363,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDECLAST_VdqWdqR(bxInstruction_c *i)
op1.xmm64u(0) ^= op2.xmm64u(0);
op1.xmm64u(1) ^= op2.xmm64u(1);
BX_WRITE_XMM_REG(i->nnn(), op1);
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
#endif
}
@ -380,7 +380,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR(bxInstruction_c
result.xmm32u(2) = AES_SubWord(op.xmm32u(3));
result.xmm32u(3) = AES_RotWord(result.xmm32u(2)) ^ rcon32;
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -388,7 +388,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR(bxInstruction_c
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCLMULQDQ_VdqWdqIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv()), op2 = BX_READ_XMM_REG(i->rm());
BxPackedXmmRegister r, a;
Bit8u imm8 = i->Ib();
@ -417,6 +417,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCLMULQDQ_VdqWdqIbR(bxInstruction_c *i)
b >>= 1;
}
BX_WRITE_XMM_REG(i->nnn(), r);
BX_WRITE_XMM_REGZ(i->nnn(), r, i->getVL());
#endif
}

880
bochs/cpu/avx.cc Normal file
View File

@ -0,0 +1,880 @@
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
//
/////////////////////////////////////////////////////////////////////////
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_AVX
/* VZEROUPPER: VEX.128.0F.77 (VEX.W ignore, VEX.VVV #UD) */
/* VZEROALL: VEX.256.0F.77 (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VZEROUPPER(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
if (i->getVL() == BX_VL128) {
for(unsigned index=0; index < BX_XMM_REGISTERS; index++)
{
if (index < 8 || long64_mode())
BX_CLEAR_AVX_HIGH(index);
}
}
else {
// prepare empty AVX register - zeroed by compiler because of static variable
static BxPackedAvxRegister nil;
for(unsigned index=0; index < BX_XMM_REGISTERS; index++)
{
if (index < 8 || long64_mode())
BX_WRITE_AVX_REG(index, nil);
}
}
#endif
}
/* VMOVSS: VEX.F3.0F 10 (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSS_VssWssR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op = BX_READ_XMM_REG(i->vvv());
op.xmm32u(0) = BX_READ_XMM_REG_LO_DWORD(i->rm());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
#endif
}
/* VMOVSS: VEX.F2.0F 10 (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSD_VsdWsdR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op;
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->rm());
op.xmm64u(1) = BX_READ_XMM_REG_HI_QWORD(i->vvv());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
#endif
}
/* VMOVAPS: VEX 0F 28 (VEX.W ignore, VEX.VVV #UD) */
/* VMOVAPD: VEX.66.0F 28 (VEX.W ignore, VEX.VVV #UD) */
/* VMOVDQA: VEX.66.0F 6F (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BX_WRITE_AVX_REGZ(i->nnn(), BX_READ_AVX_REG(i->rm()), i->getVL());
#endif
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_VpsWpsM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op;
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
/* pointer, segment address pair */
read_virtual_vector_aligned(i->seg(), eaddr, len << 2, &op);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
#endif
}
/* VMOVUPS: VEX 0F 10 (VEX.W ignore, VEX.VVV #UD) */
/* VMOVUPD: VEX.66.0F 10 (VEX.W ignore, VEX.VVV #UD) */
/* VMOVDQU: VEX.F3.0F 6F (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPS_VpsWpsM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op;
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
/* pointer, segment address pair */
read_virtual_vector(i->seg(), eaddr, len << 2, &op);
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
#endif
}
/* VMOVUPS: VEX 0F 11 (VEX.W ignore, VEX.VVV #UD) */
/* VMOVUPD: VEX.66.0F 11 (VEX.W ignore, VEX.VVV #UD) */
/* VMOVUQA: VEX.66.0F 7F (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVUPS_WpsVpsM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op = BX_READ_AVX_REG(i->nnn());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
/* pointer, segment address pair */
write_virtual_vector(i->seg(), eaddr, i->getVL() << 2, &op);
#endif
}
/* VMOVAPS: VEX 0F 29 (VEX.W ignore, VEX.VVV #UD) */
/* VMOVAPD: VEX.66.0F 29 (VEX.W ignore, VEX.VVV #UD) */
/* VMOVDQA: VEX.66.0F 7F (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVAPS_WpsVpsM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op = BX_READ_AVX_REG(i->nnn());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
/* pointer, segment address pair */
write_virtual_vector_aligned(i->seg(), eaddr, i->getVL() << 2, &op);
#endif
}
/* VEX.F2.0F 12 (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVDDUP_VpdWpdR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n+=2) {
op.avx64u(n+1) = op.avx64u(n);
}
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
#endif
}
/* VEX.F3.0F 12 (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSLDUP_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (4*len); n+=2) {
op.avx32u(n+1) = op.avx32u(n);
}
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
#endif
}
/* VEX.F3.0F 12 (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVSHDUP_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (4*len); n+=2) {
op.avx32u(n) = op.avx32u(n+1);
}
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
#endif
}
/* VEX.0F 12 (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHLPS_VpsWps(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op;
op.xmm64u(0) = BX_READ_XMM_REG_HI_QWORD(i->rm());
op.xmm64u(1) = BX_READ_XMM_REG_HI_QWORD(i->vvv());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
#endif
}
/* VEX.66.0F 12 (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLPD_VpdMq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
BxPackedXmmRegister op;
op.xmm64u(0) = read_virtual_qword(i->seg(), eaddr);
op.xmm64u(1) = BX_READ_XMM_REG_HI_QWORD(i->vvv());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
#endif
}
/* VEX.0F 16 (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVLHPS_VpsWps(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op;
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->vvv());
op.xmm64u(1) = BX_READ_XMM_REG_LO_QWORD(i->rm());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
#endif
}
/* VEX.66.0F 16 (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVHPD_VpdMq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
BxPackedXmmRegister op;
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->vvv());
op.xmm64u(1) = read_virtual_qword(i->seg(), eaddr);
BX_WRITE_XMM_REG_CLEAR_HIGH(i->nnn(), op);
#endif
}
/* VUNPCKLPS: VEX. 0F 14 (VEX.W ignore) */
/* VPUNPCKLDQ: VEX.66.0F 62 (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKLPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++) {
op1.avx32u(n*4+3) = op2.avx32u(n*4+1);
op1.avx32u(n*4+2) = op1.avx32u(n*4+1);
op1.avx32u(n*4+1) = op2.avx32u(n*4);
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* VUNPCKHPS: VEX. 0F 15 (VEX.W ignore) */
/* VPUNPCKHDQ: VEX.66.0F 6A (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKHPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++) {
op1.avx32u(n*4+0) = op1.avx32u(n*4+2);
op1.avx32u(n*4+1) = op2.avx32u(n*4+2);
op1.avx32u(n*4+2) = op1.avx32u(n*4+3);
op1.avx32u(n*4+3) = op2.avx32u(n*4+3);
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* VUNPCKLPD: VEX.66.0F 14 (VEX.W ignore) */
/* VPUNPCKLQDQ: VEX.66.0F 6C (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKLPD_VpdWpdR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++)
op1.avx64u(n*2+1) = op2.avx64u(n*2);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* VUNPCKLPD: VEX.66.0F 15 (VEX.W ignore) */
/* VPUNPCKLQDQ: VEX.66.0F 6D (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VUNPCKHPD_VpdWpdR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < len; n++) {
op1.avx64u(n*2) = op1.avx64u(n*2+1);
op1.avx64u(n*2+1) = op2.avx64u(n*2+1);
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* VEX.0F 50 (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVMSKPS_GdVRps(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
Bit32u val32 = 0;
for (unsigned n=0; n < (4*len); n++)
if(op.avx32u(n) & 0x80000000) val32 |= (1 << n);
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
#endif
}
/* VEX.66.0F 50 (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMOVMSKPD_GdVRpd(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
Bit32u val32 = 0;
for (unsigned n=0; n < (2*len); n++)
if(op.avx32u(2*n+1) & 0x80000000) val32 |= (1 << n);
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
#endif
}
/* VEX.66.0F 50 (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVMSKB_GdUdq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
Bit32u val32 = 0;
for (unsigned n=0; n < (16*len); n++)
if(op.avxubyte(n) & 0x80) val32 |= (1 << n);
BX_WRITE_32BIT_REGZ(i->nnn(), val32);
#endif
}
/* VANDPS: VEX 0F 54 (VEX.W ignore) */
/* VANDPD: VEX.66.0F 54 (VEX.W ignore) */
/* VPAND: VEX.66.0F DB (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VANDPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n++)
op1.avx64u(n) = op1.avx64u(n) & op2.avx64u(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* VANDNPS: VEX 0F 55 (VEX.W ignore) */
/* VANDNPD: VEX.66.0F 55 (VEX.W ignore) */
/* VPANDN: VEX.66.0F DF (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VANDNPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n++)
op1.avx64u(n) = ~(op1.avx64u(n)) & op2.avx64u(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* VORPS: VEX 0F 56 (VEX.W ignore) */
/* VORPD: VEX.66.0F 56 (VEX.W ignore) */
/* VPOR: VEX.66.0F EB (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VORPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n++)
op1.avx64u(n) = op1.avx64u(n) | op2.avx64u(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* VXORPS: VEX 0F 57 (VEX.W ignore) */
/* VXORPD: VEX.66.0F 57 (VEX.W ignore) */
/* VPXOR: VEX.66.0F EF (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VXORPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n++)
op1.avx64u(n) = op1.avx64u(n) ^ op2.avx64u(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* Opcode: VEX.0F.C6 (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPS_VpsWpsIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
Bit8u order = i->Ib();
for (unsigned n=0; n < (4*len); n+=4) {
result.avx32u(n) = op1.avx32u(n + ((order >> 0) & 0x3));
result.avx32u(n+1) = op1.avx32u(n + ((order >> 2) & 0x3));
result.avx32u(n+2) = op2.avx32u(n + ((order >> 4) & 0x3));
result.avx32u(n+3) = op2.avx32u(n + ((order >> 6) & 0x3));
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
#endif
}
/* Opcode: VEX.66.0F.C6 (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VSHUFPD_VpdWpdIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
Bit8u order = i->Ib();
for (unsigned n=0; n < (2*len); n+=2) {
result.avx64u(n) = op1.avx64u(n + ((order >> 0) & 0x1));
result.avx64u(n+1) = op2.avx64u(n + ((order >> 1) & 0x1));
order >>= 2;
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
#endif
}
/* Opcode: VEX.66.0F.38.17 (VEX.W ignore, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPTEST_VdqWdqR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->nnn()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
unsigned result = EFlagsZFMask | EFlagsCFMask;
for (unsigned n=0; n < (2*len); n++) {
if ((op2.avx64u(n) & op1.avx64u(n)) != 0) result &= ~EFlagsZFMask;
if ((op2.avx64u(n) & ~op1.avx64u(n)) != 0) result &= ~EFlagsCFMask;
}
setEFlagsOSZAPC(result);
#endif
}
/* Opcode: VEX.66.0F.38.18 /r (VEX.W=0, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VBROADCASTSS_VpsMss(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
unsigned len = i->getVL();
BxPackedAvxRegister op;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u val32 = read_virtual_dword(i->seg(), eaddr);
for (unsigned n=0; n < len; n++) {
op.avx32u(n*4) = val32;
op.avx32u(n*4+1) = val32;
op.avx32u(n*4+2) = val32;
op.avx32u(n*4+3) = val32;
}
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
#endif
}
/* Opcode: VEX.256.66.0F.38.19 (VEX.W=0, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VBROADCASTSD_VpdMsd(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
unsigned len = i->getVL();
BxPackedAvxRegister op;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit64u val64 = read_virtual_qword(i->seg(), eaddr);
for (unsigned n=0; n < len; n++) {
op.avx64u(n*2) = val64;
op.avx64u(n*2+1) = val64;
}
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
#endif
}
/* Opcode: VEX.256.66.0F.38.1A (VEX.W=0, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VBROADCASTF128_VdqMdq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
unsigned len = i->getVL();
BxPackedAvxRegister op;
BxPackedXmmRegister src;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
read_virtual_dqword(i->seg(), eaddr, (Bit8u*) &src);
for (unsigned n=0; n < len; n++) {
op.avx64u(n*2) = src.xmm64u(0);
op.avx64u(n*2+1) = src.xmm64u(1);
}
BX_WRITE_AVX_REGZ(i->nnn(), op, len);
#endif
}
/* Opcode: VEX.66.0F.3A 0C (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPS_VpsWpsIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
Bit8u mask = i->Ib();
for (unsigned n=0; n < (4*len); n++) {
if (mask & 0x1) op1.avx32u(n) = op2.avx32u(n);
mask >>= 1;
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* Opcode: VEX.66.0F.3A 0D (VEX.W ignore) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDPD_VpdWpdIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
Bit8u mask = i->Ib();
for (unsigned n=0; n < (2*len); n++) {
if (mask & 0x1) op1.avx64u(n) = op2.avx64u(n);
mask >>= 1;
}
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* Opcode: VEX.66.0F.3A 4A (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPS_VpsWpsIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()),
mask = BX_READ_AVX_REG(i->Ib());
unsigned len = i->getVL();
for (unsigned n=0; n < (4*len); n++)
if (mask.avx32u(n) & 0x80000000) op1.avx32u(n) = op2.avx32u(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* Opcode: VEX.66.0F.3A 4B (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VBLENDVPD_VpdWpdIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()),
mask = BX_READ_AVX_REG(i->Ib());
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n++)
if (mask.avx32u(n*2+1) & 0x80000000) op1.avx64u(n) = op2.avx64u(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* Opcode: VEX.66.0F.3A 4C (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPBLENDVB_VdqWdqIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv()), op2 = BX_READ_AVX_REG(i->rm()),
mask = BX_READ_AVX_REG(i->Ib());
unsigned len = i->getVL();
for(unsigned n=0; n<(16*len); n++)
if (mask.avxubyte(n) & 0x80) op1.avxubyte(n) = op2.avxubyte(n);
BX_WRITE_AVX_REGZ(i->nnn(), op1, len);
#endif
}
/* Opcode: VEX.66.0F.3A 18 (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VINSERTF128_VdqWdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm());
op1.avx128(i->Ib() & 1) = op2;
BX_WRITE_AVX_REG(i->nnn(), op1);
}
/* Opcode: VEX.66.0F.3A 19 (VEX.W=0, VEX.VVV #UD) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF128_WdqVdqIbM(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->nnn());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dqword(i->seg(), eaddr, &(op.avx128(i->Ib() & 1)));
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VEXTRACTF128_WdqVdqIbR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->nnn());
BX_WRITE_XMM_REG_CLEAR_HIGH(i->rm(), op.avx128(i->Ib() & 1));
}
/* Opcode: VEX.66.0F.38 0C (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsWpsR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < (4*len); n+=4) {
result.avx32u(n) = op1.avx32u(n + (op2.avx32u(n) & 0x3));
result.avx32u(n+1) = op1.avx32u(n + (op2.avx32u(n+1) & 0x3));
result.avx32u(n+2) = op1.avx32u(n + (op2.avx32u(n+2) & 0x3));
result.avx32u(n+3) = op1.avx32u(n + (op2.avx32u(n+3) & 0x3));
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
#endif
}
/* Opcode: VEX.66.0F.3A 05 (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdWpdR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
for (unsigned n=0; n < (2*len); n+=2) {
result.avx64u(n) = op1.avx64u(n + ((op2.avx32u(n*2+0) >> 1) & 0x1));
result.avx64u(n+1) = op1.avx64u(n + ((op2.avx32u(n*2+2) >> 1) & 0x1));
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
#endif
}
/* Opcode: VEX.66.0F.3A 04 (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPS_VpsWpsIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
Bit8u order = i->Ib();
for (unsigned n=0; n < (4*len); n+=4) {
result.avx32u(n) = op1.avx32u(n + ((order >> 0) & 0x3));
result.avx32u(n+1) = op1.avx32u(n + ((order >> 2) & 0x3));
result.avx32u(n+2) = op1.avx32u(n + ((order >> 4) & 0x3));
result.avx32u(n+3) = op1.avx32u(n + ((order >> 6) & 0x3));
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
#endif
}
/* Opcode: VEX.66.0F.3A 05 (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMILPD_VpdWpdIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->rm()), result;
unsigned len = i->getVL();
Bit8u order = i->Ib();
for (unsigned n=0; n < (2*len); n+=2) {
result.avx64u(n) = op1.avx64u(n + ((order >> 0) & 0x1));
result.avx64u(n+1) = op1.avx64u(n + ((order >> 1) & 0x1));
order >>= 2;
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
#endif
}
/* Opcode: VEX.66.0F.3A 06 (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERM2F128_VdqWdqIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->vvv());
BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->rm()), result;
Bit8u order = i->Ib();
for (unsigned n=0;n<2;n++) {
if (order & 0x8) {
result.avx64u(n*2) = result.avx64u(n*2+1) = 0;
}
else {
if (order & 0x2)
result.avx128(n) = op2.avx128(order & 0x1);
else
result.avx128(n) = op1.avx128(order & 0x1);
}
order >>= 4;
}
BX_WRITE_AVX_REG(i->nnn(), result);
#endif
}
/* Opcode: VEX.66.0F.38 2C (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_VpsMps(bxInstruction_c *i)
{
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), result;
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
#if BX_SUPPORT_X86_64
if (i->as64L()) {
for (unsigned n=0; n < (4*len); n++) {
if (mask.avx32u(n) & 0x80000000) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 4*n)))
exception(int_number(i->seg()), 0);
}
}
}
#endif
for (int n=4*len-1; n >= 0; n--) {
if (mask.avx32u(n) & 0x80000000)
result.avx32u(n) = read_virtual_dword(i->seg(), (eaddr + 4*n) & i->asize_mask());
else
result.avx32u(n) = 0;
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
}
/* Opcode: VEX.66.0F.38 2D (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_VpdMpd(bxInstruction_c *i)
{
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), result;
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
#if BX_SUPPORT_X86_64
if (i->as64L()) {
for (unsigned n=0; n < (2*len); n++) {
if (mask.avx32u(n*2+1) & 0x80000000) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 8*n)))
exception(int_number(i->seg()), 0);
}
}
}
#endif
for (int n=2*len-1; n >= 0; n--) {
if (mask.avx32u(n*2+1) & 0x80000000)
result.avx64u(n) = read_virtual_qword(i->seg(), (eaddr + 8*n) & i->asize_mask());
else
result.avx64u(n) = 0;
}
BX_WRITE_AVX_REGZ(i->nnn(), result, len);
}
/* Opcode: VEX.66.0F.38 2C (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsVps(bxInstruction_c *i)
{
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), op = BX_READ_AVX_REG(i->nnn());
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
#if BX_SUPPORT_X86_64
if (i->as64L()) {
for (unsigned n=0; n < (4*len); n++) {
if (mask.avx32u(n) & 0x80000000) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 4*n)))
exception(int_number(i->seg()), 0);
}
}
}
#endif
// see you can successfully write all the elements first
for (int n=4*len-1; n >= 0; n--) {
if (mask.avx32u(n) & 0x80000000)
read_RMW_virtual_dword(i->seg(), (eaddr + 4*n) & i->asize_mask());
}
for (unsigned n=0; n < (4*len); n++) {
if (mask.avx32u(n) & 0x80000000)
write_virtual_dword(i->seg(), (eaddr + 4*n) & i->asize_mask(), op.avx32u(n));
}
}
/* Opcode: VEX.66.0F.38 2D (VEX.W=0) */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPD_MpdVpd(bxInstruction_c *i)
{
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), op = BX_READ_AVX_REG(i->nnn());
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
#if BX_SUPPORT_X86_64
if (i->as64L()) {
for (unsigned n=0; n < (2*len); n++) {
if (mask.avx32u(n*2+1) & 0x80000000) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 8*n)))
exception(int_number(i->seg()), 0);
}
}
}
#endif
// see you can successfully write all the elements first
for (int n=2*len-1; n >= 0; n--) {
if (mask.avx32u(2*n+1) & 0x80000000)
read_RMW_virtual_qword(i->seg(), (eaddr + 8*n) & i->asize_mask());
}
for (unsigned n=0; n < (2*len); n++) {
if (mask.avx32u(2*n+1) & 0x80000000)
write_virtual_qword(i->seg(), (eaddr + 8*n) & i->asize_mask(), op.avx64u(n));
}
}
#endif

1650
bochs/cpu/avx_pfp.cc Normal file
View File

File diff suppressed because it is too large Load Diff

4
bochs/cpu/cpu.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
// Copyright (C) 2001-2011 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -129,6 +129,8 @@ void BX_CPU_C::cpu_loop(Bit32u max_instr_count)
for(;;) {
#endif
//printf("%s\n", get_bx_opcode_name(i->getIaOpcode()));
#if BX_DISASM
if (BX_CPU_THIS_PTR trace) {
// print the instruction that is about to be executed

208
bochs/cpu/cpu.h
View File

@ -904,6 +904,7 @@ public: // for now...
#if BX_CPU_LEVEL >= 6
xcr0_t xcr0;
Bit32u xcr0_suppmask;
#endif
/* SMM base register */
@ -922,7 +923,11 @@ public: // for now...
#endif
#if BX_CPU_LEVEL >= 6
bx_xmm_reg_t xmm[BX_XMM_REGISTERS+1];
#if BX_SUPPORT_AVX
bx_avx_reg_t vmm[BX_XMM_REGISTERS+1];
#else
bx_xmm_reg_t vmm[BX_XMM_REGISTERS+1];
#endif
bx_mxcsr_t mxcsr;
Bit32u mxcsr_mask;
#endif
@ -991,6 +996,9 @@ public: // for now...
#endif
#if BX_CPU_LEVEL >= 6
unsigned sse_ok;
#if BX_SUPPORT_AVX
unsigned avx_ok;
#endif
#endif
// for exceptions
@ -1772,6 +1780,10 @@ public: // for now...
BX_SMF void LOAD_Wss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void LOAD_Wsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void LOAD_Ww(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#if BX_SUPPORT_AVX
BX_SMF void LOAD_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void LOAD_VectorQ(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
#if BX_SUPPORT_FPU == 0 // if FPU is disabled
BX_SMF void FPU_ESC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2362,6 +2374,122 @@ public: // for now...
BX_SMF void INVVPID(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* VMXx2 */
#if BX_SUPPORT_AVX
BX_SMF void VZEROUPPER(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVSS_VssWssR(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVSD_VsdWsdR(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVAPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVAPS_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVUPS_VpsWpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVAPS_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVUPS_WpsVpsM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVLPD_VpdMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVHPD_VpdMq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVLHPS_VpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVHLPS_VpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVSHDUP_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVSLDUP_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVDDUP_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VUNPCKLPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VUNPCKHPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VUNPCKLPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VUNPCKHPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVMSKPS_GdVRps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMOVMSKPD_GdVRpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VPMOVMSKB_GdUdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSQRTPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSQRTSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSQRTSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VHADDPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VHADDPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VHSUBPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VHSUBPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VADDPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VADDPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VADDSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VADDSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMULPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMULPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMULSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMULSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSUBPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSUBPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSUBSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSUBSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTSS2SD_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTSD2SS_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTDQ2PS_VpsWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTPS2DQ_VdqWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTTPS2DQ_VdqWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTPS2PD_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTPD2PS_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTPD2DQ_VqWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTDQ2PD_VpdWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTTPD2DQ_VqWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTSI2SD_VsdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTSI2SS_VssEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTSI2SD_VsdEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCVTSI2SS_VssEqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMINPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMINPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMINSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMINSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VDIVPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VDIVPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VDIVSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VDIVSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMAXPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMAXPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMAXSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMAXSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCMPPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCMPSS_VssWssIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCMPPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VCMPSD_VsdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VADDSUBPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VADDSUBPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VROUNDPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VROUNDPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VROUNDSS_VssWssIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VROUNDSD_VsdWsdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VDPPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VRSQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VRSQRTSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VRCPPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VRCPSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSHUFPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VSHUFPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VBLENDPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VBLENDPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VPBLENDVB_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VPTEST_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VTESTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VTESTPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VANDPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VANDNPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VORPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VXORPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VBROADCASTSS_VpsMss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VBROADCASTSD_VpdMsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VBROADCASTF128_VdqMdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VBLENDVPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VBLENDVPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VINSERTF128_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VEXTRACTF128_WdqVdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VEXTRACTF128_WdqVdqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VPERMILPS_VpsWpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VPERMILPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VPERMILPD_VpdWpdIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VPERMILPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VPERM2F128_VdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMASKMOVPS_VpsMps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMASKMOVPD_VpdMpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMASKMOVPS_MpsVps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void VMASKMOVPD_MpdVpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
BX_SMF void CMPXCHG_XBTS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CMPXCHG_IBTS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CMPXCHG8B(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2798,6 +2926,7 @@ public: // for now...
BX_SMF void BxError(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#if BX_CPU_LEVEL >= 6
BX_SMF void BxNoSSE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void BxNoAVX(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
BX_SMF bx_address BxResolve16BaseIndex(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2867,6 +2996,10 @@ public: // for now...
#if BX_CPU_LEVEL >= 6
BX_SMF void read_virtual_dqword_32(unsigned seg, Bit32u off, BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
BX_SMF void read_virtual_dqword_aligned_32(unsigned seg, Bit32u off, BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
#if BX_SUPPORT_AVX
BX_SMF void read_virtual_vector_32(unsigned seg, Bit32u off, unsigned elements, BxPackedAvxRegister *data);
BX_SMF void read_virtual_vector_aligned_32(unsigned seg, Bit32u off, unsigned elements, BxPackedAvxRegister *data);
#endif
#endif
BX_SMF void write_virtual_byte_32(unsigned seg, Bit32u offset, Bit8u data) BX_CPP_AttrRegparmN(3);
@ -2876,6 +3009,10 @@ public: // for now...
#if BX_CPU_LEVEL >= 6
BX_SMF void write_virtual_dqword_32(unsigned seg, Bit32u offset, const BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
BX_SMF void write_virtual_dqword_aligned_32(unsigned seg, Bit32u offset, const BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
#if BX_SUPPORT_AVX
BX_SMF void write_virtual_vector_32(unsigned seg, Bit32u off, unsigned elements, const BxPackedAvxRegister *data);
BX_SMF void write_virtual_vector_aligned_32(unsigned seg, Bit32u off, unsigned elements, const BxPackedAvxRegister *data);
#endif
#endif
BX_SMF Bit8u read_RMW_virtual_byte_32(unsigned seg, Bit32u offset) BX_CPP_AttrRegparmN(2);
@ -2895,6 +3032,10 @@ public: // for now...
BX_SMF void write_virtual_qword_64(unsigned seg, Bit64u offset, Bit64u data) BX_CPP_AttrRegparmN(3);
BX_SMF void write_virtual_dqword_64(unsigned seg, Bit64u offset, const BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
BX_SMF void write_virtual_dqword_aligned_64(unsigned seg, Bit64u offset, const BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
#if BX_SUPPORT_AVX
BX_SMF void write_virtual_vector_64(unsigned seg, Bit64u offset, unsigned elements, const BxPackedAvxRegister *data);
BX_SMF void write_virtual_vector_aligned_64(unsigned seg, Bit64u offset, unsigned elements, const BxPackedAvxRegister *data);
#endif
BX_SMF Bit8u read_virtual_byte_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
BX_SMF Bit16u read_virtual_word_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
@ -2902,6 +3043,10 @@ public: // for now...
BX_SMF Bit64u read_virtual_qword_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
BX_SMF void read_virtual_dqword_64(unsigned seg, Bit64u off, BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
BX_SMF void read_virtual_dqword_aligned_64(unsigned seg, Bit64u off, BxPackedXmmRegister *data) BX_CPP_AttrRegparmN(3);
#if BX_SUPPORT_AVX
BX_SMF void read_virtual_vector_64(unsigned seg, Bit64u offset, unsigned elements, BxPackedAvxRegister *data);
BX_SMF void read_virtual_vector_aligned_64(unsigned seg, Bit64u offset, unsigned elements, BxPackedAvxRegister *data);
#endif
BX_SMF Bit8u read_RMW_virtual_byte_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
BX_SMF Bit16u read_RMW_virtual_word_64(unsigned seg, Bit64u offset) BX_CPP_AttrRegparmN(2);
@ -2952,6 +3097,20 @@ public: // for now...
write_virtual_dqword_aligned_64(seg, (Bit64u) offset, (const BxPackedXmmRegister*)(data)) : \
write_virtual_dqword_aligned_32(seg, (Bit32u) offset, (const BxPackedXmmRegister*)(data))
#if BX_SUPPORT_AVX
#define write_virtual_vector(seg, offset, elements, data) \
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
write_virtual_vector_64(seg, (Bit64u) offset, elements, (const BxPackedAvxRegister*)(data)) : \
write_virtual_vector_32(seg, (Bit32u) offset, elements, (const BxPackedAvxRegister*)(data))
#define write_virtual_vector_aligned(seg, offset, elements, data) \
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
write_virtual_vector_aligned_64(seg, (Bit64u) offset, elements, (const BxPackedAvxRegister*)(data)) : \
write_virtual_vector_aligned_32(seg, (Bit32u) offset, elements, (const BxPackedAvxRegister*)(data))
#endif
// read
#define read_virtual_byte(seg, offset) \
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
@ -2983,6 +3142,20 @@ public: // for now...
read_virtual_dqword_aligned_64(seg, (Bit64u) offset, (BxPackedXmmRegister*)(data)) : \
read_virtual_dqword_aligned_32(seg, (Bit32u) offset, (BxPackedXmmRegister*)(data))
#if BX_SUPPORT_AVX
#define read_virtual_vector(seg, offset, elements, data) \
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
read_virtual_vector_64(seg, (Bit64u) offset, elements, (BxPackedAvxRegister*)(data)) : \
read_virtual_vector_32(seg, (Bit32u) offset, elements, (BxPackedAvxRegister*)(data))
#define read_virtual_vector_aligned(seg, offset, elements, data) \
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
read_virtual_vector_aligned_64(seg, (Bit64u) offset, elements, (BxPackedAvxRegister*)(data)) : \
read_virtual_vector_aligned_32(seg, (Bit32u) offset, elements, (BxPackedAvxRegister*)(data))
#endif
// RMW
#define read_RMW_virtual_byte(seg, offset) \
(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) ? \
@ -3020,6 +3193,15 @@ public: // for now...
#define write_virtual_dqword_aligned(seg, offset, data) \
write_virtual_dqword_aligned_32(seg, offset, (const BxPackedXmmRegister*)(data))
#if BX_SUPPORT_AVX
#define write_virtual_vector(seg, offset, elements, data) \
write_virtual_vector_32(seg, offset, elements, (const BxPackedAvxRegister*)(data))
#define write_virtual_vector_aligned(seg, offset, elements, data) \
write_virtual_vector_aligned_32(seg, offset, elements, (const BxPackedAvxRegister*)(data))
#endif
// read
#define read_virtual_byte(seg, offset) \
read_virtual_byte_32(seg, offset)
@ -3034,6 +3216,15 @@ public: // for now...
#define read_virtual_dqword_aligned(seg, offset, data) \
read_virtual_dqword_aligned_32(seg, offset, (BxPackedXmmRegister*)(data))
#if BX_SUPPORT_AVX
#define read_virtual_vector(seg, offset, elements, data) \
read_virtual_vector_32(seg, offset, elements, (BxPackedAvxRegister*)(data))
#define read_virtual_vector_aligned(seg, offset, elements, data) \
read_virtual_vector_aligned_32(seg, offset, elements, (BxPackedAvxRegister*)(data))
#endif
// RMW
#define read_RMW_virtual_byte(seg, offset) \
read_RMW_virtual_byte_32(seg, offset)
@ -3166,6 +3357,7 @@ public: // for now...
#endif
#if BX_CPU_LEVEL >= 6
BX_SMF void handleSseModeChange(void);
BX_SMF void handleAvxModeChange(void);
#endif
#if BX_CPU_LEVEL >= 5
@ -3394,10 +3586,9 @@ public: // for now...
#if BX_CPU_LEVEL >= 6
BX_SMF void check_exceptionsSSE(int);
BX_SMF void print_state_SSE(void);
#endif
#if BX_CPU_LEVEL >= 6
BX_SMF void prepareXSAVE(void);
BX_SMF void print_state_AVX(void);
#endif
#if BX_SUPPORT_MONITOR_MWAIT
@ -3535,14 +3726,18 @@ BX_CPP_INLINE void BX_CPU_C::prepareXSAVE(void)
// bit 0 - CS.D_B
// bit 1 - long64 mode (CS.L)
// bit 2 - SSE_OK
// bit 3 - AVX_OK
//
// updateFetchModeMask - has to be called everytime
// CS.L or CS.D_B / CR0.TS or CR0.EM / CR4.OSFXSR changes
// CS.L / CS.D_B / CR0.PE, CR0.TS or CR0.EM / CR4.OSFXSR / CR4.OSXSAVE changes
//
BX_CPP_INLINE void BX_CPU_C::updateFetchModeMask(void)
{
BX_CPU_THIS_PTR fetchModeMask =
#if BX_CPU_LEVEL >= 6
#if BX_SUPPORT_AVX
(BX_CPU_THIS_PTR avx_ok << 3) |
#endif
(BX_CPU_THIS_PTR sse_ok << 2) |
#endif
#if BX_SUPPORT_X86_64
@ -3889,7 +4084,8 @@ enum {
#if BX_SUPPORT_X86_64
#define BxImmediate_Iq 0x0007 // 64 bit override
#endif
#define BxImmediate_BrOff8 0x0008 // Relative branch offset byte
#define BxImmediate_Ib4 0x0008 // Register encoded in Ib[7:4]
#define BxImmediate_BrOff8 0x0009 // Relative branch offset byte
#define BxImmediate_BrOff16 BxImmediate_Iw // Relative branch offset word, not encodable in 64-bit mode
#define BxImmediate_BrOff32 BxImmediate_Id // Relative branch offset dword
@ -3906,6 +4102,8 @@ enum {
#define BxFPEscape 0x0070 // Group encoding: 0111
#define Bx3ByteOp 0x0080 // Group encoding: 1000
#define BxOSizeGrp 0x0090 // Group encoding: 1001
#define BxPrefixVEX 0x00A0 // Group encoding: 1010
#define BxSplitVexW 0x00B0 // Group encoding: 1011
// The BxImmediate2 mask specifies kind of second immediate data
// required by instruction.

59
bochs/cpu/cpuid.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007-2010 Stanislav Shwartsman
// Copyright (c) 2007-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -152,6 +152,12 @@ Bit32u BX_CPU_C::get_extended_cpuid_features(void)
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE))
features |= BX_CPUID_EXT_XSAVE | BX_CPUID_EXT_OSXSAVE;
#if BX_SUPPORT_AVX
// support AVX extensions
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_AVX))
features |= BX_CPUID_EXT_AVX;
#endif
return features;
}
@ -614,9 +620,17 @@ void BX_CPU_C::set_cpuid_defaults(void)
// EBX - Maximum size (in bytes) required by enabled features
// ECX - Maximum size (in bytes) required by CPU supported features
// EDX - valid bits of XCR0 (upper part)
cpuid->eax = BX_XCR0_SUPPORTED_BITS;
cpuid->eax = BX_CPU_THIS_PTR xcr0_suppmask;
cpuid->ebx = 512+64;
#if BX_SUPPORT_AVX
if (BX_CPU_THIS_PTR xcr0_suppmask & BX_XCR0_AVX_MASK)
cpuid->ebx += 256;
#endif
cpuid->ecx = 512+64;
#if BX_SUPPORT_AVX
if (BX_CPU_THIS_PTR xcr0_suppmask & BX_XCR0_AVX_MASK)
cpuid->ecx += 256;
#endif
cpuid->edx = 0;
BX_INFO(("CPUID[0x0000000D]: %08x %08x %08x %08x", cpuid->eax, cpuid->ebx, cpuid->ecx, cpuid->edx));
@ -939,17 +953,40 @@ void BX_CPU_C::bx_cpuid_extended_cpuid_leaf(Bit32u subfunction)
void BX_CPU_C::bx_cpuid_xsave_leaf(Bit32u subfunction)
{
BX_ASSERT(BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE));
if (subfunction == 0) {
switch(subfunction) {
case 0:
RAX = BX_CPU_THIS_PTR cpuid_std_function[0xd].eax;
RBX = BX_CPU_THIS_PTR cpuid_std_function[0xd].ebx;
RCX = BX_CPU_THIS_PTR cpuid_std_function[0xd].ecx;
RDX = BX_CPU_THIS_PTR cpuid_std_function[0xd].edx;
}
else {
break;
case 1:
RAX = 0; // TODO: report XSAVEOPT
RBX = 0;
RCX = 0;
RDX = 0;
break;
#if BX_SUPPORT_AVX
case 2: // AVX leaf
if (BX_CPU_THIS_PTR xcr0_suppmask & BX_XCR0_AVX_MASK) {
RAX = 256;
RBX = 576;
RCX = 0;
RDX = 0;
break;
}
// else fall through
#endif
default:
RAX = 0; // reserved
RBX = 0; // reserved
RCX = 0; // reserved
RDX = 0; // reserved
break;
}
}
#endif
@ -1028,6 +1065,13 @@ void BX_CPU_C::init_isa_features_bitmask(void)
}
}
#if BX_SUPPORT_AVX
if (BX_SUPPORT_AVX && ! xsave_enabled) {
BX_PANIC(("PANIC: AVX emulation requires XSAVE support !"));
return;
}
#endif
#if BX_SUPPORT_X86_64
if (sse_enabled < BX_CPUID_SUPPORT_SSE2) {
BX_PANIC(("PANIC: x86-64 emulation requires SSE2 support !"));
@ -1113,6 +1157,9 @@ void BX_CPU_C::init_isa_features_bitmask(void)
if (movbe_enabled)
features_bitmask |= BX_CPU_MOVBE;
#if BX_SUPPORT_AVX
features_bitmask |= BX_CPU_AVX;
#endif
#if BX_SUPPORT_VMX
@ -1125,6 +1172,8 @@ void BX_CPU_C::init_isa_features_bitmask(void)
static bx_bool fsgsbase_enabled = SIM->get_param_bool(BXPN_CPUID_FSGSBASE)->get();
if (fsgsbase_enabled)
features_bitmask |= BX_CPU_FSGSBASE;
#endif
#endif
BX_CPU_THIS_PTR isa_extensions_bitmask = features_bitmask;

11
bochs/cpu/crregs.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2010 Stanislav Shwartsman
// Copyright (c) 2010-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -951,6 +951,9 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR0(bx_address val)
#if BX_CPU_LEVEL >= 6
handleSseModeChange();
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
#endif
// Modification of PG,PE flushes TLB cache according to docs.
@ -1131,6 +1134,9 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR4(bx_address val)
#if BX_CPU_LEVEL >= 6
handleSseModeChange();
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
#endif
return 1;
@ -1176,6 +1182,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CLTS(bxInstruction_c *i)
#if BX_CPU_LEVEL >= 6
handleSseModeChange();
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
#endif
}

7
bochs/cpu/crregs.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007-2009 Stanislav Shwartsman
// Copyright (c) 2007-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -209,15 +209,18 @@ struct bx_efer_t {
struct xcr0_t {
Bit32u val32; // 32bit value of register
#define BX_XCR0_SUPPORTED_BITS 0x3
#define BX_XCR0_SUPPORTED_BITS 0x7
#define BX_XCR0_FPU_BIT 0
#define BX_XCR0_FPU_MASK (1<<BX_XCR0_FPU_BIT)
#define BX_XCR0_SSE_BIT 1
#define BX_XCR0_SSE_MASK (1<<BX_XCR0_SSE_BIT)
#define BX_XCR0_AVX_BIT 2
#define BX_XCR0_AVX_MASK (1<<BX_XCR0_AVX_BIT)
IMPLEMENT_CRREG_ACCESSORS(FPU, BX_XCR0_FPU_BIT);
IMPLEMENT_CRREG_ACCESSORS(SSE, BX_XCR0_SSE_BIT);
IMPLEMENT_CRREG_ACCESSORS(AVX, BX_XCR0_AVX_BIT);
BX_CPP_INLINE Bit32u get32() const { return val32; }
BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }

175
bochs/cpu/fetchdecode.cc
View File

@ -359,8 +359,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* C1 /w */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2Ew },
/* C2 /w */ { BxImmediate_Iw | BxTraceEnd, BX_IA_RETnear16_Iw },
/* C3 /w */ { BxTraceEnd, BX_IA_RETnear16 },
/* C4 /w */ { 0, BX_IA_LES_GwMp },
/* C5 /w */ { 0, BX_IA_LDS_GwMp },
/* C4 /w */ { BxPrefixVEX, BX_IA_LES_GwMp },
/* C5 /w */ { BxPrefixVEX, BX_IA_LDS_GwMp },
/* C6 /w */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Eb },
/* C7 /w */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Ew },
/* C8 /w */ { BxImmediate_Iw | BxImmediate_Ib2, BX_IA_ENTER16_IwIb },
@ -904,8 +904,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* C1 /d */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2Ed },
/* C2 /d */ { BxImmediate_Iw | BxTraceEnd, BX_IA_RETnear32_Iw },
/* C3 /d */ { BxTraceEnd, BX_IA_RETnear32 },
/* C4 /d */ { 0, BX_IA_LES_GdMp },
/* C5 /d */ { 0, BX_IA_LDS_GdMp },
/* C4 /d */ { BxPrefixVEX, BX_IA_LES_GdMp },
/* C5 /d */ { BxPrefixVEX, BX_IA_LDS_GdMp },
/* C6 /d */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Eb },
/* C7 /d */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Ed },
/* C8 /d */ { BxImmediate_Iw | BxImmediate_Ib2, BX_IA_ENTER32_IwIb },
@ -1270,6 +1270,13 @@ BX_CPU_C::fetchDecode32(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
#define SSE_PREFIX_F2 3
unsigned sse_prefix = SSE_PREFIX_NONE;
int had_vex = 0;
#if BX_SUPPORT_AVX
int vvv = -1;
unsigned vex;
bx_bool vex_w = 0;
#endif
os_32 = is_32 =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b;
@ -1338,12 +1345,66 @@ fetch_b1:
}
i->setB1(b1);
i->setVL(BX_NO_VL);
unsigned index = b1 + (os_32 << 9); // *512
unsigned attr = BxOpcodeInfo32[index].Attr;
bx_bool has_modrm = BxOpcodeHasModrm32[b1];
bx_bool has_modrm = 0;
#if BX_SUPPORT_AVX
if ((attr & BxGroupX) == BxPrefixVEX && (*iptr & 0xc0) == 0xc0) {
had_vex = 1;
if (sse_prefix) had_vex = -1;
unsigned vex_opcext = 1;
if (remain != 0) {
remain--;
vex = *iptr++;
}
else
return(-1);
if (b1 == 0xc4) {
// decode 3-byte VEX prefix
vex_opcext = vex & 0x1f;
if (remain != 0) {
remain--;
vex = *iptr++; // fetch VEX3
}
else
return(-1);
vex_w = (vex >> 7) & 0x1;
}
vvv = 15 - ((vex >> 3) & 0xf);
i->setVL(BX_VL128 + ((vex >> 2) & 0x1));
sse_prefix = vex & 0x3;
if (remain != 0) {
remain--;
b1 = *iptr++; // fetch new b1
}
else
return(-1);
b1 += 256 * vex_opcext;
if (b1 < 256 || b1 >= 1024) had_vex = -1;
else {
if (b1 >= 512)
has_modrm = 1;
else
has_modrm = BxOpcodeHasModrm32[b1];
}
}
else
#endif
{
has_modrm = BxOpcodeHasModrm32[b1];
}
if (has_modrm) {
@ -1371,12 +1432,18 @@ fetch_b1:
nnn = (b2 >> 3) & 0x7;
rm = b2 & 0x7;
i->setNnn(nnn);
#if BX_SUPPORT_AVX
if (had_vex == 0) vvv = nnn;
i->setVvv(vvv);
#endif
// MOVs with CRx and DRx always use register ops and ignore the mod field.
if ((b1 & ~3) == 0x120)
mod = 0xc0;
i->setModRM(b2);
i->setNnn(nnn);
if ((b1 & 0xff8) == 0xd8)
i->setModRM(b2);
if (mod == 0xc0) { // mod == 11b
i->assertModC0();
@ -1516,7 +1583,17 @@ modrm_done:
// Resolve ExecutePtr and additional opcode Attr
const BxOpcodeInfo_t *OpcodeInfoPtr = &(BxOpcodeInfo32[index]);
attr = BxOpcodeInfo32[index].Attr;
#if BX_SUPPORT_AVX
if (had_vex != 0) {
if (had_vex < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
OpcodeInfoPtr = &BxOpcodeTableAVX[b1-256];
}
#endif
attr = OpcodeInfoPtr->Attr;
while(attr & BxGroupX) {
Bit32u group = attr & BxGroupX;
@ -1535,10 +1612,22 @@ modrm_done:
switch(group) {
case BxGroupN:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn]);
#if BX_SUPPORT_AVX
if (had_vex == 0) i->setVvv(rm);
#endif
break;
case BxSplitGroupN:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn + (mod_mem << 3)]);
break;
#if BX_SUPPORT_AVX
case BxSplitVexW:
BX_ASSERT(had_vex != 0);
if (vex_w)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[0]);
break;
#endif
case Bx3ByteOp:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[b3]);
break;
@ -1559,8 +1648,10 @@ modrm_done:
else
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[(b2 & 0x3f) + 8]);
break;
case BxPrefixVEX:
continue;
default:
BX_PANIC(("fetchdecode: Unknown opcode group"));
BX_PANIC(("fetchdecode: Unknown opcode group %d", group));
}
/* get additional attributes from group table */
@ -1577,10 +1668,20 @@ modrm_done:
const BxOpcodeInfo_t *OpcodeInfoPtr = &(BxOpcodeInfo32[index]);
#if BX_SUPPORT_AVX
if (had_vex != 0) {
i->setVvv(vvv);
if (had_vex < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
OpcodeInfoPtr = &BxOpcodeTableAVX[b1-256];
}
#endif
unsigned group = attr & BxGroupX;
BX_ASSERT(group == BxPrefixSSE || group == 0);
if (group == BxPrefixSSE && sse_prefix)
if (group == BxPrefixSSE && sse_prefix) {
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix-1]);
}
ia_opcode = OpcodeInfoPtr->IA;
i->setRm(b1 & 7);
@ -1667,6 +1768,17 @@ modrm_done:
else return(-1);
}
break;
#if BX_SUPPORT_AVX
case BxImmediate_Ib4:
if (remain != 0) {
i->modRMForm.Ib = ((*iptr++) >> 4) & 7;
remain--;
}
else {
return(-1);
}
break;
#endif
default:
BX_INFO(("b1 was %x", b1));
BX_PANIC(("fetchdecode: imm_mode = %u", imm_mode));
@ -1712,6 +1824,35 @@ modrm_done:
i->setILen(remainingInPage - remain);
i->setIaOpcode(ia_opcode);
#if BX_CPU_LEVEL >= 6
Bit32u op_flags = BxOpcodesTable[ia_opcode].flags;
if (! BX_CPU_THIS_PTR sse_ok) {
if (op_flags & BX_PREPARE_SSE) {
if (i->execute != &BX_CPU_C::BxError) i->execute = &BX_CPU_C::BxNoSSE;
return(1);
}
}
#if BX_SUPPORT_AVX
if (! BX_CPU_THIS_PTR avx_ok) {
if (op_flags & BX_PREPARE_AVX) {
if (i->execute != &BX_CPU_C::BxError) i->execute = &BX_CPU_C::BxNoAVX;
return(1);
}
}
if (had_vex > 0) {
if ((op_flags & BX_VEX_NO_VVV) && i->vvv() != 0) {
ia_opcode = BX_IA_ERROR;
}
if (i->getVL() == BX_VEX_L128 && !(op_flags & BX_VEX_L128)) {
ia_opcode = BX_IA_ERROR;
}
if (i->getVL() == BX_VEX_L256 && !(op_flags & BX_VEX_L256)) {
ia_opcode = BX_IA_ERROR;
}
}
#endif
#endif
if (mod_mem) {
i->execute = BxOpcodesTable[ia_opcode].execute1;
i->execute2 = BxOpcodesTable[ia_opcode].execute2;
@ -1728,16 +1869,6 @@ modrm_done:
BX_ASSERT(i->execute);
#if BX_CPU_LEVEL >= 6
Bit32u op_flags = BxOpcodesTable[ia_opcode].flags;
if (! BX_CPU_THIS_PTR sse_ok) {
if (op_flags & BX_PREPARE_SSE) {
if (i->execute != &BX_CPU_C::BxError) i->execute = &BX_CPU_C::BxNoSSE;
return(1);
}
}
#endif
#if BX_SUPPORT_TRACE_CACHE
if ((attr & BxTraceEnd) || ia_opcode == BX_IA_ERROR)
return(1);
@ -1794,7 +1925,7 @@ void BX_CPU_C::init_FetchDecodeTables(void)
BX_PANIC(("init_FetchDecodeTables: CPU features bitmask is empty !"));
#endif
if (BX_IA_LAST > 0xffff)
if (BX_IA_LAST > 0xfff)
BX_PANIC(("init_FetchDecodeTables: too many opcodes defined !"));
for (unsigned n=0; n < BX_IA_LAST; n++) {

2
bochs/cpu/fetchdecode.h
View File

@ -63,6 +63,7 @@ BX_CPP_INLINE Bit64u FetchQWORD(const Bit8u *iptr)
#define BX_PREPARE_AVX (0x02)
#define BX_VEX_L128 (0x04) /* VEX.L128 allowed */
#define BX_VEX_L256 (0x08) /* VEX.L256 allowed */
#define BX_VEX_NO_VVV (0x10) /* no VEX.VVV allowed */
struct bxIAOpcodeTable {
BxExecutePtr_tR execute1;
@ -76,6 +77,7 @@ struct bxIAOpcodeTable {
#include "fetchdecode_x87.h"
#include "fetchdecode_sse.h"
#include "fetchdecode_avx.h"
/* ************************************************************************ */
/* Opcode Groups */

177
bochs/cpu/fetchdecode64.cc
View File

@ -335,8 +335,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* C1 /w */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2Ew },
/* C2 /w */ { BxImmediate_Iw | BxTraceEnd, BX_IA_RETnear64_Iw },
/* C3 /w */ { BxTraceEnd, BX_IA_RETnear64 },
/* C4 /w */ { 0, BX_IA_ERROR },
/* C5 /w */ { 0, BX_IA_ERROR },
/* C4 /w */ { BxPrefixVEX, BX_IA_ERROR },
/* C5 /w */ { BxPrefixVEX, BX_IA_ERROR },
/* C6 /w */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Eb },
/* C7 /w */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Ew },
/* C8 /w */ { BxImmediate_Iw | BxImmediate_Ib2, BX_IA_ENTER64_IwIb },
@ -850,8 +850,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* C1 /d */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2Ed },
/* C2 /d */ { BxImmediate_Iw | BxTraceEnd, BX_IA_RETnear64_Iw },
/* C3 /d */ { BxTraceEnd, BX_IA_RETnear64 },
/* C4 /d */ { 0, BX_IA_ERROR },
/* C5 /d */ { 0, BX_IA_ERROR },
/* C4 /d */ { BxPrefixVEX, BX_IA_ERROR },
/* C5 /d */ { BxPrefixVEX, BX_IA_ERROR },
/* C6 /d */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Eb },
/* C7 /d */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Ed },
/* C8 /d */ { BxImmediate_Iw | BxImmediate_Ib2, BX_IA_ENTER64_IwIb },
@ -1365,8 +1365,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* C1 /q */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfo64G2Eq },
/* C2 /q */ { BxImmediate_Iw | BxTraceEnd, BX_IA_RETnear64_Iw },
/* C3 /q */ { BxTraceEnd, BX_IA_RETnear64 },
/* C4 /q */ { 0, BX_IA_ERROR },
/* C5 /q */ { 0, BX_IA_ERROR },
/* C4 /q */ { BxPrefixVEX, BX_IA_ERROR },
/* C5 /q */ { BxPrefixVEX, BX_IA_ERROR },
/* C6 /q */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Eb },
/* C7 /q */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfo64G11Eq },
/* C8 /q */ { BxImmediate_Iw | BxImmediate_Ib2, BX_IA_ENTER64_IwIb },
@ -1690,7 +1690,8 @@ BX_CPU_C::fetchDecode64(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
if (remainingInPage > 15) remainingInPage = 15;
unsigned remain = remainingInPage; // remain must be at least 1
unsigned b1, b2 = 0, lock=0, ia_opcode = 0;
unsigned b1, b2 = 0, ia_opcode = 0;
bx_bool lock=0;
unsigned offset = 512, rex_r = 0, rex_x = 0, rex_b = 0;
unsigned rm = 0, mod = 0, nnn = 0, mod_mem = 0;
unsigned seg = BX_SEG_REG_DS, seg_override = BX_SEG_REG_NULL;
@ -1702,6 +1703,13 @@ BX_CPU_C::fetchDecode64(const Bit8u *iptr, bxInstruction_c *i, unsigned remainin
unsigned sse_prefix = SSE_PREFIX_NONE;
unsigned rex_prefix = 0;
int had_vex = 0;
#if BX_SUPPORT_AVX
int vvv = -1;
unsigned vex;
bx_bool vex_w = 0;
#endif
i->ResolveModrm = 0;
i->init(/*os32*/ 1, // operand size 32 override defaults to 1
/*as32*/ 1, // address size 32 override defaults to 1
@ -1808,12 +1816,75 @@ fetch_b1:
}
i->setB1(b1);
i->setVL(BX_NO_VL);
unsigned index = b1+offset;
unsigned attr = BxOpcodeInfo64[index].Attr;
bx_bool has_modrm = BxOpcodeHasModrm64[b1];
bx_bool has_modrm = 0;
#if BX_SUPPORT_AVX
if ((attr & BxGroupX) == BxPrefixVEX) {
had_vex = 1;
if (sse_prefix || rex_prefix) had_vex = -1;
unsigned vex_opcext = 1;
if (remain != 0) {
remain--;
vex = *iptr++;
}
else
return(-1);
rex_r = ((vex >> 4) & 0x8) ^ 0x8;
if (b1 == 0xc4) {
rex_x = ((vex >> 3) & 0x8) ^ 0x8;
rex_b = ((vex >> 2) & 0x8) ^ 0x8;
// decode 3-byte VEX prefix
vex_opcext = vex & 0x1f;
if (remain != 0) {
remain--;
vex = *iptr++; // fetch VEX3
}
else
return(-1);
if (vex & 0x80) {
vex_w = 1;
i->assertOs64();
i->assertOs32();
}
}
vvv = 15 - ((vex >> 3) & 0xf);
i->setVL(BX_VL128 + ((vex >> 2) & 0x1));
sse_prefix = vex & 0x3;
if (remain != 0) {
remain--;
b1 = *iptr++; // fetch new b1
}
else
return(-1);
b1 += 256 * vex_opcext;
if (b1 < 256 || b1 >= 1024) had_vex = -1;
else {
if (b1 >= 512)
has_modrm = 1;
else
has_modrm = BxOpcodeHasModrm64[b1];
}
}
else
#endif
{
has_modrm = BxOpcodeHasModrm64[b1];
}
if (has_modrm) {
@ -1841,12 +1912,18 @@ fetch_b1:
nnn = ((b2 >> 3) & 0x7) | rex_r;
rm = (b2 & 0x7) | rex_b;
i->setNnn(nnn);
#if BX_SUPPORT_AVX
if (had_vex == 0) vvv = nnn;
i->setVvv(vvv);
#endif
// MOVs with CRx and DRx always use register ops and ignore the mod field.
if ((b1 & ~3) == 0x120)
mod = 0xc0;
i->setModRM(b2);
i->setNnn(nnn);
if ((b1 & 0xff8) == 0xd8)
i->setModRM(b2);
if (mod == 0xc0) { // mod == 11b
i->setRm(rm);
@ -1985,7 +2062,17 @@ modrm_done:
// Resolve ExecutePtr and additional opcode Attr
const BxOpcodeInfo_t *OpcodeInfoPtr = &(BxOpcodeInfo64[index]);
attr = BxOpcodeInfo64[index].Attr;
#if BX_SUPPORT_AVX
if (had_vex != 0) {
if (had_vex < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
OpcodeInfoPtr = &BxOpcodeTableAVX[b1-256];
}
#endif
attr = OpcodeInfoPtr->Attr;
while(attr & BxGroupX) {
Bit32u group = attr & BxGroupX;
@ -2004,10 +2091,19 @@ modrm_done:
switch(group) {
case BxGroupN:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[nnn & 0x7]);
#if BX_SUPPORT_AVX
if (had_vex == 0) i->setVvv(rm);
#endif
break;
case BxSplitGroupN:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[(nnn & 0x7) + (mod_mem << 3)]);
break;
#if BX_SUPPORT_AVX
case BxSplitVexW:
BX_ASSERT(had_vex != 0);
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[vex_w]);
break;
#endif
case Bx3ByteOp:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[b3]);
break;
@ -2029,7 +2125,7 @@ modrm_done:
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[(b2 & 0x3f) + 8]);
break;
default:
BX_PANIC(("fetchdecode: Unknown opcode group"));
BX_PANIC(("fetchdecode: Unknown opcode group %d", group));
}
/* get additional attributes from group table */
@ -2046,12 +2142,21 @@ modrm_done:
const BxOpcodeInfo_t *OpcodeInfoPtr = &(BxOpcodeInfo64[index]);
#if BX_SUPPORT_AVX
if (had_vex != 0) {
i->setVvv(vvv);
if (had_vex < 0)
OpcodeInfoPtr = &BxOpcodeGroupSSE_ERR[0]; // BX_IA_ERROR
else
OpcodeInfoPtr = &BxOpcodeTableAVX[b1-256];
}
#endif
if (b1 == 0x90 && sse_prefix == SSE_PREFIX_F3) {
ia_opcode = BX_IA_PAUSE;
}
else {
unsigned group = attr & BxGroupX;
BX_ASSERT(group == BxPrefixSSE || group == 0);
if (group == BxPrefixSSE && sse_prefix)
OpcodeInfoPtr = &(OpcodeInfoPtr->AnotherArray[sse_prefix-1]);
@ -2158,6 +2263,17 @@ modrm_done:
else return(-1);
}
break;
#if BX_SUPPORT_AVX
case BxImmediate_Ib4:
if (remain != 0) {
i->modRMForm.Ib = (*iptr++) >> 4;
remain--;
}
else {
return(-1);
}
break;
#endif
default:
BX_INFO(("b1 was %x", b1));
BX_PANIC(("fetchdecode: imm_mode = %u", imm_mode));
@ -2193,6 +2309,33 @@ modrm_done:
i->setILen(remainingInPage - remain);
i->setIaOpcode(ia_opcode);
Bit32u op_flags = BxOpcodesTable[ia_opcode].flags;
if (! BX_CPU_THIS_PTR sse_ok) {
if (op_flags & BX_PREPARE_SSE) {
if (i->execute != &BX_CPU_C::BxError) i->execute = &BX_CPU_C::BxNoSSE;
return(1);
}
}
#if BX_SUPPORT_AVX
if (! BX_CPU_THIS_PTR avx_ok) {
if (op_flags & BX_PREPARE_AVX) {
if (i->execute != &BX_CPU_C::BxError) i->execute = &BX_CPU_C::BxNoAVX;
return(1);
}
}
if (had_vex > 0) {
if ((op_flags & BX_VEX_NO_VVV) && i->vvv() != 0) {
ia_opcode = BX_IA_ERROR;
}
if (i->getVL() == BX_VEX_L128 && !(op_flags & BX_VEX_L128)) {
ia_opcode = BX_IA_ERROR;
}
if (i->getVL() == BX_VEX_L256 && !(op_flags & BX_VEX_L256)) {
ia_opcode = BX_IA_ERROR;
}
}
#endif
if (mod_mem) {
i->execute = BxOpcodesTable[ia_opcode].execute1;
i->execute2 = BxOpcodesTable[ia_opcode].execute2;
@ -2209,14 +2352,6 @@ modrm_done:
BX_ASSERT(i->execute);
Bit32u op_flags = BxOpcodesTable[ia_opcode].flags;
if (! BX_CPU_THIS_PTR sse_ok) {
if (op_flags & BX_PREPARE_SSE) {
if (i->execute != &BX_CPU_C::BxError) i->execute = &BX_CPU_C::BxNoSSE;
return(1);
}
}
#if BX_SUPPORT_TRACE_CACHE
if ((attr & BxTraceEnd) || ia_opcode == BX_IA_ERROR)
return(1);

1274
bochs/cpu/fetchdecode_avx.h Normal file
View File

File diff suppressed because it is too large Load Diff

298
bochs/cpu/ia_opcodes.h
View File

@ -2,7 +2,7 @@
// $Id$,,,
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2010 Stanislav Shwartsman
// Copyright (c) 2008-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -1350,3 +1350,299 @@ bx_define_opcode(BX_IA_VMWRITE_GqEq, &BX_CPU_C::VMWRITE, &BX_CPU_C::VMWRITE, BX_
bx_define_opcode(BX_IA_INVEPT, &BX_CPU_C::INVEPT, &BX_CPU_C::BxError, BX_CPU_X86_64 | BX_CPU_VMX, 0)
bx_define_opcode(BX_IA_INVVPID, &BX_CPU_C::INVVPID, &BX_CPU_C::BxError, BX_CPU_X86_64 | BX_CPU_VMX, 0)
// VMX
// AVX
#if BX_SUPPORT_AVX
bx_define_opcode(BX_IA_VMOVUPD_VpdWpd, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVUPD_WpdVpd, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
bx_define_opcode(BX_IA_VMOVSD_VsdWsd, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::VMOVSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVSS_VssWss, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::VMOVSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVSD_WsdVsd, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::VMOVSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128) /* dstRM */
bx_define_opcode(BX_IA_VMOVSS_WssVss, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::VMOVSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128) /* dstRM */
bx_define_opcode(BX_IA_VMOVLPD_VpdMq, &BX_CPU_C::VMOVLPD_VpdMq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVLPD_MqVsd, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVSHDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSHDUP_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VUNPCKLPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VUNPCKHPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVHPD_VpdMq, &BX_CPU_C::VMOVHPD_VpdMq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVHPD_MqVsd, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVAPD_VpdWpd, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVAPD_WpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
bx_define_opcode(BX_IA_VMOVNTPD_MpdVpd, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VUCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCOMISD_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVMSKPS_GdVRps, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPS_GdVRps, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVMSKPD_GdVRpd, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPD_GdVRpd, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSQRTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSQRTPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSQRTSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSQRTSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSQRTSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VRSQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRSQRTSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VRSQRTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRSQRTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VRCPSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VRCPSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VRCPPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VRCPPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VANDPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VANDPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VANDNPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VANDNPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VORPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VORPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VXORPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VXORPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPD2DQ_VqWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTPD2DQ_VqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2DQ_VqWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTDQ2PD_VpdWq, &BX_CPU_C::LOAD_VectorQ, &BX_CPU_C::VCVTDQ2PD_VpdWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTPD2PS_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPD2PS_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSD2SS_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCVTSD2SS_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSS2SD_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCVTSS2SD_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTDQ2PS_VpsWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTDQ2PS_VpsWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTPS2DQ_VdqWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPS2DQ_VdqWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VADDSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VADDSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMULPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMULPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMULPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMULSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMULSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMULSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMULSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSUBPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSUBPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSUBPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSUBSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VSUBSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSUBSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VSUBSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VDIVPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VDIVPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDIVPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VDIVSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VDIVSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VDIVSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VDIVSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMAXPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMAXPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMAXPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMAXSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMAXSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMAXSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMAXSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMINPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMINPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMINPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMINSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMINSD_VsdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMINSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VMINSS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVDQA_VdqWdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVDQU_VdqWdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPSHUFD_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSHUFHW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSHUFHW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSHUFLW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSHUFLW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VHADDPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VHADDPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VHSUBPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VHSUBPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVQ_WqVq, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::MOVQ_VqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128) /* dstRM */
bx_define_opcode(BX_IA_VMOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVDQA_WdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVDQU_WdqVdq, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
bx_define_opcode(BX_IA_VCMPPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCMPPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCMPPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCMPSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VCMPSD_VsdWsdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCMPSS_VssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VCMPSS_VssWssIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VSHUFPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDSUBPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VADDSUBPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPSRLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRAW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLW_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLW_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLD_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRAD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAD_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLD_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLD_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLDQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLDQ_UdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VLDMXCSR, &BX_CPU_C::LDMXCSR, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VSTMXCSR, &BX_CPU_C::STMXCSR, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVUPS_VpsWps, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVUPS_WpsVps, &BX_CPU_C::VMOVUPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
bx_define_opcode(BX_IA_VMOVLPS_VpsMq, &BX_CPU_C::VMOVLPD_VpdMq, &BX_CPU_C::VMOVHLPS_VpsWps, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVHPS_VpsMq, &BX_CPU_C::VMOVHPD_VpdMq, &BX_CPU_C::VMOVLHPS_VpsWps, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVLPS_MqVps, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVHPS_MqVps, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VUNPCKLPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VUNPCKHPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVAPS_VpsWps, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMOVAPS_WpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::VMOVAPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256) /* dstRM */
bx_define_opcode(BX_IA_VMOVNTPS_MpsVps, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VUCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCOMISS_VpsWps, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTPS2PD_VpsWps, &BX_CPU_C::LOAD_VectorQ, &BX_CPU_C::VCVTPS2PD_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPUNPCKHDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKLDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPACKSSWB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKSSWB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPGTB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPGTB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPGTW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPGTW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPGTD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPGTD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPGTQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPGTQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPACKUSWB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKUSWB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKLBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPCKLBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKLWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPCKLWD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKHBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPCKHBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKHWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PUNPCKHWD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPACKUSDW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKUSDW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKLQDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPUNPCKHQDQ_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPEQB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPEQW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPEQD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPEQQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPEQQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VZEROUPPER, NULL, &BX_CPU_C::VZEROUPPER, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::PINSRW_VdqEwIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VSHUFPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPSRLW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRLQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRLQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULLW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULLW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBUSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBUSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBUSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBUSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDUSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDUSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDUSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDUSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPAVGB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PAVGB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPAVGW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PAVGW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRAW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSRAD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSRAD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULHUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULHUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULHW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULHW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVNTDQ_MdqVdq, &BX_CPU_C::VMOVAPS_WpsVpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPSUBSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPANDN_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDNPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPAND_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VANDPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPOR_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPXOR_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VXORPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VLDDQU_VdqMdq, &BX_CPU_C::VMOVUPS_VpsWpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPSLLW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSLLQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSLLQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULUDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULUDQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMADDWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMADDWD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSADBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSADBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVDQU_VdqUdq, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSUBQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSUBQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPADDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PADDQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSHUFB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSHUFB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHADDW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHADDW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHADDD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHADDD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHADDSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHADDSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMADDUBSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMADDUBSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHSUBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHSUBW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHSUBD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHSUBD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHSUBSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHSUBSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSIGNB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSIGNB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSIGNW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSIGNW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPSIGND_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PSIGND_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULHRSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULHRSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VTESTPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VTESTPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VTESTPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPTEST_VdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPTEST_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VBROADCASTSS_VpsMss, &BX_CPU_C::VBROADCASTSS_VpsMss, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VBROADCASTSD_VpdMsd, &BX_CPU_C::VBROADCASTSD_VpdMsd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L256)
bx_define_opcode(BX_IA_VBROADCASTF128_VdqMdq, &BX_CPU_C::VBROADCASTF128_VdqMdq, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L256)
bx_define_opcode(BX_IA_VPABSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PABSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPABSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PABSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPABSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PABSD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULDQ_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVNTDQA_VdqMdq, &BX_CPU_C::VMOVAPS_VpsWpsM, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPACKSSDW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PACKSSDW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMASKMOVPS_VpsMps, &BX_CPU_C::VMASKMOVPS_VpsMps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMASKMOVPD_VpdMpd, &BX_CPU_C::VMASKMOVPD_VpdMpd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMASKMOVPS_MpsVps, &BX_CPU_C::VMASKMOVPS_MpsVps, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VMASKMOVPD_MpdVpd, &BX_CPU_C::VMASKMOVPD_MpdVpd, &BX_CPU_C::BxError, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPMOVSXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXBW_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVSXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXBD_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVSXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVSXBQ_VdqWwR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVSXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXWD_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVSXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVSXWQ_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVSXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVSXDQ_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXBW_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXBW_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXBD_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXBD_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXBQ_VdqWw, &BX_CPU_C::LOAD_Ww, &BX_CPU_C::PMOVZXBQ_VdqWwR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXWD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXWD_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXWQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::PMOVZXWQ_VdqWdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMOVZXDQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::PMOVZXDQ_VdqWqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINSD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINUB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINUB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMINUD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMINUD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXSB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXSB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXSW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXSW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXSD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXSD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXUB_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXUB_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMAXUD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMAXUD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPMULLD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PMULLD_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPHMINPOSUW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPERMILPS_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPERMILPD_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdWpdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPERMILPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPERMILPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMILPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPERM2F128_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L256)
bx_define_opcode(BX_IA_VROUNDPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VROUNDPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VROUNDPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VROUNDSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VROUNDSD_VsdWsdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VROUNDSS_VssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VROUNDSS_VssWssIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VBLENDPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VBLENDPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPBLENDW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PBLENDW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPALIGNR_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PALIGNR_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, &BX_CPU_C::PEXTRB_EbdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_CPU_C::PEXTRW_EwdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VINSERTF128_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L256)
bx_define_opcode(BX_IA_VEXTRACTF128_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L256)
bx_define_opcode(BX_IA_VPINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqEbIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsWssIb, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VDPPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VDPPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VDPPD_VpdWpdIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::DPPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMPSADBW_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::MPSADBW_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VBLENDVPS_VpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPS_VpsWpsIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VBLENDVPD_VpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VBLENDVPD_VpdWpdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPBLENDVB_VdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPBLENDVB_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPESTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPESTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPISTRM_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCMPISTRI_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESIMC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESENC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESENC_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESENCLAST_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESENCLAST_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESDEC_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESDEC_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESDECLAST_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESDECLAST_VdqWdqR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VAESKEYGENASSIST_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPCLMULQDQ_VdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCLMULQDQ_VdqWdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVD_VdqEd, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVD_VdqEdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPINSRD_VdqEdIb, &BX_CPU_C::PINSRD_VdqEdIbM, &BX_CPU_C::PINSRD_VdqEdIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VPEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VCVTSI2SD_VsdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTSI2SD_VsdEdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSI2SS_VssEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VCVTSI2SS_VssEdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_CPU_AVX, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSI2SD_VsdEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTSI2SD_VsdEqR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSI2SS_VssEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VCVTSI2SS_VssEqR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GqWsdR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128 | BX_VEX_L256)
bx_define_opcode(BX_IA_VPEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_NO_VVV | BX_VEX_L128)
bx_define_opcode(BX_IA_VPINSRQ_VdqEqIb, &BX_CPU_C::PINSRD_VdqEdIbM, &BX_CPU_C::PINSRD_VdqEdIbR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVQ_VdqEq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VdqEqR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_L128)
bx_define_opcode(BX_IA_VMOVQ_EqVq, &BX_CPU_C::MOVLPS_MqVps, &BX_CPU_C::MOVQ_EqVqR, BX_CPU_AVX | BX_CPU_X86_64, BX_PREPARE_AVX | BX_VEX_L128)
#endif
// AVX

33
bochs/cpu/init.cc
View File

@ -528,13 +528,17 @@ void BX_CPU_C::register_state(void)
#if BX_CPU_LEVEL >= 6
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE)) {
bx_list_c *sse = new bx_list_c(cpu, "SSE", 2*BX_XMM_REGISTERS+1);
bx_list_c *sse = new bx_list_c(cpu, "SSE", BX_VLMAX*2*BX_XMM_REGISTERS+1);
BXRS_HEX_PARAM_FIELD(sse, mxcsr, mxcsr.mxcsr);
for (n=0; n<BX_XMM_REGISTERS; n++) {
sprintf(name, "xmm%02d_1", n);
new bx_shadow_num_c(sse, name, &xmm[n].xmm64u(1), BASE_HEX);
sprintf(name, "xmm%02d_0", n);
new bx_shadow_num_c(sse, name, &xmm[n].xmm64u(0), BASE_HEX);
for(unsigned j=0;j < BX_VLMAX*2;j++) {
sprintf(name, "xmm%02d_%d", n, j);
#if BX_SUPPORT_AVX
new bx_shadow_num_c(sse, name, &vmm[n].avx64u(j), BASE_HEX);
#else
new bx_shadow_num_c(sse, name, &vmm[n].xmm64u(j), BASE_HEX);
#endif
}
}
}
#endif
@ -694,6 +698,9 @@ void BX_CPU_C::after_restore_state(void)
handleCpuModeChange();
#if BX_CPU_LEVEL >= 6
handleSseModeChange();
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
#endif
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_IA32_REAL) CPL = 0;
@ -901,6 +908,11 @@ void BX_CPU_C::reset(unsigned source)
#if BX_CPU_LEVEL >= 6
BX_CPU_THIS_PTR xcr0.set32(0x1);
BX_CPU_THIS_PTR xcr0_suppmask = 0x3;
#if BX_SUPPORT_AVX
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_AVX))
BX_CPU_THIS_PTR xcr0_suppmask |= BX_XCR0_AVX_MASK;
#endif
#endif
/* initialise MSR registers to defaults */
@ -994,17 +1006,18 @@ void BX_CPU_C::reset(unsigned source)
#if BX_CPU_LEVEL >= 6
BX_CPU_THIS_PTR sse_ok = 0;
#if BX_SUPPORT_AVX
BX_CPU_THIS_PTR avx_ok = 0;
#endif
// Reset XMM state - unchanged on #INIT
if (source == BX_RESET_HARDWARE) {
static BxPackedXmmRegister xmmnil; /* compiler will clear the variable */
for(n=0; n<BX_XMM_REGISTERS; n++)
{
BX_CPU_THIS_PTR xmm[n].xmm64u(0) = 0;
BX_CPU_THIS_PTR xmm[n].xmm64u(1) = 0;
}
BX_WRITE_XMM_REG_CLEAR_HIGH(n, xmmnil);
BX_CPU_THIS_PTR mxcsr.mxcsr = MXCSR_RESET;
BX_CPU_THIS_PTR mxcsr_mask = 0x0000FFBF;
BX_CPU_THIS_PTR mxcsr_mask = 0x0000ffbf;
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE2))
BX_CPU_THIS_PTR mxcsr_mask |= MXCSR_DAZ;
if (BX_SUPPORT_MISALIGNED_SSE)

26
bochs/cpu/instr.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2010 Stanislav Shwartsman
// Copyright (c) 2008-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -50,7 +50,8 @@ public:
BxResolvePtr_tR ResolveModrm;
struct {
// 15..0 opcode
// 15.12 AVX vl (0=no VL, 1=128 bit, 2=256 bit)
// 11..0 opcode
Bit16u ia_opcode;
// 7...4 (unused)
@ -74,7 +75,8 @@ public:
#define BX_INSTR_METADATA_BASE 4
#define BX_INSTR_METADATA_INDEX 5
#define BX_INSTR_METADATA_SCALE 6
#define BX_INSTR_METADATA_MODRM 7
#define BX_INSTR_METADATA_MODRM 7 /* modrm for FPU only */
#define BX_INSTR_METADATA_VVV 7
// using 5-bit field for registers (16 regs in 64-bit, RIP, NIL)
Bit8u metaData[8];
@ -237,10 +239,10 @@ public:
}
BX_CPP_INLINE unsigned getIaOpcode(void) const {
return metaInfo.ia_opcode;
return metaInfo.ia_opcode & 0xfff;
}
BX_CPP_INLINE void setIaOpcode(Bit16u op) {
metaInfo.ia_opcode = op;
metaInfo.ia_opcode = (metaInfo.ia_opcode & 0xf000) | op;
}
BX_CPP_INLINE unsigned repUsedL(void) const {
@ -253,6 +255,20 @@ public:
metaInfo.metaInfo1 = (metaInfo.metaInfo1 & 0x3f) | (value << 6);
}
BX_CPP_INLINE unsigned getVL(void) const {
return metaInfo.ia_opcode >> 12;
}
BX_CPP_INLINE void setVL(unsigned value) {
metaInfo.ia_opcode = (metaInfo.ia_opcode & 0xfff) | (value << 12);
}
BX_CPP_INLINE void setVvv(unsigned vvv) {
metaData[BX_INSTR_METADATA_VVV] = vvv;
}
BX_CPP_INLINE unsigned vvv() const {
return metaData[BX_INSTR_METADATA_VVV];
}
BX_CPP_INLINE unsigned modC0() const
{
// This is a cheaper way to test for modRM instructions where

35
bochs/cpu/load.cc
View File

@ -92,17 +92,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wsd(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wdq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
#if BX_SUPPORT_MISALIGNED_SSE
if (BX_CPU_THIS_PTR mxcsr.get_MM())
read_virtual_dqword(i->seg(), eaddr, &op);
read_virtual_dqword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_TMP_REGISTER));
else
#endif
read_virtual_dqword_aligned(i->seg(), eaddr, &op);
BX_WRITE_XMM_REG(BX_TMP_REGISTER, op);
read_virtual_dqword_aligned(i->seg(), eaddr, &BX_READ_XMM_REG(BX_TMP_REGISTER));
BX_CPU_CALL_METHOD(i->execute2, (i));
#endif
@ -111,11 +108,33 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wdq(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOADU_Wdq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
read_virtual_dqword(i->seg(), eaddr, &op);
BX_WRITE_XMM_REG(BX_TMP_REGISTER, op);
read_virtual_dqword(i->seg(), eaddr, &BX_READ_XMM_REG(BX_TMP_REGISTER));
BX_CPU_CALL_METHOD(i->execute2, (i));
#endif
}
#if BX_SUPPORT_AVX
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Vector(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
read_virtual_vector(i->seg(), eaddr, i->getVL() << 2, &BX_READ_AVX_REG(BX_TMP_REGISTER));
BX_CPU_CALL_METHOD(i->execute2, (i));
#endif
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_VectorQ(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
read_virtual_vector(i->seg(), eaddr, i->getVL() << 1, &BX_READ_AVX_REG(BX_TMP_REGISTER));
BX_CPU_CALL_METHOD(i->execute2, (i));
#endif
}
#endif

40
bochs/cpu/proc_ctrl.cc
View File

@ -261,6 +261,12 @@ void BX_CPU_C::handleCpuModeChange(void)
updateFetchModeMask();
#if BX_CPU_LEVEL >= 6
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
#endif
if (mode != BX_CPU_THIS_PTR cpu_mode) {
BX_DEBUG(("%s activated", cpu_mode_string(BX_CPU_THIS_PTR cpu_mode)));
#if BX_DEBUGGER
@ -313,7 +319,41 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BxNoSSE(bxInstruction_c *i)
if(BX_CPU_THIS_PTR cr0.get_TS())
exception(BX_NM_EXCEPTION, 0);
BX_ASSERT(0);
}
#if BX_SUPPORT_AVX
void BX_CPU_C::handleAvxModeChange(void)
{
if(BX_CPU_THIS_PTR cr0.get_TS()) {
BX_CPU_THIS_PTR avx_ok = 0;
}
else {
if (! protected_mode() || ! BX_CPU_THIS_PTR cr4.get_OSXSAVE() ||
(~BX_CPU_THIS_PTR xcr0.val32 & 0x6) != 0) BX_CPU_THIS_PTR avx_ok = 0;
else
BX_CPU_THIS_PTR avx_ok = 1;
}
updateFetchModeMask(); /* AVX_OK changed */
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::BxNoAVX(bxInstruction_c *i)
{
if (! protected_mode() || ! BX_CPU_THIS_PTR cr4.get_OSXSAVE())
exception(BX_UD_EXCEPTION, 0);
if (~BX_CPU_THIS_PTR xcr0.val32 & 0x6)
exception(BX_UD_EXCEPTION, 0);
if(BX_CPU_THIS_PTR cr0.get_TS())
exception(BX_NM_EXCEPTION, 0);
BX_ASSERT(0);
}
#endif
#endif
void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPMC(bxInstruction_c *i)

6
bochs/cpu/smm.cc
View File

@ -215,6 +215,9 @@ void BX_CPU_C::enter_system_management_mode(void)
#if BX_CPU_LEVEL >= 6
handleSseModeChange();
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
#endif
/* DS (Data Segment) and descriptor cache */
@ -656,6 +659,9 @@ bx_bool BX_CPU_C::smram_restore_state(const Bit32u *saved_state)
#if BX_CPU_LEVEL >= 6
handleSseModeChange();
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
#endif
Bit16u ar_data = SMRAM_FIELD(saved_state, SMRAM_FIELD_LDTR_SELECTOR_AR) >> 16;

530
bochs/cpu/sse.cc
View File

File diff suppressed because it is too large Load Diff

41
bochs/cpu/sse_move.cc
View File

@ -465,8 +465,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWssM(bxInstruction_c *i)
op.xmm64u(0) = (Bit64u) read_virtual_dword(i->seg(), eaddr);
op.xmm64u(1) = 0;
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
#endif
}
@ -662,7 +661,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_VdqEdR(bxInstruction_c *i)
op.xmm64u(0) = (Bit64u) BX_READ_32BIT_REG(i->rm());
op.xmm64u(1) = 0;
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
#endif
}
@ -676,7 +675,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VdqEqR(bxInstruction_c *i)
op.xmm64u(0) = BX_READ_64BIT_REG(i->rm());
op.xmm64u(1) = 0;
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
#endif
}
@ -711,7 +710,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqR(bxInstruction_c *i)
op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->rm());
op.xmm64u(1) = 0; /* zero-extension to 128 bit */
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
#endif
}
@ -723,8 +722,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqM(bxInstruction_c *i)
op.xmm64u(0) = read_virtual_qword(i->seg(), eaddr);
op.xmm64u(1) = 0; /* zero-extension to 128 bit */
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), op);
BX_WRITE_XMM_REGZ(i->nnn(), op, i->getVL());
#endif
}
@ -838,7 +836,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBW_VdqWqR(bxInstruction_c *i)
result.xmm16u(7) = MMXSB7(op);
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -855,7 +853,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBD_VdqWdR(bxInstruction_c *i)
result.xmm32u(3) = (Bit8s) (val32 >> 24);
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -870,7 +868,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBQ_VdqWwR(bxInstruction_c *i)
result.xmm64u(1) = (Bit8s) (val16 >> 8);
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -887,7 +885,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWD_VdqWqR(bxInstruction_c *i)
result.xmm32u(3) = (Bit16s) (val64 >> 48);
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -902,7 +900,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWQ_VdqWdR(bxInstruction_c *i)
result.xmm64u(1) = (Bit16s) (val32 >> 16);
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -917,7 +915,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXDQ_VdqWqR(bxInstruction_c *i)
result.xmm64u(1) = (Bit32s) (val64 >> 32);
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -941,7 +939,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBW_VdqWqR(bxInstruction_c *i)
result.xmm16u(7) = MMXUB7(op);
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -958,7 +956,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBD_VdqWdR(bxInstruction_c *i)
result.xmm32u(3) = val32 >> 24;
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -973,7 +971,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBQ_VdqWwR(bxInstruction_c *i)
result.xmm64u(1) = val16 >> 8;
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -990,7 +988,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWD_VdqWqR(bxInstruction_c *i)
result.xmm32u(3) = val64 >> 48;
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -1005,7 +1003,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWQ_VdqWdR(bxInstruction_c *i)
result.xmm64u(1) = val32 >> 16;
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -1020,7 +1018,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXDQ_VdqWqR(bxInstruction_c *i)
result.xmm64u(1) = val64 >> 32;
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}
@ -1028,7 +1026,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXDQ_VdqWqR(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_VdqWdqIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm()), result;
unsigned shift = i->Ib() * 8;
@ -1068,7 +1066,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_VdqWdqIbR(bxInstruction_c *i)
result.xmm64u(1) = 0;
}
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REGZ(i->nnn(), result, i->getVL());
#endif
}

7
bochs/cpu/sse_pfp.cc
View File

@ -48,7 +48,7 @@ void BX_CPU_C::check_exceptionsSSE(int exceptions_flags)
}
}
BX_CPP_INLINE void mxcsr_to_softfloat_status_word(float_status_t &status, bx_mxcsr_t mxcsr)
void mxcsr_to_softfloat_status_word(float_status_t &status, bx_mxcsr_t mxcsr)
{
status.float_exception_flags = 0; // clear exceptions before execution
status.float_nan_handling_mode = float_first_operand_nan;
@ -2175,6 +2175,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDSD_VsdWsdIbR(bxInstruction_c *i)
#endif
}
/* Opcode: 66 0F 3A 40
* Selectively multiply packed SP floating-point values from xmm1 with
* packed SP floating-point values from xmm2, add and selectively
@ -2237,7 +2238,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DPPS_VpsWpsIbR(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::DPPD_VpdWpdIbR(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn());
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->vvv());
BxPackedXmmRegister op2 = BX_READ_XMM_REG(i->rm()), tmp;
Bit8u mask = i->Ib();
@ -2267,6 +2268,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DPPD_VpdWpdIbR(bxInstruction_c *i)
if (mask & 0x02) op1.xmm64u(1) = result;
check_exceptionsSSE(status_word.float_exception_flags);
BX_WRITE_XMM_REG(i->nnn(), op1);
BX_WRITE_XMM_REGZ(i->nnn(), op1, i->getVL());
#endif
}

6
bochs/cpu/sse_rcp.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2010 Stanislav Shwartsman
// Copyright (c) 2003-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -295,7 +295,7 @@ static Bit16u rcp_table[2048] = {
};
// approximate reciprocal of scalar single precision FP
static float32 approximate_rcp(float32 op)
float32 approximate_rcp(float32 op)
{
float_class_t op_class = float32_class(op);
@ -640,7 +640,7 @@ Bit16u rsqrt_table1[1024] =
// approximate reciprocal sqrt of scalar single precision FP
static float32 approximate_rsqrt(float32 op)
float32 approximate_rsqrt(float32 op)
{
float_class_t op_class = float32_class(op);

6
bochs/cpu/sse_string.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007-2010 Stanislav Shwartsman
// Copyright (c) 2007-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -340,7 +340,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRM_VdqWdqIbR(bxInstruction_c *i)
flags |= EFlagsOFMask;
setEFlagsOSZAPC(flags);
BX_WRITE_XMM_REG(0, result); /* store result XMM0 */
BX_WRITE_XMM_REGZ(0, result, i->getVL()); /* store result XMM0 */
#endif
}
@ -438,7 +438,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRM_VdqWdqIbR(bxInstruction_c *i)
flags |= EFlagsOFMask;
setEFlagsOSZAPC(flags);
BX_WRITE_XMM_REG(0, result); /* store result XMM0 */
BX_WRITE_XMM_REGZ(0, result, i->getVL()); /* store result XMM0 */
#endif
}

3
bochs/cpu/tasking.cc
View File

@ -683,6 +683,9 @@ void BX_CPU_C::task_switch(bxInstruction_c *i, bx_selector_t *tss_selector,
#if BX_CPU_LEVEL >= 6
handleSseModeChange(); /* CR0.TS changes */
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
#endif
//

4
bochs/cpu/todo
View File

@ -42,11 +42,11 @@ TODO (know issues in CPU model):
Currently Bochs emulation is according to Intel version.
Do we need to support both ?
[!] More flexible CPUID - vendor and etc
[!] More flexible CPUID
[!] VMX:
- Dual-monitor treatment of SMIs and SMM not implemented yet
- VMENTER to not-active state not supported yet
[!] SSE4A, SMX, SVM, AVX
[!] SSE4A, SMX, SVM, XOP

6
bochs/cpu/vmx.cc
View File

@ -1584,6 +1584,9 @@ Bit32u BX_CPU_C::VMenterLoadCheckGuestState(Bit64u *qualification)
#endif
handleCpuModeChange();
handleSseModeChange();
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
return VMXERR_NO_ERROR;
}
@ -2029,6 +2032,9 @@ void BX_CPU_C::VMexitLoadHostState(void)
#endif
handleCpuModeChange();
handleSseModeChange();
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
}
void BX_CPU_C::VMexit(bxInstruction_c *i, Bit32u reason, Bit64u qualification)

135
bochs/cpu/xmm.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2010 Stanislav Shwartsman
// Copyright (c) 2003-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -57,30 +57,91 @@ typedef union bx_xmm_reg_t {
#define xmm64u(i) xmm_u64[(i)]
#endif
/* AVX REGISTER */
enum bx_avx_vector_length {
BX_NO_VL,
BX_VL128,
BX_VL256
};
#if BX_SUPPORT_AVX
#define BX_VLMAX BX_VL256
#else
#define BX_VLMAX BX_VL128
#endif
#if BX_SUPPORT_AVX
typedef union bx_avx_reg_t {
Bit8s avx_sbyte[32];
Bit16s avx_s16[16];
Bit32s avx_s32[8];
Bit64s avx_s64[4];
Bit8u avx_ubyte[32];
Bit16u avx_u16[16];
Bit32u avx_u32[8];
Bit64u avx_u64[4];
BxPackedXmmRegister avx_v128[2];
} BxPackedAvxRegister;
#ifdef BX_BIG_ENDIAN
#define avx64s(i) avx_s64[3 - (i)]
#define avx32s(i) avx_s32[7 - (i)]
#define avx16s(i) avx_s16[15 - (i)]
#define avxsbyte(i) avx_sbyte[31 - (i)]
#define avxubyte(i) avx_ubyte[31 - (i)]
#define avx16u(i) avx_u16[15 - (i)]
#define avx32u(i) avx_u32[7 - (i)]
#define avx64u(i) avx_u64[3 - (i)]
#define avx128(i) avx_v128[1 - (i)]
#else
#define avx64s(i) avx_s64[(i)]
#define avx32s(i) avx_s32[(i)]
#define avx16s(i) avx_s16[(i)]
#define avxsbyte(i) avx_sbyte[(i)]
#define avxubyte(i) avx_ubyte[(i)]
#define avx16u(i) avx_u16[(i)]
#define avx32u(i) avx_u32[(i)]
#define avx64u(i) avx_u64[(i)]
#define avx128(i) avx_v128[(i)]
#endif
#endif
#if BX_SUPPORT_X86_64
# define BX_XMM_REGISTERS 16
#else
# define BX_XMM_REGISTERS 8
#endif
#if BX_SUPPORT_AVX
/* read XMM register */
#define BX_READ_XMM_REG(index) (BX_CPU_THIS_PTR xmm[index])
#define BX_READ_XMM_REG(index) ((BX_CPU_THIS_PTR vmm[index]).avx128(0))
#else
/* read XMM register */
#define BX_READ_XMM_REG(index) ((BX_CPU_THIS_PTR vmm[index]))
#endif
/* read only high 64 bit of the register */
#define BX_READ_XMM_REG_HI_QWORD(index) \
((BX_CPU_THIS_PTR xmm[index]).xmm64u(1))
((BX_READ_XMM_REG(index)).xmm64u(1))
/* read only low 64 bit of the register */
#define BX_READ_XMM_REG_LO_QWORD(index) \
((BX_CPU_THIS_PTR xmm[index]).xmm64u(0))
((BX_READ_XMM_REG(index)).xmm64u(0))
/* read only low 32 bit of the register */
#define BX_READ_XMM_REG_LO_DWORD(index) \
((BX_CPU_THIS_PTR xmm[index]).xmm32u(0))
((BX_READ_XMM_REG(index)).xmm32u(0))
/* read only low 16 bit of the register */
#define BX_READ_XMM_REG_LO_WORD(index) \
((BX_CPU_THIS_PTR xmm[index]).xmm16u(0))
((BX_READ_XMM_REG(index)).xmm16u(0))
/* short names for above macroses */
#define BX_XMM_REG_HI_QWORD BX_READ_XMM_REG_HI_QWORD
@ -89,26 +150,72 @@ typedef union bx_xmm_reg_t {
#define BX_XMM_REG BX_READ_XMM_REG
/* store XMM register */
#define BX_WRITE_XMM_REG(index, reg) \
{ BX_CPU_THIS_PTR xmm[index] = (reg); }
/* store only high 64 bit of the register, rest of the register unchanged */
#define BX_WRITE_XMM_REG_HI_QWORD(index, reg64) \
{ (BX_CPU_THIS_PTR xmm[index]).xmm64u(1) = (reg64); }
{ (BX_XMM_REG(index)).xmm64u(1) = (reg64); }
/* store only low 64 bit of the register, rest of the register unchanged */
#define BX_WRITE_XMM_REG_LO_QWORD(index, reg64) \
{ (BX_CPU_THIS_PTR xmm[index]).xmm64u(0) = (reg64); }
{ (BX_XMM_REG(index)).xmm64u(0) = (reg64); }
/* store only low 32 bit of the register, rest of the register unchanged */
#define BX_WRITE_XMM_REG_LO_DWORD(index, reg32) \
{ (BX_CPU_THIS_PTR xmm[index]).xmm32u(0) = (reg32); }
{ (BX_XMM_REG(index)).xmm32u(0) = (reg32); }
/* store only low 16 bit of the register, rest of the register unchanged */
#define BX_WRITE_XMM_REG_LO_WORD(index, reg16) \
{ (BX_CPU_THIS_PTR xmm[index]).xmm16u(0) = (reg16); }
{ (BX_XMM_REG(index)).xmm16u(0) = (reg16); }
/* store only low 16 bit of the register, rest of the register unchanged */
#define BX_WRITE_XMM_REG_LO_WORD(index, reg16) \
{ (BX_XMM_REG(index)).xmm16u(0) = (reg16); }
/* store XMM register */
#define BX_WRITE_XMM_REG(index, reg) \
{ (BX_XMM_REG(index)) = (reg); }
#if BX_SUPPORT_AVX
/* read AVX register */
#define BX_READ_AVX_REG(index) (BX_CPU_THIS_PTR vmm[index])
/* read AVX register */
#define BX_READ_AVX_REG_LINE(index, line) \
((BX_READ_AVX_REG(index)).avx128(line))
/* write AVX register */
#define BX_WRITE_AVX_REG(index, reg) \
{ (BX_READ_AVX_REG(index)) = (reg); }
/* clear upper part of AVX register */
#define BX_CLEAR_AVX_HIGH(index) \
{ (BX_READ_AVX_REG(index)).avx64u(2) = (BX_READ_AVX_REG(index)).avx64u(3) = 0; }
/* write AVX register and potentialy clear upper part of the register */
#define BX_WRITE_AVX_REGZ(index, reg, vlen) \
{ BX_CPU_THIS_PTR vmm[index] = (reg); \
if (vlen == BX_VL128) BX_CLEAR_AVX_HIGH(index); }
/* write XMM register while clearing upper part of AVX register */
#define BX_WRITE_XMM_REG_CLEAR_HIGH(index, reg) \
{ BX_XMM_REG(index) = (reg); BX_CLEAR_AVX_HIGH(index); }
/* write XMM register while clearing upper part of AVX register */
#define BX_WRITE_XMM_REGZ(index, reg, vlen) \
{ (BX_XMM_REG(index)) = (reg); \
if (vlen == BX_VL128) BX_CLEAR_AVX_HIGH(index); }
#else
/* write XMM register while clearing upper part of AVX register */
#define BX_WRITE_XMM_REG_CLEAR_HIGH(index, reg) \
BX_WRITE_XMM_REG(index, reg)
/* write XMM register while clearing upper part of AVX register */
#define BX_WRITE_XMM_REGZ(index, reg, vlen) \
BX_WRITE_XMM_REG(index, reg)
#endif
/* MXCSR REGISTER */

58
bochs/cpu/xsave.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2009 Stanislav Shwartsman
// Copyright (c) 2008-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -149,6 +149,24 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XSAVE(bxInstruction_c *i)
header1 |= BX_XCR0_SSE_MASK;
}
#if BX_SUPPORT_AVX
/////////////////////////////////////////////////////////////////////////////
if (BX_CPU_THIS_PTR xcr0.get_AVX() && (EAX & BX_XCR0_AVX_MASK) != 0)
{
/* store AVX state */
for(index=0; index < BX_XMM_REGISTERS; index++)
{
// save YMM8-YMM15 only in 64-bit mode
if (index < 8 || long64_mode()) {
write_virtual_dqword(i->seg(),
(eaddr+index*16+576) & asize_mask, (Bit8u *)(&BX_READ_AVX_REG_LINE(index, 1)));
}
}
header1 |= BX_XCR0_AVX_MASK;
}
#endif
// always update header to 'dirty' state
write_virtual_qword(i->seg(), (eaddr + 512) & asize_mask, header1);
#endif
@ -274,6 +292,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XRSTOR(bxInstruction_c *i)
}
}
static BxPackedXmmRegister xmmnil; /* compiler will clear the variable */
/////////////////////////////////////////////////////////////////////////////
if (BX_CPU_THIS_PTR xcr0.get_SSE() && (EAX & BX_XCR0_SSE_MASK) != 0)
{
@ -297,14 +317,40 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XRSTOR(bxInstruction_c *i)
// initialize SSE with reset values
for(index=0; index < BX_XMM_REGISTERS; index++) {
// set XMM8-XMM15 only in 64-bit mode
if (index < 8 || long64_mode())
BX_WRITE_XMM_REG(index, xmmnil);
}
}
}
#if BX_SUPPORT_AVX
/////////////////////////////////////////////////////////////////////////////
if (BX_CPU_THIS_PTR xcr0.get_AVX() && (EAX & BX_XCR0_AVX_MASK) != 0)
{
if (header1 & BX_XCR0_AVX_MASK) {
// load AVX state from XSAVE area
for(index=0; index < BX_XMM_REGISTERS; index++)
{
// restore YMM8-YMM15 only in 64-bit mode
if (index < 8 || long64_mode()) {
BX_CPU_THIS_PTR xmm[index].xmm64u(0) = 0;
BX_CPU_THIS_PTR xmm[index].xmm64u(1) = 0;
read_virtual_dqword(i->seg(),
(eaddr+index*16+576) & asize_mask, (Bit8u *)(&BX_READ_AVX_REG_LINE(index, 1)));
}
}
}
else {
// initialize upper part of AVX registers with reset values
for(index=0; index < BX_XMM_REGISTERS; index++) {
// set YMM8-YMM15 only in 64-bit mode
if (index < 8 || long64_mode()) {
for (int j=2;j < BX_VLMAX*2;j++)
BX_CPU_THIS_PTR vmm[index].avx64u(j) = 0;
}
}
}
}
#endif
#endif
}
/* 0F 01 D0 */
@ -349,11 +395,15 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XSETBV(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}
if (EDX != 0 || (EAX & ~BX_XCR0_SUPPORTED_BITS) != 0 || (EAX & 1) == 0) {
if (EDX != 0 || (EAX & ~BX_CPU_THIS_PTR xcr0_suppmask) != 0 || (EAX & 1) == 0) {
BX_ERROR(("XSETBV: Attempting to change reserved bits!"));
exception(BX_GP_EXCEPTION, 0);
}
BX_CPU_THIS_PTR xcr0.set32(EAX);
#if BX_SUPPORT_AVX
handleAvxModeChange();
#endif
#endif
}

2
bochs/disasm/Makefile.in
View File

@ -75,7 +75,7 @@ dist-clean: clean
# dependencies generated by
# gcc -MM -I.. -I../instrument/stubs *.cc | sed 's/\.cc/.@CPP_SUFFIX@/g'
###########################################
dis_decode.o: dis_decode.@CPP_SUFFIX@ disasm.h ../config.h dis_tables.h opcodes.inc dis_tables.inc dis_tables_x87.inc dis_tables_sse.inc
dis_decode.o: dis_decode.@CPP_SUFFIX@ disasm.h ../config.h dis_tables.h opcodes.inc dis_tables.inc dis_tables_x87.inc dis_tables_sse.inc dis_tables_avx.inc
dis_groups.o: dis_groups.@CPP_SUFFIX@ disasm.h ../config.h
resolve.o: resolve.@CPP_SUFFIX@ disasm.h ../config.h
syntax.o: syntax.@CPP_SUFFIX@ disasm.h ../config.h

53
bochs/disasm/dis_decode.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2009 Stanislav Shwartsman
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -199,7 +199,22 @@ x86_insn disassembler::decode(bx_bool is_32, bx_bool is_64, bx_address base, bx_
entry = opcode_table + insn.b1;
if (instruction_has_modrm[insn.b1])
if ((insn.b1 & ~1) == 0xc4 && (is_64 || (peek_byte() & 0xc0) == 0xc0))
{
if (sse_prefix)
dis_sprintf("(bad vex+rex prefix) ");
if (rex_prefix)
dis_sprintf("(bad vex+sse prefix) ");
// decode 0xC4 or 0xC5 VEX prefix
sse_prefix = decode_vex(&insn);
if (insn.b1 < 256 || insn.b1 >= 1024)
entry = &BxDisasmGroupSSE_ERR[0];
else
entry = BxDisasmOpcodesAVX + (insn.b1 - 256);
}
if (insn.b1 >= 512 || instruction_has_modrm[insn.b1])
{
// take 3rd byte for 3-byte opcode
if (entry->Attr == _GRP3BOP) {
@ -346,11 +361,45 @@ x86_insn disassembler::decode(bx_bool is_32, bx_bool is_64, bx_address base, bx_
dis_sprintf(", taken");
}
if (insn.is_vex < 0)
dis_sprintf(" (bad vex)");
insn.ilen = (unsigned)(instruction - instruction_begin);
return insn;
}
unsigned disassembler::decode_vex(x86_insn *insn)
{
insn->is_vex = 1;
unsigned b2 = fetch_byte(), vex_opcode_extension = 1;
insn->rex_r = (b2 & 0x80) ? 0 : 0x8;
if (insn->b1 == 0xc4) {
// decode 3-byte VEX prefix
insn->rex_x = (b2 & 0x40) ? 0 : 0x8;
if (insn->is_64)
insn->rex_b = (b2 & 0x20) ? 0 : 0x8;
vex_opcode_extension = b2 & 0x1f;
if (! vex_opcode_extension || vex_opcode_extension > 3)
insn->is_vex = -1;
b2 = fetch_byte(); // fetch VEX3 byte
if (b2 & 0x80) {
insn->os_64 = 1;
insn->os_32 = 1;
}
}
insn->vex_override = 15 - ((b2 >> 3) & 0xf);
insn->vex_vl = (b2 >> 2) & 0x1;
insn->b1 = fetch_byte() + 256 * vex_opcode_extension;
return b2 & 0x3;
}
void disassembler::dis_sprintf(const char *fmt, ...)
{
va_list ap;

29
bochs/disasm/dis_groups.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2009 Stanislav Shwartsman
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -402,13 +402,10 @@ void disassembler::Qq(const x86_insn *insn)
(this->*resolve_modrm)(insn, Q_SIZE);
}
// xmm register
// xmm/ymm register
void disassembler::Udq(const x86_insn *insn)
{
if (intel_mode)
dis_sprintf ("xmm%d", insn->rm);
else
dis_sprintf("%%xmm%d", insn->rm);
dis_sprintf("%s%d", vector_reg_name[insn->vex_vl], insn->rm);
}
void disassembler::Ups(const x86_insn *insn) { Udq(insn); }
@ -416,10 +413,7 @@ void disassembler::Upd(const x86_insn *insn) { Udq(insn); }
void disassembler::Vq(const x86_insn *insn)
{
if (intel_mode)
dis_sprintf ("xmm%d", insn->nnn);
else
dis_sprintf("%%xmm%d", insn->nnn);
dis_sprintf("%s%d", vector_reg_name[insn->vex_vl], insn->nnn);
}
void disassembler::Vdq(const x86_insn *insn) { Vq(insn); }
@ -428,6 +422,21 @@ void disassembler::Vsd(const x86_insn *insn) { Vq(insn); }
void disassembler::Vps(const x86_insn *insn) { Vq(insn); }
void disassembler::Vpd(const x86_insn *insn) { Vq(insn); }
void disassembler::VIb(const x86_insn *insn)
{
unsigned vreg = fetch_byte() >> 4;
if (! insn->is_64) vreg &= 7;
dis_sprintf("%s%d", vector_reg_name[insn->vex_vl], vreg);
}
void disassembler::Hdq(const x86_insn *insn)
{
dis_sprintf("%s%d", vector_reg_name[insn->vex_vl], insn->vex_override);
}
void disassembler::Hps(const x86_insn *insn) { Hdq(insn); }
void disassembler::Hpd(const x86_insn *insn) { Hdq(insn); }
void disassembler::Ww(const x86_insn *insn)
{
if (insn->mod == 3) Udq(insn);

9
bochs/disasm/dis_tables.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2010 Stanislav Shwartsman
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -37,6 +37,7 @@
/* ************************************************************************ */
#define GRPSSE(n) _GRPSSE, BxDisasmGroupSSE_##n
#define GRPAVX(n) _GRPSSE, BxDisasmGroupAVX_##n
#define GRPN(n) _GROUPN, BxDisasmGroup##n
#define GRPRM(n) _GRPRM, BxDisasmGroupRm##n
#define GRPMOD(n) _SPLIT11B, BxDisasmGroupMod##n
@ -132,6 +133,7 @@
#define Vsd &disassembler::Vsd
#define Vps &disassembler::Vps
#define Vpd &disassembler::Vpd
#define VIb &disassembler::VIb
#define Ups &disassembler::Ups
#define Upd &disassembler::Upd
@ -146,6 +148,10 @@
#define Wps &disassembler::Wps
#define Wpd &disassembler::Wpd
#define Hdq &disassembler::Hdq
#define Hps &disassembler::Hps
#define Hpd &disassembler::Hpd
#define Ob &disassembler::Ob
#define Ow &disassembler::Ow
#define Od &disassembler::Od
@ -189,6 +195,7 @@ const struct BxDisasmOpcodeInfo_t
#include "opcodes.inc"
#include "dis_tables_x87.inc"
#include "dis_tables_sse.inc"
#include "dis_tables_avx.inc"
#include "dis_tables.inc"
#undef XX

2
bochs/disasm/dis_tables.inc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2010 Stanislav Shwartsman
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or

1196
bochs/disasm/dis_tables_avx.inc Normal file
View File

File diff suppressed because it is too large Load Diff

10
bochs/disasm/dis_tables_sse.inc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2010 Stanislav Shwartsman
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -65,15 +65,15 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f13[4] = {
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f14[4] = {
/* -- */ { 0, &Ia_unpcklps_Vps_Wdq },
/* 66 */ { 0, &Ia_unpcklpd_Vpd_Wdq },
/* -- */ { 0, &Ia_unpcklps_Vps_Wps },
/* 66 */ { 0, &Ia_unpcklpd_Vpd_Wpd },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f15[4] = {
/* -- */ { 0, &Ia_unpckhps_Vps_Wdq },
/* 66 */ { 0, &Ia_unpckhpd_Vpd_Wdq },
/* -- */ { 0, &Ia_unpckhps_Vps_Wps },
/* 66 */ { 0, &Ia_unpckhpd_Vpd_Wpd },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
};

39
bochs/disasm/disasm.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2009 Stanislav Shwartsman
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -153,6 +153,10 @@ public:
unsigned b1;
unsigned ilen;
#define BX_AVX_VL128 0
#define BX_AVX_VL256 1
Bit8u vex_override, vex_vl;
int is_vex; // 0 - no VEX used, 1 - VEX is used, 2 - invalid VEX
Bit8u modrm, mod, nnn, rm;
Bit8u sib, scale, index, base;
union {
@ -185,6 +189,9 @@ BX_CPP_INLINE x86_insn::x86_insn(bx_bool is32, bx_bool is64)
ilen = 0;
b1 = 0;
is_vex = 0;
vex_override = 0;
vex_vl = BX_AVX_VL128;
modrm = mod = nnn = rm = 0;
sib = scale = index = base = 0;
displacement.displ32 = 0;
@ -234,6 +241,7 @@ private:
const char **segment_name;
const char **index16;
const char **vector_reg_name;
const char *sreg_mod00_base32[16];
const char *sreg_mod01or10_base32[16];
@ -287,6 +295,7 @@ private:
void dis_putc(char symbol);
void dis_sprintf(const char *fmt, ...);
void decode_modrm(x86_insn *insn);
unsigned decode_vex(x86_insn *insn);
void resolve16_mod0 (const x86_insn *insn, unsigned mode);
void resolve16_mod1or2(const x86_insn *insn, unsigned mode);
@ -354,11 +363,11 @@ public:
* R - The mod field of the ModR/M byte may refer only to a general register.
* S - The reg field of the ModR/M byte selects a segment register.
* T - The reg field of the ModR/M byte selects a test register.
* U - The R/M field of the ModR/M byte selects a 128-bit XMM register.
* V - The reg field of the ModR/M byte selects a 128-bit XMM register.
* U - The R/M field of the ModR/M byte selects a 128-bit XMM/256-bit YMM register.
* V - The reg field of the ModR/M byte selects a 128-bit XMM/256-bit YMM register.
* W - A ModR/M byte follows the opcode and specifies the operand. The
* operand is either a 128-bit XMM register or a memory address. If
* it is a memory address, the address is computed from a segment
* operand is either a 128-bit XMM/256-bit YMM register or a memory address.
* If it is a memory address, the address is computed from a segment
* register and any of the following values: a base register, an
* index register, a scaling factor, and a displacement.
* X - Memory addressed by the DS:rSI register pair.
@ -375,14 +384,14 @@ public:
* d - Doubleword, regardless of operand-size attribute.
* dq - Double-quadword, regardless of operand-size attribute.
* p - 32-bit or 48-bit pointer, depending on operand-size attribute.
* pd - 128-bit packed double-precision floating-point data.
* pd - 128-bit/256-bit packed double-precision floating-point data.
* pi - Quadword MMX technology register (packed integer)
* ps - 128-bit packed single-precision floating-point data.
* ps - 128-bit/256-bit packed single-precision floating-point data.
* q - Quadword, regardless of operand-size attribute.
* s - 6-byte or 10-byte pseudo-descriptor.
* si - Doubleword integer register (scalar integer)
* ss - Scalar element of a 128-bit packed single-precision floating data.
* sd - Scalar element of a 128-bit packed double-precision floating data.
* ss - Scalar element of a packed single-precision floating data.
* sd - Scalar element of a packed double-precision floating data.
* v - Word, doubleword or quadword, depending on operand-size attribute.
* w - Word, regardless of operand-size attr.
* y - Doubleword or quadword (in 64-bit mode) depending on 32/64 bit
@ -449,6 +458,7 @@ public:
void Ey(const x86_insn *insn);
void Ebd(const x86_insn *insn);
void Ewd(const x86_insn *insn);
void Edq(const x86_insn *insn);
// general purpose register
void Gb(const x86_insn *insn);
@ -493,7 +503,7 @@ public:
void Vq(const x86_insn *insn);
void Nq(const x86_insn *insn);
// xmm register
// xmm/ymm register
void Ups(const x86_insn *insn);
void Upd(const x86_insn *insn);
void Udq(const x86_insn *insn);
@ -503,8 +513,10 @@ public:
void Vsd(const x86_insn *insn);
void Vps(const x86_insn *insn);
void Vpd(const x86_insn *insn);
// xmm/ymm register through imm byte
void VIb(const x86_insn *insn);
// xmm register or memory operand
// xmm/ymm register or memory operand
void Ww(const x86_insn *insn);
void Wd(const x86_insn *insn);
void Wq(const x86_insn *insn);
@ -515,6 +527,11 @@ public:
void Wps(const x86_insn *insn);
void Wpd(const x86_insn *insn);
// vex override xmm/ymm register
void Hdq(const x86_insn *insn);
void Hps(const x86_insn *insn);
void Hpd(const x86_insn *insn);
// direct memory access
void OP_O(const x86_insn *insn, unsigned size);
void Ob(const x86_insn *insn);

300
bochs/disasm/opcodes.inc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2009 Stanislav Shwartsman
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -1290,24 +1290,314 @@ Ia_ucomisd_Vsd_Wsd = { "ucomisd", "ucomisd", Vsd, Wsd, XX, XX, IA_SSE2 },
Ia_ucomiss_Vss_Wss = { "ucomiss", "ucomiss", Vss, Wss, XX, XX, IA_SSE },
Ia_ud2a = { "ud2a", "ud2a", XX, XX, XX, XX, IA_P6 },
Ia_ud2b = { "ud2b", "ud2b", XX, XX, XX, XX, IA_P6 },
Ia_unpckhpd_Vpd_Wdq = { "unpckhpd", "unpckhpd", Vpd, Wdq, XX, XX, IA_SSE2 },
Ia_unpckhps_Vps_Wdq = { "unpckhps", "unpckhps", Vps, Wdq, XX, XX, IA_SSE },
Ia_unpcklpd_Vpd_Wdq = { "unpcklpd", "unpcklpd", Vpd, Wdq, XX, XX, IA_SSE2 },
Ia_unpcklps_Vps_Wdq = { "unpcklps", "unpcklps", Vps, Wdq, XX, XX, IA_SSE },
Ia_unpckhpd_Vpd_Wpd = { "unpckhpd", "unpckhpd", Vpd, Wpd, XX, XX, IA_SSE2 },
Ia_unpckhps_Vps_Wps = { "unpckhps", "unpckhps", Vps, Wps, XX, XX, IA_SSE },
Ia_unpcklpd_Vpd_Wpd = { "unpcklpd", "unpcklpd", Vpd, Wpd, XX, XX, IA_SSE2 },
Ia_unpcklps_Vps_Wps = { "unpcklps", "unpcklps", Vps, Wps, XX, XX, IA_SSE },
Ia_vaddpd_Vpd_Hpd_Wpd = { "vaddpd", "vaddpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vaddps_Vps_Hps_Wps = { "vaddps", "vaddps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vaddsd_Vsd_Hpd_Wsd = { "vaddsd", "vaddsd", Vsd, Hpd, Wsd, XX, IA_AVX },
Ia_vaddss_Vss_Hps_Wss = { "vaddss", "vaddss", Vss, Hps, Wss, XX, IA_AVX },
Ia_vaddsubpd_Vpd_Hpd_Wpd = { "vaddsubpd", "vaddsubpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vaddsubps_Vps_Hps_Wps = { "vaddsubps", "vaddsubps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vaesdec_Vdq_Hdq_Wdq = { "vaesdec", "vaesdec", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vaesdeclast_Vdq_Hdq_Wdq = { "vaesdeclast", "vaesdeclast", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vaesenc_Vdq_Hdq_Wdq = { "vaesenc", "vaesenc", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vaesenclast_Vdq_Hdq_Wdq = { "vaesenclast", "vaesenclast", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vaesimc_Vdq_Wdq = { "vaesimc", "vaesimc", Vdq, Wdq, XX, XX, IA_AVX },
Ia_vaeskeygenassist_Vdq_Wdq_Ib = { "vaeskeygenassist", "vaeskeygenassist", Vdq, Wdq, Ib, XX, IA_AVX },
Ia_vandnpd_Vpd_Hpd_Wpd = { "vandnpd", "vandnpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vandnps_Vps_Hps_Wps = { "vandnps", "vandnps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vandpd_Vpd_Hpd_Wpd = { "vandpd", "vandpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vandps_Vps_Hps_Wps = { "vandps", "vandps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vblendpd_Vpd_Hpd_Wpd_Ib = { "vblendpd", "vblendpd", Vpd, Hpd, Wpd, Ib, IA_AVX },
Ia_vblendps_Vps_Hps_Wps_Ib = { "vblendps", "vblendps", Vps, Hps, Wps, Ib, IA_AVX },
Ia_vblendvpd_Vpd_Hpd_Wpd_Ib = { "vblendvpd", "vblendvpd", Vpd, Hpd, Wpd, VIb, IA_AVX },
Ia_vblendvps_Vps_Hps_Wps_Ib = { "vblendvps", "vblendvps", Vps, Hps, Wps, VIb, IA_AVX },
Ia_vbroadcastf128_Vdq_Mdq = { "vbroadcastf128", "vbroadcastf128", Vdq, Mdq, XX, XX, IA_AVX },
Ia_vbroadcastsd_Vpd_Msd = { "vbroadcastsd", "vbroadcastsd", Vpd, Msd, XX, XX, IA_AVX },
Ia_vbroadcastss_Vps_Mss = { "vbroadcastss", "vbroadcastss", Vps, Mss, XX, XX, IA_AVX },
Ia_vcmppd_Vpd_Hpd_Wpd_Ib = { "vcmppd", "vcmppd", Vpd, Hpd, Wpd, Ib, IA_AVX },
Ia_vcmpps_Vps_Hps_Wps_Ib = { "vcmpps", "vcmpps", Vps, Hps, Wps, Ib, IA_AVX },
Ia_vcmpsd_Vsd_Hpd_Wsd_Ib = { "vcmpsd", "vcmpsd", Vsd, Hpd, Wsd, Ib, IA_AVX },
Ia_vcmpss_Vss_Hps_Wss_Ib = { "vcmpss", "vcmpss", Vss, Hps, Wss, Ib, IA_AVX },
Ia_vcomisd_Vsd_Wsd = { "vcomisd", "vcomisd", Vsd, Wsd, XX, XX, IA_AVX },
Ia_vcomiss_Vss_Wss = { "vcomiss", "vcomiss", Vss, Wss, XX, XX, IA_AVX },
Ia_vcvtdq2pd_Vpd_Wq = { "vcvtdq2pd", "vcvtdq2pd", Vpd, Wq, XX, XX, IA_AVX },
Ia_vcvtdq2ps_Vps_Wdq = { "vcvtdq2ps", "vcvtdq2ps", Vps, Wdq, XX, XX, IA_AVX },
Ia_vcvtpd2dq_Vq_Wpd = { "vcvtpd2dq", "vcvtpd2dq", Vq, Wpd, XX, XX, IA_AVX },
Ia_vcvtpd2ps_Vps_Wpd = { "vcvtpd2ps", "vcvtpd2ps", Vps, Wpd, XX, XX, IA_AVX },
Ia_vcvtps2dq_Vdq_Wps = { "vcvtps2dq", "vcvtps2dq", Vdq, Wps, XX, XX, IA_AVX },
Ia_vcvtps2pd_Vpd_Wps = { "vcvtps2pd", "vcvtps2pd", Vpd, Wps, XX, XX, IA_AVX },
Ia_vcvtsd2si_Gy_Wsd = { "vcvtsd2si", "vcvtsd2si", Gy, Wsd, XX, XX, IA_AVX },
Ia_vcvtsd2ss_Vss_Hps_Wsd = { "vcvtsd2ss", "vcvtsd2ss", Vss, Hps, Wsd, XX, IA_AVX },
Ia_vcvtsi2sd_Vsd_Hpd_Ey = { "vcvtsi2sd", "vcvtsi2sd", Vsd, Hpd, Ey, XX, IA_AVX },
Ia_vcvtsi2ss_Vss_Hps_Ey = { "vcvtsi2ss", "vcvtsi2ss", Vss, Hps, Ey, XX, IA_AVX },
Ia_vcvtss2sd_Vsd_Hpd_Wss = { "vcvtss2sd", "vcvtss2sd", Vsd, Hpd, Wss, XX, IA_AVX },
Ia_vcvtss2si_Gy_Wss = { "vcvtss2si", "vcvtss2si", Gy, Wss, XX, XX, IA_AVX },
Ia_vcvttpd2dq_Vq_Wpd = { "vcvttpd2dq", "vcvttpd2dq", Vq, Wpd, XX, XX, IA_AVX },
Ia_vcvttps2dq_Vdq_Wps = { "vcvttps2dq", "vcvttps2dq", Vdq, Wps, XX, XX, IA_AVX },
Ia_vcvttsd2si_Gy_Wsd = { "vcvttsd2si", "vcvttsd2si", Gy, Wsd, XX, XX, IA_AVX },
Ia_vcvttss2si_Gy_Wss = { "vcvttss2si", "vcvttss2si", Gy, Wss, XX, XX, IA_AVX },
Ia_vdivpd_Vpd_Hpd_Wpd = { "vdivpd", "vdivpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vdivps_Vps_Hps_Wps = { "vdivps", "vdivps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vdivsd_Vsd_Hpd_Wsd = { "vdivsd", "vdivsd", Vsd, Hpd, Wsd, XX, IA_AVX },
Ia_vdivss_Vss_Hps_Wss = { "vdivss", "vdivss", Vss, Hps, Wss, XX, IA_AVX },
Ia_vdppd_Vpd_Hpd_Wpd_Ib = { "vdppd", "vdppd", Vpd, Hpd, Wpd, Ib, IA_AVX },
Ia_vdpps_Vps_Hps_Wps_Ib = { "vdpps", "vdpps", Vps, Hps, Wps, Ib, IA_AVX },
Ia_verr = { "verr", "verr", Ew, XX, XX, XX, 0 },
Ia_verw = { "verw", "verw", Ew, XX, XX, XX, 0 },
Ia_vextractf128_Wdq_Vdq_Ib = { "vextractf128", "vextractf128", Wdq, Vdq, Ib, XX, IA_AVX },
Ia_vextractps_Ed_Vdq_Ib = { "vextractps", "vextractps", Ed, Vdq, Ib, XX, IA_AVX },
Ia_vhaddpd_Vpd_Hpd_Wpd = { "vhaddpd", "vhaddpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vhaddps_Vps_Hps_Wps = { "vhaddps", "vhaddps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vhsubpd_Vpd_Hpd_Wpd = { "vhsubpd", "vhsubpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vhsubps_Vps_Hps_Wps = { "vhsubps", "vhsubps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vinsertf128_Vdq_Hdq_Wdq_Ib = { "vinsertf128", "vinsertf128", Vdq, Hdq, Wdq, Ib, IA_AVX },
Ia_vinsertps_Vps_Hps_Wss_Ib = { "vinsertps", "vinsertps", Vps, Hps, Wss, Ib, IA_AVX },
Ia_vlddqu_Vdq_Mdq = { "vlddqu", "vlddqu", Vdq, Mdq, XX, XX, IA_AVX },
Ia_vldmxcsr = { "vldmxcsr", "vldmxcsr", Md, XX, XX, XX, IA_AVX },
Ia_vmaskmovdqu_Vdq_Udq = { "vmaskmovdqu", "vmaskmovdqu", Vdq, Udq, XX, XX, IA_AVX },
Ia_vmaskmovpd_Vpd_Hpd_Mpd = { "vmaskmovpd", "vmaskmovpd", Vpd, Hpd, Mpd, XX, IA_AVX },
Ia_vmaskmovpd_Mpd_Hpd_Vpd = { "vmaskmovpd", "vmaskmovpd", Mpd, Hpd, Vpd, XX, IA_AVX },
Ia_vmaskmovps_Vps_Hps_Mps = { "vmaskmovps", "vmaskmovps", Vps, Hps, Mps, XX, IA_AVX },
Ia_vmaskmovps_Mps_Hps_Vps = { "vmaskmovps", "vmaskmovps", Mps, Hps, Vps, XX, IA_AVX },
Ia_vmaxpd_Vpd_Hpd_Wpd = { "vmaxpd", "vmaxpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vmaxps_Vps_Hps_Wps = { "vmaxps", "vmaxps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vmaxsd_Vsd_Hpd_Wsd = { "vmaxsd", "vmaxsd", Vsd, Hpd, Wsd, XX, IA_AVX },
Ia_vmaxss_Vss_Hps_Wss = { "vmaxss", "vmaxss", Vss, Hps, Wss, XX, IA_AVX },
Ia_vmcall = { "vmcall", "vmcall", XX, XX, XX, XX, IA_VMX },
Ia_vmclear_Mq = { "vmclear", "vmclear", Mq, XX, XX, XX, IA_VMX },
Ia_vminpd_Vpd_Hpd_Wpd = { "vminpd", "vminpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vminps_Vps_Hps_Wps = { "vminps", "vminps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vminsd_Vsd_Hpd_Wsd = { "vminsd", "vminsd", Vsd, Hpd, Wsd, XX, IA_AVX },
Ia_vminss_Vss_Hps_Wss = { "vminss", "vminss", Vss, Hps, Wss, XX, IA_AVX },
Ia_vmlaunch = { "vmlaunch", "vmlaunch", XX, XX, XX, XX, IA_VMX },
Ia_vmovapd_Vpd_Wpd = { "vmovapd", "vmovapd", Vpd, Wpd, XX, XX, IA_AVX },
Ia_vmovapd_Wpd_Vpd = { "vmovapd", "vmovapd", Wpd, Vpd, XX, XX, IA_AVX },
Ia_vmovaps_Vps_Wps = { "vmovaps", "vmovaps", Vps, Wps, XX, XX, IA_AVX },
Ia_vmovaps_Wps_Vps = { "vmovaps", "vmovaps", Wps, Vps, XX, XX, IA_AVX },
Ia_vmovd_Ed_Vd = { "vmovd", "vmovd", Ed, Vdq, XX, XX, IA_AVX },
Ia_vmovd_Vdq_Ed = { "vmovd", "vmovd", Vdq, Ed, XX, XX, IA_AVX },
Ia_vmovq_Vdq_Eq = { "vmovq", "vmovq", Vdq, Eq, XX, XX, IA_AVX },
Ia_vmovddup_Vdq_Wq = { "vmovddup", "vmovddup", Vdq, Wq, XX, XX, IA_AVX },
Ia_vmovdqa_Vdq_Wdq = { "vmovdqa", "vmovdqa", Vdq, Wdq, XX, XX, IA_AVX },
Ia_vmovdqa_Wdq_Vdq = { "vmovdqa", "vmovdqa", Wdq, Vdq, XX, XX, IA_AVX },
Ia_vmovdqu_Vdq_Wdq = { "vmovdqu", "vmovdqu", Vdq, Wdq, XX, XX, IA_AVX },
Ia_vmovdqu_Wdq_Vdq = { "vmovdqu", "vmovdqu", Wdq, Vdq, XX, XX, IA_AVX },
Ia_vmovhlpd_Vpd_Hdq_Udq = { "vmovhlpd", "vmovhlpd", Vpd, Hdq, Udq, XX, IA_AVX },
Ia_vmovhlps_Vps_Hdq_Udq = { "vmovhlps", "vmovhlps", Vps, Hdq, Udq, XX, IA_AVX },
Ia_vmovhpd_Mq_Vpd = { "vmovhpd", "vmovhpd", Mq, Vpd, XX, XX, IA_AVX },
Ia_vmovhpd_Vpd_Hdq_Mq = { "vmovhpd", "vmovhpd", Vpd, Hdq, Mq, XX, IA_AVX },
Ia_vmovhps_Mq_Vps = { "vmovhps", "vmovhps", Mq, Vps, XX, XX, IA_AVX },
Ia_vmovhps_Vps_Hdq_Mq = { "vmovhps", "vmovhps", Vps, Hdq, Mq, XX, IA_AVX },
Ia_vmovlhpd_Vpd_Hdq_Udq = { "vmovlhpd", "vmovlhpd", Vpd, Hdq, Udq, XX, IA_AVX },
Ia_vmovlhps_Vps_Hdq_Udq = { "vmovlhps", "vmovlhps", Vps, Hdq, Udq, XX, IA_AVX },
Ia_vmovlpd_Mq_Vpd = { "vmovlpd", "vmovlpd", Mq, Vpd, XX, XX, IA_AVX },
Ia_vmovlpd_Vpd_Hdq_Mq = { "vmovlpd", "vmovlpd", Vpd, Hdq, Mq, XX, IA_AVX },
Ia_vmovlps_Mq_Vps = { "vmovlps", "vmovlps", Mq, Vps, XX, XX, IA_AVX },
Ia_vmovlps_Vps_Hdq_Mq = { "vmovlps", "vmovlps", Vps, Hdq, Mq, XX, IA_AVX },
Ia_vmovmskpd_Gd_Vpd = { "vmovmskpd", "vmovmskpd", Gd, Vpd, XX, XX, IA_AVX },
Ia_vmovmskps_Gd_Vps = { "vmovmskps", "vmovmskps", Gd, Vps, XX, XX, IA_AVX },
Ia_vmovntdq_Mdq_Vdq = { "vmovntdq", "vmovntdq", Mdq, Vdq, XX, XX, IA_AVX },
Ia_vmovntdqa_Vdq_Mdq = { "vmovntdqa", "vmovntdqa", Vdq, Mdq, XX, XX, IA_AVX },
Ia_vmovntpd_Mpd_Vpd = { "vmovntpd", "vmovntpd", Mpd, Vpd, XX, XX, IA_AVX },
Ia_vmovntps_Mps_Vps = { "vmovntps", "vmovntps", Mps, Vps, XX, XX, IA_AVX },
Ia_vmovq_Eq_Vq = { "vmovq", "vmovq", Eq, Vq, XX, XX, IA_AVX },
Ia_vmovq_Vq_Wq = { "vmovq", "vmovq", Vq, Wq, XX, XX, IA_AVX },
Ia_vmovq_Wq_Vq = { "vmovq", "vmovq", Wq, Vq, XX, XX, IA_AVX },
Ia_vmovsd_Vsd_Wsd = { "vmovsd", "vmovsd", Vsd, Hpd, Wsd, XX, IA_AVX },
Ia_vmovsd_Wsd_Vsd = { "vmovsd", "vmovsd", Wsd, Vsd, XX, XX, IA_AVX },
Ia_vmovshdup_Vdq_Wdq = { "vmovshdup", "vmovshdup", Vdq, Wdq, XX, XX, IA_AVX },
Ia_vmovsldup_Vdq_Wdq = { "vmovsldup", "vmovsldup", Vdq, Wdq, XX, XX, IA_AVX },
Ia_vmovss_Vss_Wss = { "vmovss", "vmovss", Vss, Hps, Wss, XX, IA_AVX },
Ia_vmovss_Wss_Vss = { "vmovss", "vmovss", Wss, Vss, XX, XX, IA_AVX },
Ia_vmovupd_Vpd_Wpd = { "vmovupd", "vmovupd", Vpd, Wpd, XX, XX, IA_AVX },
Ia_vmovupd_Wpd_Vpd = { "vmovupd", "vmovupd", Wpd, Vpd, XX, XX, IA_AVX },
Ia_vmovups_Vps_Wps = { "vmovups", "vmovups", Vps, Wps, XX, XX, IA_AVX },
Ia_vmovups_Wps_Vps = { "vmovups", "vmovups", Wps, Vps, XX, XX, IA_AVX },
Ia_vmpsadbw_Vdq_Hdq_Wdq_Ib = { "vmpsadbw", "vmpsadbw", Vdq, Hdq, Wdq, Ib, IA_AVX },
Ia_vmptrld_Mq = { "vmptrld", "vmptrld", Mq, XX, XX, XX, IA_VMX },
Ia_vmptrst_Mq = { "vmptrst", "vmptrst", Mq, XX, XX, XX, IA_VMX },
Ia_vmread_Ed_Gd = { "vmread", "vmread", Ed, Gd, XX, XX, IA_VMX },
Ia_vmread_Eq_Gq = { "vmread", "vmread", Eq, Gq, XX, XX, IA_VMX },
Ia_vmresume = { "vmresume", "vmresume", XX, XX, XX, XX, IA_VMX },
Ia_vmulpd_Vpd_Hpd_Wpd = { "vmulpd", "vmulpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vmulps_Vps_Hps_Wps = { "vmulps", "vmulps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vmulsd_Vsd_Hpd_Wsd = { "vmulsd", "vmulsd", Vsd, Hpd, Wsd, XX, IA_AVX },
Ia_vmulss_Vss_Hps_Wss = { "vmulss", "vmulss", Vss, Hps, Wss, XX, IA_AVX },
Ia_vmwrite_Gd_Ed = { "vmwrite", "vmwrite", Gd, Ed, XX, XX, IA_VMX },
Ia_vmwrite_Gq_Eq = { "vmwrite", "vmwrite", Gq, Eq, XX, XX, IA_VMX },
Ia_vmxoff = { "vmxoff", "vmxoff", XX, XX, XX, XX, IA_VMX },
Ia_vmxon_Mq = { "vmxon", "vmxon", Mq, XX, XX, XX, IA_VMX },
Ia_vorpd_Vpd_Hpd_Wpd = { "vorpd", "vorpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vorps_Vps_Hps_Wps = { "vorps", "vorps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vpabsb_Vdq_Hdq_Wdq = { "vpabsb", "vpabsb", Vdq, Wdq, XX, XX, IA_AVX },
Ia_vpabsd_Vdq_Hdq_Wdq = { "vpabsd", "vpabsd", Vdq, Wdq, XX, XX, IA_AVX },
Ia_vpabsw_Vdq_Hdq_Wdq = { "vpabsw", "vpabsw", Vdq, Wdq, XX, XX, IA_AVX },
Ia_vpackssdw_Vdq_Hdq_Wdq = { "vpackssdw", "vpackssdw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpacksswb_Vdq_Hdq_Wdq = { "vpacksswb", "vpacksswb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpackusdw_Vdq_Hdq_Wdq = { "vpackusdw", "vpackusdw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpackuswb_Vdq_Hdq_Wdq = { "vpackuswb", "vpackuswb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpaddb_Vdq_Hdq_Wdq = { "vpaddb", "vpaddb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpaddd_Vdq_Hdq_Wdq = { "vpaddd", "vpaddd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpaddq_Vdq_Hdq_Wdq = { "vpaddq", "vpaddq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpaddsb_Vdq_Hdq_Wdq = { "vpaddsb", "vpaddsb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpaddsw_Vdq_Hdq_Wdq = { "vpaddsw", "vpaddsw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpaddusb_Vdq_Hdq_Wdq = { "vpaddusb", "vpaddusb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpaddusw_Vdq_Hdq_Wdq = { "vpaddusw", "vpaddusw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpaddw_Vdq_Hdq_Wdq = { "vpaddw", "vpaddw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpalignr_Vdq_Hdq_Wdq_Ib = { "vpalignr", "vpalignr", Vdq, Hdq, Wdq, Ib, IA_AVX },
Ia_vpand_Vdq_Hdq_Wdq = { "vpand", "vpand", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpandn_Vdq_Hdq_Wdq = { "vpandn", "vpandn", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpavgb_Vdq_Hdq_Wdq = { "vpavgb", "vpavgb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpavgw_Vdq_Hdq_Wdq = { "vpavgw", "vpavgw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpblendvb_Vdq_Hdq_Wdq_Ib = { "vpblendvb", "vpblendvb", Vdq, Hdq, Wdq, VIb, IA_AVX },
Ia_vpblendw_Vdq_Hdq_Wdq_Ib = { "vpblendw", "vpblendw", Vdq, Hdq, Wdq, Ib, IA_AVX },
Ia_vpclmulqdq_Vdq_Hdq_Wdq_Ib = { "vpclmulqdq", "vpclmulqdq", Vdq, Hdq, Wdq, Ib, IA_AVX },
Ia_vpcmpeqb_Vdq_Hdq_Wdq = { "vpcmpeqb", "vpcmpeqb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpcmpeqd_Vdq_Hdq_Wdq = { "vpcmpeqd", "vpcmpeqd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpcmpeqq_Vdq_Hdq_Wdq = { "vpcmpeqq", "vpcmpeqq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpcmpeqw_Vdq_Hdq_Wdq = { "vpcmpeqw", "vpcmpeqw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpcmpestri_Vdq_Wdq_Ib = { "vpcmpestri", "vpcmpestri", Vdq, Wdq, Ib, XX, IA_AVX },
Ia_vpcmpestrm_Vdq_Wdq_Ib = { "vpcmpestrm", "vpcmpestrm", Vdq, Wdq, Ib, XX, IA_AVX },
Ia_vpcmpgtb_Vdq_Hdq_Wdq = { "vpcmpgtb", "vpcmpgtb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpcmpgtd_Vdq_Hdq_Wdq = { "vpcmpgtd", "vpcmpgtd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpcmpgtq_Vdq_Hdq_Wdq = { "vpcmpgtq", "vpcmpgtq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpcmpgtw_Vdq_Hdq_Wdq = { "vpcmpgtw", "vpcmpgtw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpcmpistri_Vdq_Wdq_Ib = { "vpcmpistri", "vpcmpistri", Vdq, Wdq, Ib, XX, IA_AVX },
Ia_vpcmpistrm_Vdq_Wdq_Ib = { "vpcmpistrm", "vpcmpistrm", Vdq, Wdq, Ib, XX, IA_AVX },
Ia_vperm2f128_Vdq_Hdq_Wdq_Ib = { "vperm2f128", "vperm2f128", Vdq, Hdq, Wdq, Ib, IA_AVX },
Ia_vpermilpd_Vpd_Hpd_Wpd = { "vpermilpd", "vpermilpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vpermilpd_Vpd_Wpd_Ib = { "vpermilpd", "vpermilpd", Vpd, Wpd, Ib, XX, IA_AVX },
Ia_vpermilps_Vps_Hps_Wps = { "vpermilps", "vpermilps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vpermilps_Vps_Wps_Ib = { "vpermilps", "vpermilps", Vps, Wps, Ib, XX, IA_AVX },
Ia_vpextrb_Ebd_Vdq_Ib = { "vpextrb", "vpextrb", Ebd, Vdq, Ib, XX, IA_AVX },
Ia_vpextrd_Ed_Vdq_Ib = { "vpextrd", "vpextrd", Ed, Vdq, Ib, XX, IA_AVX },
Ia_vpextrq_Eq_Vdq_Ib = { "vpextrq", "vpextrq", Eq, Vdq, Ib, XX, IA_AVX },
Ia_vpextrw_Ewd_Vdq_Ib = { "vpextrw", "vpextrw", Ewd, Vdq, Ib, XX, IA_AVX },
Ia_vpextrw_Gd_Udq_Ib = { "vpextrw", "vpextrw", Gd, Udq, Ib, XX, IA_AVX },
Ia_vphaddd_Vdq_Hdq_Wdq = { "vphaddd", "vphaddd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vphaddsw_Vdq_Hdq_Wdq = { "vphaddsw", "vphaddsw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vphaddw_Vdq_Hdq_Wdq = { "vphaddw", "vphaddw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vphminposuw_Vdq_Wdq = { "vphminposuw", "vphminposuw", Vdq, Wdq, XX, XX, IA_AVX },
Ia_vphsubd_Vdq_Hdq_Wdq = { "vphsubd", "vphsubd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vphsubsw_Vdq_Hdq_Wdq = { "vphsubsw", "vphsubsw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vphsubw_Vdq_Hdq_Wdq = { "vphsubw", "vphsubw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpinsrb_Vdq_Hdq_Ed_Ib = { "vpinsrb", "vpinsrb", Vdq, Hdq, Ed, Ib, IA_AVX },
Ia_vpinsrd_Vdq_Hdq_Ed_Ib = { "vpinsrd", "vpinsrd", Vdq, Hdq, Ed, Ib, IA_AVX },
Ia_vpinsrq_Vdq_Hdq_Eq_Ib = { "vpinsrq", "vpinsrq", Vdq, Hdq, Eq, Ib, IA_AVX },
Ia_vpinsrw_Vdq_Hdq_Ew_Ib = { "vpinsrw", "vpinsrw", Vdq, Hdq, Ew, Ib, IA_AVX },
Ia_vpmaddubsw_Vdq_Hdq_Wdq = { "vpmaddubsw", "vpmaddubsw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmaddwd_Vdq_Hdq_Wdq = { "vpmaddwd", "vpmaddwd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmaxsb_Vdq_Hdq_Wdq = { "vpmaxsb", "vpmaxsb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmaxsd_Vdq_Hdq_Wdq = { "vpmaxsd", "vpmaxsd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmaxsw_Vdq_Hdq_Wdq = { "vpmaxsw", "vpmaxsw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmaxub_Vdq_Hdq_Wdq = { "vpmaxub", "vpmaxub", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmaxud_Vdq_Hdq_Wdq = { "vpmaxud", "vpmaxud", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmaxuw_Vdq_Hdq_Wdq = { "vpmaxuw", "vpmaxuw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpminsb_Vdq_Hdq_Wdq = { "vpminsb", "vpminsb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpminsd_Vdq_Hdq_Wdq = { "vpminsd", "vpminsd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpminsw_Vdq_Hdq_Wdq = { "vpminsw", "vpminsw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpminub_Vdq_Hdq_Wdq = { "vpminub", "vpminub", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpminud_Vdq_Hdq_Wdq = { "vpminud", "vpminud", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpminuw_Vdq_Hdq_Wdq = { "vpminuw", "vpminuw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmovmskb_Gd_Udq = { "vpmovmskb", "vpmovmskb", Gd, Udq, XX, XX, IA_AVX },
Ia_vpmovsxbd_Vdq_Wd = { "vpmovsxbd", "vpmovsxbd", Vdq, Wd, XX, XX, IA_AVX },
Ia_vpmovsxbq_Vdq_Ww = { "vpmovsxbq", "vpmovsxbq", Vdq, Ww, XX, XX, IA_AVX },
Ia_vpmovsxbw_Vdq_Wq = { "vpmovsxbw", "vpmovsxbw", Vdq, Wq, XX, XX, IA_AVX },
Ia_vpmovsxdq_Vdq_Wq = { "vpmovsxdq", "vpmovsxdq", Vdq, Wq, XX, XX, IA_AVX },
Ia_vpmovsxwd_Vdq_Wq = { "vpmovsxwd", "vpmovsxwd", Vdq, Wq, XX, XX, IA_AVX },
Ia_vpmovsxwq_Vdq_Wd = { "vpmovsxwq", "vpmovsxwq", Vdq, Wd, XX, XX, IA_AVX },
Ia_vpmovzxbd_Vdq_Wd = { "vpmovzxbd", "vpmovzxbd", Vdq, Wd, XX, XX, IA_AVX },
Ia_vpmovzxbq_Vdq_Ww = { "vpmovzxbq", "vpmovzxbq", Vdq, Ww, XX, XX, IA_AVX },
Ia_vpmovzxbw_Vdq_Wq = { "vpmovzxbw", "vpmovzxbw", Vdq, Wq, XX, XX, IA_AVX },
Ia_vpmovzxdq_Vdq_Wq = { "vpmovzxdq", "vpmovzxdq", Vdq, Wq, XX, XX, IA_AVX },
Ia_vpmovzxwd_Vdq_Wq = { "vpmovzxwd", "vpmovzxwd", Vdq, Wq, XX, XX, IA_AVX },
Ia_vpmovzxwq_Vdq_Wd = { "vpmovzxwq", "vpmovzxwq", Vdq, Wd, XX, XX, IA_AVX },
Ia_vpmuldq_Vdq_Hdq_Wdq = { "vpmuldq", "vpmuldq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmulhrsw_Vdq_Hdq_Wdq = { "vpmulhrsw", "vpmulhrsw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmulhuw_Vdq_Hdq_Wdq = { "vpmulhuw", "vpmulhuw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmulhw_Vdq_Hdq_Wdq = { "vpmulhw", "vpmulhw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmulld_Vdq_Hdq_Wdq = { "vpmulld", "vpmulld", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmullw_Vdq_Hdq_Wdq = { "vpmullw", "vpmullw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpmuludq_Vdq_Hdq_Wdq = { "vpmuludq", "vpmuludq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpor_Vdq_Hdq_Wdq = { "vpor", "vpor", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsadbw_Vdq_Hdq_Wdq = { "vpsadbw", "vpsadbw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpshufb_Vdq_Hdq_Wdq = { "vpshufb", "vpshufb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpshufd_Vdq_Hdq_Wdq_Ib = { "vpshufd", "vpshufd", Vdq, Wdq, Ib, XX, IA_AVX },
Ia_vpshufhw_Vdq_Hdq_Wdq_Ib = { "vpshufhw", "vpshufhw", Vdq, Wdq, Ib, XX, IA_AVX },
Ia_vpshuflw_Vdq_Hdq_Wdq_Ib = { "vpshuflw", "vpshuflw", Vdq, Wdq, Ib, XX, IA_AVX },
Ia_vpsignb_Vdq_Hdq_Wdq = { "vpsignb", "vpsignb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsignd_Vdq_Hdq_Wdq = { "vpsignd", "vpsignd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsignw_Vdq_Hdq_Wdq = { "vpsignw", "vpsignw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpslld_Hdq_Udq_Ib = { "vpslld", "vpslld", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpslld_Vdq_Hdq_Wdq = { "vpslld", "vpslld", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpslldq_Hdq_Udq_Ib = { "vpslldq", "vpslldq", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsllq_Hdq_Udq_Ib = { "vpsllq", "vpsllq", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsllq_Vdq_Hdq_Wdq = { "vpsllq", "vpsllq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsllw_Hdq_Udq_Ib = { "vpsllw", "vpsllw", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsllw_Vdq_Hdq_Wdq = { "vpsllw", "vpsllw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsrad_Hdq_Udq_Ib = { "vpsrad", "vpsrad", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsrad_Vdq_Hdq_Wdq = { "vpsrad", "vpsrad", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsraw_Hdq_Udq_Ib = { "vpsraw", "vpsraw", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsraw_Vdq_Hdq_Wdq = { "vpsraw", "vpsraw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsrld_Hdq_Udq_Ib = { "vpsrld", "vpsrld", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsrld_Vdq_Hdq_Wdq = { "vpsrld", "vpsrld", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsrldq_Hdq_Udq_Ib = { "vpsrldq", "vpsrldq", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsrlq_Hdq_Udq_Ib = { "vpsrlq", "vpsrlq", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsrlq_Vdq_Hdq_Wdq = { "vpsrlq", "vpsrlq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsrlw_Hdq_Udq_Ib = { "vpsrlw", "vpsrlw", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsrlw_Vdq_Hdq_Wdq = { "vpsrlw", "vpsrlw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsubb_Vdq_Hdq_Wdq = { "vpsubb", "vpsubb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsubd_Vdq_Hdq_Wdq = { "vpsubd", "vpsubd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsubq_Vdq_Hdq_Wdq = { "vpsubq", "vpsubq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsubsb_Vdq_Hdq_Wdq = { "vpsubsb", "vpsubsb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsubsw_Vdq_Hdq_Wdq = { "vpsubsw", "vpsubsw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsubusb_Vdq_Hdq_Wdq = { "vpsubusb", "vpsubusb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsubusw_Vdq_Hdq_Wdq = { "vpsubusw", "vpsubusw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsubw_Vdq_Hdq_Wdq = { "vpsubw", "vpsubw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vptest_Vdq_Wdq = { "vptest", "vptest", Vdq, Wdq, XX, XX, IA_AVX },
Ia_vpunpckhbw_Vdq_Hdq_Wdq = { "vpunpckhbw", "vpunpckhbw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpunpckhdq_Vdq_Hdq_Wdq = { "vpunpckhdq", "vpunpckhdq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpunpckhqdq_Vdq_Hdq_Wdq = { "vpunpckhqdq", "vpunpckhqdq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpunpckhwd_Vdq_Hdq_Wdq = { "vpunpckhwd", "vpunpckhwd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpunpcklbw_Vdq_Hdq_Wdq = { "vpunpcklbw", "vpunpcklbw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpunpckldq_Vdq_Hdq_Wdq = { "vpunpckldq", "vpunpckldq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpunpcklqdq_Vdq_Hdq_Wdq = { "vpunpcklqdq", "vpunpcklqdq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpunpcklwd_Vdq_Hdq_Wdq = { "vpunpcklwd", "vpunpcklwd", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpxor_Vdq_Hdq_Wdq = { "vpxor", "vpxor", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vrcpps_Vps_Wps = { "vrcpps", "vrcpps", Vps, Wps, XX, XX, IA_AVX },
Ia_vrcpss_Vss_Hps_Wss = { "vrcpss", "vrcpss", Vss, Hps, Wss, XX, IA_AVX },
Ia_vroundpd_Vpd_Wpd_Ib = { "vroundpd", "vroundpd", Vpd, Wpd, Ib, XX, IA_AVX },
Ia_vroundps_Vps_Wps_Ib = { "vroundps", "vroundps", Vps, Wps, Ib, XX, IA_AVX },
Ia_vroundsd_Vsd_Hpd_Wsd_Ib = { "vroundsd", "vroundsd", Vsd, Hpd, Wsd, Ib, IA_AVX },
Ia_vroundss_Vss_Hps_Wss_Ib = { "vroundss", "vroundss", Vss, Hps, Wss, Ib, IA_AVX },
Ia_vrsqrtps_Vps_Wps = { "vrsqrtps", "vrsqrtps", Vps, Wps, XX, XX, IA_AVX },
Ia_vrsqrtss_Vss_Hps_Wss = { "vrsqrtss", "vrsqrtss", Vss, Hps, Wss, XX, IA_AVX },
Ia_vshufpd_Vpd_Hpd_Wpd_Ib = { "vshufpd", "vshufpd", Vpd, Hpd, Wpd, Ib, IA_AVX },
Ia_vshufps_Vps_Hps_Wps_Ib = { "vshufps", "vshufps", Vps, Hps, Wps, Ib, IA_AVX },
Ia_vsqrtpd_Vpd_Wpd = { "vsqrtpd", "vsqrtpd", Vpd, Wpd, XX, XX, IA_AVX },
Ia_vsqrtps_Vps_Wps = { "vsqrtps", "vsqrtps", Vps, Wps, XX, XX, IA_AVX },
Ia_vsqrtsd_Vsd_Hpd_Wsd = { "vsqrtsd", "vsqrtsd", Vsd, Hpd, Wsd, XX, IA_AVX },
Ia_vsqrtss_Vss_Hps_Wss = { "vsqrtss", "vsqrtss", Vss, Hps, Wss, XX, IA_AVX },
Ia_vstmxcsr = { "vstmxcsr", "vstmxcsr", Md, XX, XX, XX, IA_AVX },
Ia_vsubpd_Vpd_Hpd_Wpd = { "vsubpd", "vsubpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vsubps_Vps_Hps_Wps = { "vsubps", "vsubps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vsubsd_Vsd_Hpd_Wsd = { "vsubsd", "vsubsd", Vsd, Hpd, Wsd, XX, IA_AVX },
Ia_vsubss_Vss_Hps_Wss = { "vsubss", "vsubss", Vss, Hps, Wss, XX, IA_AVX },
Ia_vtestpd_Vpd_Wpd = { "vtestpd", "vtestpd", Vpd, Wpd, XX, XX, IA_AVX },
Ia_vtestps_Vps_Wps = { "vtestps", "vtestps", Vps, Wps, XX, XX, IA_AVX },
Ia_vucomisd_Vsd_Wsd = { "vucomisd", "vucomisd", Vsd, Wsd, XX, XX, IA_AVX },
Ia_vucomiss_Vss_Wss = { "vucomiss", "vucomiss", Vss, Wss, XX, XX, IA_AVX },
Ia_vunpckhpd_Vpd_Hpd_Wpd = { "vunpckhpd", "vunpckhpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vunpckhps_Vps_Hps_Wps = { "vunpckhps", "vunpckhps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vunpcklpd_Vpd_Hpd_Wpd = { "vunpcklpd", "vunpcklpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vunpcklps_Vps_Hps_Wps = { "vunpcklps", "vunpcklps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vxorpd_Vpd_Hpd_Wpd = { "vxorpd", "vxorpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vxorps_Vps_Hps_Wps = { "vxorps", "vxorps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vzerall = { "vzeroall", "vzeroall", XX, XX, XX, XX, IA_AVX },
Ia_vzeroupper = { "vzeroupper", "vzeroupper", XX, XX, XX, XX, IA_AVX },
Ia_wbinvd = { "wbinvd", "wbinvd", XX, XX, XX, XX, IA_486 },
Ia_wrfsbase_Ry = { "wrfsbase", "wrfsbase", Ry, XX, XX, XX, IA_FSGSBASE },
Ia_wrgsbase_Ry = { "wrgsbase", "wrgsbase", Ry, XX, XX, XX, IA_FSGSBASE },

11
bochs/disasm/syntax.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2009 Stanislav Shwartsman
// Copyright (c) 2005-2011 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -83,6 +83,9 @@ static const char *intel_index16[8] = {
"bx"
};
static const char *intel_vector_reg_name[2] = {
"xmm", "ymm"
};
//////////////////
// AT&T STYLE
@ -141,6 +144,10 @@ static const char *att_index16[8] = {
"%bx"
};
static const char *att_vector_reg_name[2] = {
"%xmm", "%ymm"
};
#define NULL_SEGMENT_REGISTER 7
void disassembler::initialize_modrm_segregs()
@ -214,6 +221,7 @@ void disassembler::set_syntax_intel()
segment_name = intel_segment_name;
index16 = intel_index16;
vector_reg_name = intel_vector_reg_name;
initialize_modrm_segregs();
}
@ -256,6 +264,7 @@ void disassembler::set_syntax_att()
segment_name = att_segment_name;
index16 = att_index16;
vector_reg_name = att_vector_reg_name;
initialize_modrm_segregs();
}

8
bochs/doc/docbook/user/user.dbk
View File

@ -2081,6 +2081,11 @@ turn it off.
<entry>no</entry>
<entry>Intel Virtualization Extensions (VMX) support</entry>
</row>
<row>
<entry>--enable-avx</entry>
<entry>no</entry>
<entry>AVX instructions support</entry>
</row>
<row>
<entry>--enable-x86-debugger</entry>
<entry>no</entry>
@ -6491,7 +6496,8 @@ From here, you may use the following commands:
r|reg|regs|registers List of CPU integer registers and their contents
fp|fpu List of all FPU registers and their contents
mmx List of all MMX registers and their contents
sse List of all SSE registers and their contents
sse|xmm List of all SSE registers and their contents
ymm List of all AVX registers and their contents
sreg Show segment registers and their contents
dreg Show debug registers and their contents
creg Show control registers and their contents

1
bochs/main.cc
View File

@ -1067,6 +1067,7 @@ void bx_init_hardware()
#if BX_SUPPORT_MONITOR_MWAIT
BX_INFO((" MWAIT support: %s",mwait_enabled?"yes":"no"));
#endif
BX_INFO((" AVX support: %s",BX_SUPPORT_AVX?"yes":"no"));
#if BX_SUPPORT_VMX
BX_INFO((" VMX support: %d",BX_SUPPORT_VMX));
#else