split more SSE ops
This commit is contained in:
Stanislav Shwartsman
parent
cb43e52240
commit
25b1e2e58d
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.698 2010-12-25 19:34:43 sshwarts Exp $
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// $Id: cpu.h,v 1.699 2010-12-26 20:41:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2011 The Bochs Project
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@ -2042,8 +2042,8 @@ public: // for now...
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BX_SMF void CVTTSS2SI_GdWss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPS2PI_PqWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSS2SI_GdWss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void UCOMISS_VssWss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void COMISS_VpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void UCOMISS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void COMISS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVMSKPS_GdVRps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SQRTPS_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SQRTSS_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2093,8 +2093,8 @@ public: // for now...
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BX_SMF void CVTTSD2SI_GdWsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPD2PI_PqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSD2SI_GdWsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void UCOMISD_VsdWsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void COMISD_VpdWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void UCOMISD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void COMISD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MOVMSKPD_GdVRpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SQRTPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SQRTSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2104,13 +2104,13 @@ public: // for now...
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BX_SMF void MULSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SUBPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SUBSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPS2PD_VpsWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPD2PS_VpdWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSD2SS_VsdWsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSS2SD_VssWss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTDQ2PS_VpsWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPS2DQ_VdqWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTTPS2DQ_VdqWps(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPS2PD_VpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPD2PS_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSD2SS_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTSS2SD_VssWssR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTDQ2PS_VpsWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPS2DQ_VdqWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTTPS2DQ_VdqWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MINPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void MINSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void DIVPD_VpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -2169,9 +2169,9 @@ public: // for now...
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BX_SMF void PAVGW_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PMULHUW_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PMULHW_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTTPD2DQ_VqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPD2DQ_VqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTDQ2PD_VpdWq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTTPD2DQ_VqWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTPD2DQ_VqWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CVTDQ2PD_VpdWqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PSUBSB_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PSUBSW_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void PMINSW_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.287 2010-12-25 07:59:15 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.288 2010-12-26 20:41:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2011 The Bochs Project
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@ -833,10 +833,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2*2] = {
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/* 0F 2C /wm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /wr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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/* 0F 2D /wm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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/* 0F 2E /wr */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
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/* 0F 2E /wm */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
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/* 0F 2F /wr */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
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/* 0F 2F /wm */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
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/* 0F 2E /wr */ { BxPrefixSSE, BX_IA_UCOMISS_VssWssR, BxOpcodeGroupSSE_0f2eR },
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/* 0F 2E /wm */ { BxPrefixSSE, BX_IA_UCOMISS_VssWssM, BxOpcodeGroupSSE_0f2eM },
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/* 0F 2F /wr */ { BxPrefixSSE, BX_IA_COMISS_VpsWpsR, BxOpcodeGroupSSE_0f2fR },
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/* 0F 2F /wm */ { BxPrefixSSE, BX_IA_COMISS_VpsWpsM, BxOpcodeGroupSSE_0f2fM },
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/* 0F 30 /wr */ { 0, BX_IA_WRMSR },
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/* 0F 30 /wm */ { 0, BX_IA_WRMSR },
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/* 0F 31 /wr */ { 0, BX_IA_RDTSC },
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@ -901,7 +901,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2*2] = {
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/* 0F 4E /wm */ { 0, BX_IA_CMOVLE_GwEwM },
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/* 0F 4F /wr */ { 0, BX_IA_CMOVNLE_GwEwR },
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/* 0F 4F /wm */ { 0, BX_IA_CMOVNLE_GwEwM },
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/* 0F 50 /wr */ { BxPrefixSSE, BX_IA_MOVMSKPS_GdVRps, BxOpcodeGroupSSE_0f50 },
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/* 0F 50 /wr */ { BxPrefixSSE, BX_IA_MOVMSKPS_GdVRps, BxOpcodeGroupSSE_0f50R },
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/* 0F 50 /wm */ { 0, BX_IA_ERROR }, // MOVMSKPS/PD
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/* 0F 51 /wr */ { BxPrefixSSE, BX_IA_SQRTPS_VpsWpsR, BxOpcodeGroupSSE_0f51R },
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/* 0F 51 /wm */ { BxPrefixSSE, BX_IA_SQRTPS_VpsWpsM, BxOpcodeGroupSSE_0f51M },
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@ -921,10 +921,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2*2] = {
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/* 0F 58 /wm */ { BxPrefixSSE, BX_IA_ADDPS_VpsWpsM, BxOpcodeGroupSSE_0f58M },
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/* 0F 59 /wr */ { BxPrefixSSE, BX_IA_MULPS_VpsWpsR, BxOpcodeGroupSSE_0f59R },
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/* 0F 59 /wm */ { BxPrefixSSE, BX_IA_MULPS_VpsWpsM, BxOpcodeGroupSSE_0f59M },
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/* 0F 5A /wr */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWps, BxOpcodeGroupSSE_0f5a },
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/* 0F 5A /wm */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWps, BxOpcodeGroupSSE_0f5a },
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/* 0F 5B /wr */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdq, BxOpcodeGroupSSE_0f5b },
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/* 0F 5B /wm */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdq, BxOpcodeGroupSSE_0f5b },
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/* 0F 5A /wr */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWpsR, BxOpcodeGroupSSE_0f5aR },
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/* 0F 5A /wm */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWpsM, BxOpcodeGroupSSE_0f5aM },
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/* 0F 5B /wr */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdqR, BxOpcodeGroupSSE_0f5bR },
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/* 0F 5B /wm */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdqM, BxOpcodeGroupSSE_0f5bM },
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/* 0F 5C /wr */ { BxPrefixSSE, BX_IA_SUBPS_VpsWpsR, BxOpcodeGroupSSE_0f5cR },
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/* 0F 5C /wm */ { BxPrefixSSE, BX_IA_SUBPS_VpsWpsM, BxOpcodeGroupSSE_0f5cM },
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/* 0F 5D /wr */ { BxPrefixSSE, BX_IA_MINPS_VpsWpsR, BxOpcodeGroupSSE_0f5dR },
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@ -1201,8 +1201,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2*2] = {
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/* 0F E4 /wm */ { BxPrefixSSE, BX_IA_PMULHUW_PqQq, BxOpcodeGroupSSE_0fe4 },
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/* 0F E5 /wr */ { BxPrefixSSE, BX_IA_PMULHW_PqQq, BxOpcodeGroupSSE_0fe5 },
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/* 0F E5 /wm */ { BxPrefixSSE, BX_IA_PMULHW_PqQq, BxOpcodeGroupSSE_0fe5 },
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/* 0F E6 /wr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6 },
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/* 0F E6 /wm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6 },
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/* 0F E6 /wr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6R },
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/* 0F E6 /wm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6M },
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/* 0F E7 /wr */ { 0, BX_IA_ERROR }, // MOVNTQ/MOVNTDQ SSE group
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/* 0F E7 /wm */ { BxPrefixSSE, BX_IA_MOVNTQ_MqPq, BxOpcodeGroupSSE_0fe7M },
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/* 0F E8 /wr */ { BxPrefixSSE, BX_IA_PSUBSB_PqQq, BxOpcodeGroupSSE_0fe8 },
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@ -1908,10 +1908,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2*2] = {
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/* 0F 2C /dm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /dr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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/* 0F 2D /dm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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/* 0F 2E /dr */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
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/* 0F 2E /dm */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
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/* 0F 2F /dr */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
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/* 0F 2F /dm */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
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/* 0F 2E /dr */ { BxPrefixSSE, BX_IA_UCOMISS_VssWssR, BxOpcodeGroupSSE_0f2eR },
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/* 0F 2E /dm */ { BxPrefixSSE, BX_IA_UCOMISS_VssWssM, BxOpcodeGroupSSE_0f2eM },
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/* 0F 2F /dr */ { BxPrefixSSE, BX_IA_COMISS_VpsWpsR, BxOpcodeGroupSSE_0f2fR },
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/* 0F 2F /dm */ { BxPrefixSSE, BX_IA_COMISS_VpsWpsM, BxOpcodeGroupSSE_0f2fM },
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/* 0F 30 /dr */ { 0, BX_IA_WRMSR },
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/* 0F 30 /dm */ { 0, BX_IA_WRMSR },
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/* 0F 31 /dr */ { 0, BX_IA_RDTSC },
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@ -1976,7 +1976,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2*2] = {
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/* 0F 4E /dm */ { 0, BX_IA_CMOVLE_GdEdM },
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/* 0F 4F /dr */ { 0, BX_IA_CMOVNLE_GdEdR },
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/* 0F 4F /dm */ { 0, BX_IA_CMOVNLE_GdEdM },
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/* 0F 50 /dr */ { BxPrefixSSE, BX_IA_MOVMSKPS_GdVRps, BxOpcodeGroupSSE_0f50 },
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/* 0F 50 /dr */ { BxPrefixSSE, BX_IA_MOVMSKPS_GdVRps, BxOpcodeGroupSSE_0f50R },
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/* 0F 50 /dm */ { 0, BX_IA_ERROR }, // MOVMSKPS/PD
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/* 0F 51 /dr */ { BxPrefixSSE, BX_IA_SQRTPS_VpsWpsR, BxOpcodeGroupSSE_0f51R },
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/* 0F 51 /dm */ { BxPrefixSSE, BX_IA_SQRTPS_VpsWpsM, BxOpcodeGroupSSE_0f51M },
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@ -1996,10 +1996,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2*2] = {
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/* 0F 58 /dm */ { BxPrefixSSE, BX_IA_ADDPS_VpsWpsM, BxOpcodeGroupSSE_0f58M },
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/* 0F 59 /dr */ { BxPrefixSSE, BX_IA_MULPS_VpsWpsR, BxOpcodeGroupSSE_0f59R },
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/* 0F 59 /dm */ { BxPrefixSSE, BX_IA_MULPS_VpsWpsM, BxOpcodeGroupSSE_0f59M },
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/* 0F 5A /dr */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWps, BxOpcodeGroupSSE_0f5a },
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/* 0F 5A /dm */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWps, BxOpcodeGroupSSE_0f5a },
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/* 0F 5B /dr */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdq, BxOpcodeGroupSSE_0f5b },
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/* 0F 5B /dm */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdq, BxOpcodeGroupSSE_0f5b },
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/* 0F 5A /dr */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWpsR, BxOpcodeGroupSSE_0f5aR },
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/* 0F 5A /dm */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWpsM, BxOpcodeGroupSSE_0f5aM },
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/* 0F 5B /dr */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdqR, BxOpcodeGroupSSE_0f5bR },
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/* 0F 5B /dm */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdqM, BxOpcodeGroupSSE_0f5bM },
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/* 0F 5C /dr */ { BxPrefixSSE, BX_IA_SUBPS_VpsWpsR, BxOpcodeGroupSSE_0f5cR },
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/* 0F 5C /dm */ { BxPrefixSSE, BX_IA_SUBPS_VpsWpsM, BxOpcodeGroupSSE_0f5cM },
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/* 0F 5D /dr */ { BxPrefixSSE, BX_IA_MINPS_VpsWpsR, BxOpcodeGroupSSE_0f5dR },
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@ -2276,8 +2276,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2*2] = {
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/* 0F E4 /dm */ { BxPrefixSSE, BX_IA_PMULHUW_PqQq, BxOpcodeGroupSSE_0fe4 },
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/* 0F E5 /dr */ { BxPrefixSSE, BX_IA_PMULHW_PqQq, BxOpcodeGroupSSE_0fe5 },
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/* 0F E5 /dm */ { BxPrefixSSE, BX_IA_PMULHW_PqQq, BxOpcodeGroupSSE_0fe5 },
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/* 0F E6 /dr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6 },
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/* 0F E6 /dm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6 },
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/* 0F E6 /dr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6R },
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/* 0F E6 /dm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6M },
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/* 0F E7 /dr */ { 0, BX_IA_ERROR }, // MOVNTQ/MOVNTDQ SSE group
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/* 0F E7 /dm */ { BxPrefixSSE, BX_IA_MOVNTQ_MqPq, BxOpcodeGroupSSE_0fe7M },
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/* 0F E8 /dr */ { BxPrefixSSE, BX_IA_PSUBSB_PqQq, BxOpcodeGroupSSE_0fe8 },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.282 2010-12-25 07:59:15 sshwarts Exp $
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// $Id: fetchdecode64.cc,v 1.283 2010-12-26 20:41:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2011 The Bochs Project
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@ -761,10 +761,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
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/* 0F 2C /wm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
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/* 0F 2D /wr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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/* 0F 2D /wm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
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/* 0F 2E /wr */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
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/* 0F 2E /wm */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
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/* 0F 2F /wr */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
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/* 0F 2F /wm */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
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/* 0F 2E /wr */ { BxPrefixSSE, BX_IA_UCOMISS_VssWssR, BxOpcodeGroupSSE_0f2eR },
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/* 0F 2E /wm */ { BxPrefixSSE, BX_IA_UCOMISS_VssWssM, BxOpcodeGroupSSE_0f2eM },
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/* 0F 2F /wr */ { BxPrefixSSE, BX_IA_COMISS_VpsWpsR, BxOpcodeGroupSSE_0f2fR },
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/* 0F 2F /wm */ { BxPrefixSSE, BX_IA_COMISS_VpsWpsM, BxOpcodeGroupSSE_0f2fM },
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/* 0F 30 /wr */ { 0, BX_IA_WRMSR },
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||||
/* 0F 30 /wm */ { 0, BX_IA_WRMSR },
|
||||
/* 0F 31 /wr */ { 0, BX_IA_RDTSC },
|
||||
@ -829,7 +829,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F 4E /wm */ { 0, BX_IA_CMOVLE_GwEwM },
|
||||
/* 0F 4F /wr */ { 0, BX_IA_CMOVNLE_GwEwR },
|
||||
/* 0F 4F /wm */ { 0, BX_IA_CMOVNLE_GwEwM },
|
||||
/* 0F 50 /wr */ { BxPrefixSSE, BX_IA_MOVMSKPS_GdVRps, BxOpcodeGroupSSE_0f50 },
|
||||
/* 0F 50 /wr */ { BxPrefixSSE, BX_IA_MOVMSKPS_GdVRps, BxOpcodeGroupSSE_0f50R },
|
||||
/* 0F 50 /wm */ { 0, BX_IA_ERROR }, // MOVMSKPS/PD
|
||||
/* 0F 51 /wr */ { BxPrefixSSE, BX_IA_SQRTPS_VpsWpsR, BxOpcodeGroupSSE_0f51R },
|
||||
/* 0F 51 /wm */ { BxPrefixSSE, BX_IA_SQRTPS_VpsWpsM, BxOpcodeGroupSSE_0f51M },
|
||||
@ -849,10 +849,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F 58 /wm */ { BxPrefixSSE, BX_IA_ADDPS_VpsWpsM, BxOpcodeGroupSSE_0f58M },
|
||||
/* 0F 59 /wr */ { BxPrefixSSE, BX_IA_MULPS_VpsWpsR, BxOpcodeGroupSSE_0f59R },
|
||||
/* 0F 59 /wm */ { BxPrefixSSE, BX_IA_MULPS_VpsWpsM, BxOpcodeGroupSSE_0f59M },
|
||||
/* 0F 5A /wr */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWps, BxOpcodeGroupSSE_0f5a },
|
||||
/* 0F 5A /wm */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWps, BxOpcodeGroupSSE_0f5a },
|
||||
/* 0F 5B /wr */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdq, BxOpcodeGroupSSE_0f5b },
|
||||
/* 0F 5B /wm */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdq, BxOpcodeGroupSSE_0f5b },
|
||||
/* 0F 5A /wr */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWpsR, BxOpcodeGroupSSE_0f5aR },
|
||||
/* 0F 5A /wm */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWpsM, BxOpcodeGroupSSE_0f5aM },
|
||||
/* 0F 5B /wr */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdqR, BxOpcodeGroupSSE_0f5bR },
|
||||
/* 0F 5B /wm */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdqM, BxOpcodeGroupSSE_0f5bM },
|
||||
/* 0F 5C /wr */ { BxPrefixSSE, BX_IA_SUBPS_VpsWpsR, BxOpcodeGroupSSE_0f5cR },
|
||||
/* 0F 5C /wm */ { BxPrefixSSE, BX_IA_SUBPS_VpsWpsM, BxOpcodeGroupSSE_0f5cM },
|
||||
/* 0F 5D /wr */ { BxPrefixSSE, BX_IA_MINPS_VpsWpsR, BxOpcodeGroupSSE_0f5dR },
|
||||
@ -1129,8 +1129,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F E4 /wm */ { BxPrefixSSE, BX_IA_PMULHUW_PqQq, BxOpcodeGroupSSE_0fe4 },
|
||||
/* 0F E5 /wr */ { BxPrefixSSE, BX_IA_PMULHW_PqQq, BxOpcodeGroupSSE_0fe5 },
|
||||
/* 0F E5 /wm */ { BxPrefixSSE, BX_IA_PMULHW_PqQq, BxOpcodeGroupSSE_0fe5 },
|
||||
/* 0F E6 /wr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6 },
|
||||
/* 0F E6 /wm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6 },
|
||||
/* 0F E6 /wr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6R },
|
||||
/* 0F E6 /wm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6M },
|
||||
/* 0F E7 /wr */ { 0, BX_IA_ERROR }, // MOVNTQ/MOVNTDQ SSE group
|
||||
/* 0F E7 /wm */ { BxPrefixSSE, BX_IA_MOVNTQ_MqPq, BxOpcodeGroupSSE_0fe7M },
|
||||
/* 0F E8 /wr */ { BxPrefixSSE, BX_IA_PSUBSB_PqQq, BxOpcodeGroupSSE_0fe8 },
|
||||
@ -1788,10 +1788,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F 2C /dm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
|
||||
/* 0F 2D /dr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
|
||||
/* 0F 2D /dm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
|
||||
/* 0F 2E /dr */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
|
||||
/* 0F 2E /dm */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
|
||||
/* 0F 2F /dr */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
|
||||
/* 0F 2F /dm */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
|
||||
/* 0F 2E /dr */ { BxPrefixSSE, BX_IA_UCOMISS_VssWssR, BxOpcodeGroupSSE_0f2eR },
|
||||
/* 0F 2E /dm */ { BxPrefixSSE, BX_IA_UCOMISS_VssWssM, BxOpcodeGroupSSE_0f2eM },
|
||||
/* 0F 2F /dr */ { BxPrefixSSE, BX_IA_COMISS_VpsWpsR, BxOpcodeGroupSSE_0f2fR },
|
||||
/* 0F 2F /dm */ { BxPrefixSSE, BX_IA_COMISS_VpsWpsM, BxOpcodeGroupSSE_0f2fM },
|
||||
/* 0F 30 /dr */ { 0, BX_IA_WRMSR },
|
||||
/* 0F 30 /dm */ { 0, BX_IA_WRMSR },
|
||||
/* 0F 31 /dr */ { 0, BX_IA_RDTSC },
|
||||
@ -1856,7 +1856,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F 4E /dm */ { 0, BX_IA_CMOVLE_GdEdM },
|
||||
/* 0F 4F /dr */ { 0, BX_IA_CMOVNLE_GdEdR },
|
||||
/* 0F 4F /dm */ { 0, BX_IA_CMOVNLE_GdEdM },
|
||||
/* 0F 50 /dr */ { BxPrefixSSE, BX_IA_MOVMSKPS_GdVRps, BxOpcodeGroupSSE_0f50 },
|
||||
/* 0F 50 /dr */ { BxPrefixSSE, BX_IA_MOVMSKPS_GdVRps, BxOpcodeGroupSSE_0f50R },
|
||||
/* 0F 50 /dm */ { 0, BX_IA_ERROR }, // MOVMSKPS/PD
|
||||
/* 0F 51 /dr */ { BxPrefixSSE, BX_IA_SQRTPS_VpsWpsR, BxOpcodeGroupSSE_0f51R },
|
||||
/* 0F 51 /dm */ { BxPrefixSSE, BX_IA_SQRTPS_VpsWpsM, BxOpcodeGroupSSE_0f51M },
|
||||
@ -1876,10 +1876,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F 58 /dm */ { BxPrefixSSE, BX_IA_ADDPS_VpsWpsM, BxOpcodeGroupSSE_0f58M },
|
||||
/* 0F 59 /dr */ { BxPrefixSSE, BX_IA_MULPS_VpsWpsR, BxOpcodeGroupSSE_0f59R },
|
||||
/* 0F 59 /dm */ { BxPrefixSSE, BX_IA_MULPS_VpsWpsM, BxOpcodeGroupSSE_0f59M },
|
||||
/* 0F 5A /dr */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWps, BxOpcodeGroupSSE_0f5a },
|
||||
/* 0F 5A /dm */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWps, BxOpcodeGroupSSE_0f5a },
|
||||
/* 0F 5B /dr */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdq, BxOpcodeGroupSSE_0f5b },
|
||||
/* 0F 5B /dm */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdq, BxOpcodeGroupSSE_0f5b },
|
||||
/* 0F 5A /dr */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWpsR, BxOpcodeGroupSSE_0f5aR },
|
||||
/* 0F 5A /dm */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWpsM, BxOpcodeGroupSSE_0f5aM },
|
||||
/* 0F 5B /dr */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdqR, BxOpcodeGroupSSE_0f5bR },
|
||||
/* 0F 5B /dm */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdqM, BxOpcodeGroupSSE_0f5bM },
|
||||
/* 0F 5C /dr */ { BxPrefixSSE, BX_IA_SUBPS_VpsWpsR, BxOpcodeGroupSSE_0f5cR },
|
||||
/* 0F 5C /dm */ { BxPrefixSSE, BX_IA_SUBPS_VpsWpsM, BxOpcodeGroupSSE_0f5cM },
|
||||
/* 0F 5D /dr */ { BxPrefixSSE, BX_IA_MINPS_VpsWpsR, BxOpcodeGroupSSE_0f5dR },
|
||||
@ -2156,8 +2156,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F E4 /dm */ { BxPrefixSSE, BX_IA_PMULHUW_PqQq, BxOpcodeGroupSSE_0fe4 },
|
||||
/* 0F E5 /dr */ { BxPrefixSSE, BX_IA_PMULHW_PqQq, BxOpcodeGroupSSE_0fe5 },
|
||||
/* 0F E5 /dm */ { BxPrefixSSE, BX_IA_PMULHW_PqQq, BxOpcodeGroupSSE_0fe5 },
|
||||
/* 0F E6 /dr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6 },
|
||||
/* 0F E6 /dm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6 },
|
||||
/* 0F E6 /dr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6R },
|
||||
/* 0F E6 /dm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6M },
|
||||
/* 0F E7 /dr */ { 0, BX_IA_ERROR }, // MOVNTQ/MOVNTDQ SSE group
|
||||
/* 0F E7 /dm */ { BxPrefixSSE, BX_IA_MOVNTQ_MqPq, BxOpcodeGroupSSE_0fe7M },
|
||||
/* 0F E8 /dr */ { BxPrefixSSE, BX_IA_PSUBSB_PqQq, BxOpcodeGroupSSE_0fe8 },
|
||||
@ -2815,10 +2815,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F 2C /qm */ { BxPrefixSSE, BX_IA_CVTTPS2PI_PqWps, BxOpcodeGroupSSE_0f2c },
|
||||
/* 0F 2D /qr */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
|
||||
/* 0F 2D /qm */ { BxPrefixSSE, BX_IA_CVTPS2PI_PqWps, BxOpcodeGroupSSE_0f2d },
|
||||
/* 0F 2E /qr */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
|
||||
/* 0F 2E /qm */ { BxPrefixSSE, BX_IA_UCOMISS_VssWss, BxOpcodeGroupSSE_0f2e },
|
||||
/* 0F 2F /qr */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
|
||||
/* 0F 2F /qm */ { BxPrefixSSE, BX_IA_COMISS_VpsWps, BxOpcodeGroupSSE_0f2f },
|
||||
/* 0F 2E /qr */ { BxPrefixSSE, BX_IA_UCOMISS_VssWssR, BxOpcodeGroupSSE_0f2eR },
|
||||
/* 0F 2E /qm */ { BxPrefixSSE, BX_IA_UCOMISS_VssWssM, BxOpcodeGroupSSE_0f2eM },
|
||||
/* 0F 2F /qr */ { BxPrefixSSE, BX_IA_COMISS_VpsWpsR, BxOpcodeGroupSSE_0f2fR },
|
||||
/* 0F 2F /qm */ { BxPrefixSSE, BX_IA_COMISS_VpsWpsM, BxOpcodeGroupSSE_0f2fM },
|
||||
/* 0F 30 /qr */ { 0, BX_IA_WRMSR },
|
||||
/* 0F 30 /qm */ { 0, BX_IA_WRMSR },
|
||||
/* 0F 31 /qr */ { 0, BX_IA_RDTSC },
|
||||
@ -2883,7 +2883,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F 4E /qm */ { 0, BX_IA_CMOVLE_GqEqM },
|
||||
/* 0F 4F /qr */ { 0, BX_IA_CMOVNLE_GqEqR },
|
||||
/* 0F 4F /qm */ { 0, BX_IA_CMOVNLE_GqEqM },
|
||||
/* 0F 50 /qr */ { BxPrefixSSE, BX_IA_MOVMSKPS_GdVRps, BxOpcodeGroupSSE_0f50 },
|
||||
/* 0F 50 /qr */ { BxPrefixSSE, BX_IA_MOVMSKPS_GdVRps, BxOpcodeGroupSSE_0f50R },
|
||||
/* 0F 50 /qm */ { 0, BX_IA_ERROR }, // MOVMSKPS/PD
|
||||
/* 0F 51 /qr */ { BxPrefixSSE, BX_IA_SQRTPS_VpsWpsR, BxOpcodeGroupSSE_0f51R },
|
||||
/* 0F 51 /qm */ { BxPrefixSSE, BX_IA_SQRTPS_VpsWpsM, BxOpcodeGroupSSE_0f51M },
|
||||
@ -2903,10 +2903,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F 58 /qm */ { BxPrefixSSE, BX_IA_ADDPS_VpsWpsM, BxOpcodeGroupSSE_0f58M },
|
||||
/* 0F 59 /qr */ { BxPrefixSSE, BX_IA_MULPS_VpsWpsR, BxOpcodeGroupSSE_0f59R },
|
||||
/* 0F 59 /qm */ { BxPrefixSSE, BX_IA_MULPS_VpsWpsM, BxOpcodeGroupSSE_0f59M },
|
||||
/* 0F 5A /qr */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWps, BxOpcodeGroupSSE_0f5a },
|
||||
/* 0F 5A /qm */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWps, BxOpcodeGroupSSE_0f5a },
|
||||
/* 0F 5B /qr */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdq, BxOpcodeGroupSSE_0f5b },
|
||||
/* 0F 5B /qm */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdq, BxOpcodeGroupSSE_0f5b },
|
||||
/* 0F 5A /qr */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWpsR, BxOpcodeGroupSSE_0f5aR },
|
||||
/* 0F 5A /qm */ { BxPrefixSSE, BX_IA_CVTPS2PD_VpsWpsM, BxOpcodeGroupSSE_0f5aM },
|
||||
/* 0F 5B /qr */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdqR, BxOpcodeGroupSSE_0f5bR },
|
||||
/* 0F 5B /qm */ { BxPrefixSSE, BX_IA_CVTDQ2PS_VpsWdqM, BxOpcodeGroupSSE_0f5bM },
|
||||
/* 0F 5C /qr */ { BxPrefixSSE, BX_IA_SUBPS_VpsWpsR, BxOpcodeGroupSSE_0f5cR },
|
||||
/* 0F 5C /qm */ { BxPrefixSSE, BX_IA_SUBPS_VpsWpsM, BxOpcodeGroupSSE_0f5cM },
|
||||
/* 0F 5D /qr */ { BxPrefixSSE, BX_IA_MINPS_VpsWpsR, BxOpcodeGroupSSE_0f5dR },
|
||||
@ -3183,8 +3183,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
|
||||
/* 0F E4 /qm */ { BxPrefixSSE, BX_IA_PMULHUW_PqQq, BxOpcodeGroupSSE_0fe4 },
|
||||
/* 0F E5 /qr */ { BxPrefixSSE, BX_IA_PMULHW_PqQq, BxOpcodeGroupSSE_0fe5 },
|
||||
/* 0F E5 /qm */ { BxPrefixSSE, BX_IA_PMULHW_PqQq, BxOpcodeGroupSSE_0fe5 },
|
||||
/* 0F E6 /qr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6 },
|
||||
/* 0F E6 /qm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6 },
|
||||
/* 0F E6 /qr */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6R },
|
||||
/* 0F E6 /qm */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupSSE_0fe6M },
|
||||
/* 0F E7 /qr */ { 0, BX_IA_ERROR }, // MOVNTQ/MOVNTDQ SSE group
|
||||
/* 0F E7 /qm */ { BxPrefixSSE, BX_IA_MOVNTQ_MqPq, BxOpcodeGroupSSE_0fe7M },
|
||||
/* 0F E8 /qr */ { BxPrefixSSE, BX_IA_PSUBSB_PqQq, BxOpcodeGroupSSE_0fe8 },
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: fetchdecode_sse.h,v 1.17 2010-12-25 17:04:36 sshwarts Exp $
|
||||
// $Id: fetchdecode_sse.h,v 1.18 2010-12-26 20:41:47 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2005-2011 Stanislav Shwartsman
|
||||
@ -166,19 +166,31 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2d[3] = {
|
||||
/* F2 */ { 0, BX_IA_CVTSD2SI_GdWsd }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2e[3] = {
|
||||
/* 66 */ { 0, BX_IA_UCOMISD_VsdWsd },
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2eR[3] = {
|
||||
/* 66 */ { 0, BX_IA_UCOMISD_VsdWsdR },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2f[3] = {
|
||||
/* 66 */ { 0, BX_IA_COMISD_VpdWpd },
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2eM[3] = {
|
||||
/* 66 */ { 0, BX_IA_UCOMISD_VsdWsdM },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f50[3] = {
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2fR[3] = {
|
||||
/* 66 */ { 0, BX_IA_COMISD_VpdWpdR },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f2fM[3] = {
|
||||
/* 66 */ { 0, BX_IA_COMISD_VpdWpdM },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f50R[3] = {
|
||||
/* 66 */ { 0, BX_IA_MOVMSKPD_GdVRpd },
|
||||
/* F3 */ { 0, BX_IA_ERROR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
@ -268,15 +280,27 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f59M[3] = {
|
||||
/* F2 */ { 0, BX_IA_MULSD_VsdWsdM }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f5a[3] = {
|
||||
/* 66 */ { 0, BX_IA_CVTPD2PS_VpdWpd },
|
||||
/* F3 */ { 0, BX_IA_CVTSS2SD_VssWss },
|
||||
/* F2 */ { 0, BX_IA_CVTSD2SS_VsdWsd }
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f5aR[3] = {
|
||||
/* 66 */ { 0, BX_IA_CVTPD2PS_VpdWpdR },
|
||||
/* F3 */ { 0, BX_IA_CVTSS2SD_VssWssR },
|
||||
/* F2 */ { 0, BX_IA_CVTSD2SS_VsdWsdR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f5b[3] = {
|
||||
/* 66 */ { 0, BX_IA_CVTPS2DQ_VdqWps },
|
||||
/* F3 */ { 0, BX_IA_CVTTPS2DQ_VdqWps },
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f5aM[3] = {
|
||||
/* 66 */ { 0, BX_IA_CVTPD2PS_VpdWpdM },
|
||||
/* F3 */ { 0, BX_IA_CVTSS2SD_VssWssM },
|
||||
/* F2 */ { 0, BX_IA_CVTSD2SS_VsdWsdM }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f5bR[3] = {
|
||||
/* 66 */ { 0, BX_IA_CVTPS2DQ_VdqWpsR },
|
||||
/* F3 */ { 0, BX_IA_CVTTPS2DQ_VdqWpsR },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0f5bM[3] = {
|
||||
/* 66 */ { 0, BX_IA_CVTPS2DQ_VdqWpsM },
|
||||
/* F3 */ { 0, BX_IA_CVTTPS2DQ_VdqWpsM },
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
@ -692,10 +716,16 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fe5[3] = {
|
||||
/* F2 */ { 0, BX_IA_ERROR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fe6[3] = {
|
||||
/* 66 */ { 0, BX_IA_CVTTPD2DQ_VqWpd },
|
||||
/* F3 */ { 0, BX_IA_CVTDQ2PD_VpdWq },
|
||||
/* F2 */ { 0, BX_IA_CVTPD2DQ_VqWpd }
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fe6R[3] = {
|
||||
/* 66 */ { 0, BX_IA_CVTTPD2DQ_VqWpdR },
|
||||
/* F3 */ { 0, BX_IA_CVTDQ2PD_VpdWqR },
|
||||
/* F2 */ { 0, BX_IA_CVTPD2DQ_VqWpdR }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fe6M[3] = {
|
||||
/* 66 */ { 0, BX_IA_CVTTPD2DQ_VqWpdM },
|
||||
/* F3 */ { 0, BX_IA_CVTDQ2PD_VpdWqM },
|
||||
/* F2 */ { 0, BX_IA_CVTPD2DQ_VqWpdM }
|
||||
};
|
||||
|
||||
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fe7M[3] = {
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: ia_opcodes.h,v 1.57 2010-12-25 19:34:43 sshwarts Exp $
|
||||
// $Id: ia_opcodes.h,v 1.58 2010-12-26 20:41:47 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2008-2011 Stanislav Shwartsman
|
||||
@ -1009,8 +1009,10 @@ bx_define_opcode(BX_IA_CVTTPS2PI_PqWps, &BX_CPU_C::CVTTPS2PI_PqWps, NULL, BX_CPU
|
||||
bx_define_opcode(BX_IA_CVTTSS2SI_GdWss, &BX_CPU_C::CVTTSS2SI_GdWss, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPS2PI_PqWps, &BX_CPU_C::CVTPS2PI_PqWps, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTSS2SI_GdWss, &BX_CPU_C::CVTSS2SI_GdWss, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_UCOMISS_VssWss, &BX_CPU_C::UCOMISS_VssWss, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_COMISS_VpsWps, &BX_CPU_C::COMISS_VpsWps, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_UCOMISS_VssWssR, &BX_CPU_C::UCOMISS_VssWssR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_UCOMISS_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_COMISS_VpsWpsR, &BX_CPU_C::COMISS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_COMISS_VpsWpsM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVMSKPS_GdVRps, &BX_CPU_C::MOVMSKPS_GdVRps, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_SQRTPS_VpsWpsR, &BX_CPU_C::SQRTPS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_SQRTPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
|
||||
@ -1082,8 +1084,10 @@ bx_define_opcode(BX_IA_CVTTPD2PI_PqWpd, &BX_CPU_C::CVTTPD2PI_PqWpd, NULL, BX_CPU
|
||||
bx_define_opcode(BX_IA_CVTTSD2SI_GdWsd, &BX_CPU_C::CVTTSD2SI_GdWsd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPD2PI_PqWpd, &BX_CPU_C::CVTPD2PI_PqWpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTSD2SI_GdWsd, &BX_CPU_C::CVTSD2SI_GdWsd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_UCOMISD_VsdWsd, &BX_CPU_C::UCOMISD_VsdWsd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_COMISD_VpdWpd, &BX_CPU_C::COMISD_VpdWpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_UCOMISD_VsdWsdR, &BX_CPU_C::UCOMISD_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_UCOMISD_VsdWsdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_COMISD_VpdWpdR, &BX_CPU_C::COMISD_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_COMISD_VpdWpdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVMSKPD_GdVRpd, &BX_CPU_C::MOVMSKPD_GdVRpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_SQRTPD_VpdWpdR, &BX_CPU_C::SQRTPD_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_SQRTPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
@ -1097,13 +1101,20 @@ bx_define_opcode(BX_IA_MULPD_VpdWpdR, &BX_CPU_C::MULPD_VpdWpdR, NULL, BX_CPU_SSE
|
||||
bx_define_opcode(BX_IA_MULPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MULSD_VsdWsdR, &BX_CPU_C::MULSD_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MULSD_VsdWsdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MULSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPS2PD_VpsWps, &BX_CPU_C::CVTPS2PD_VpsWps, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPD2PS_VpdWpd, &BX_CPU_C::CVTPD2PS_VpdWpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTSD2SS_VsdWsd, &BX_CPU_C::CVTSD2SS_VsdWsd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTSS2SD_VssWss, &BX_CPU_C::CVTSS2SD_VssWss, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTDQ2PS_VpsWdq, &BX_CPU_C::CVTDQ2PS_VpsWdq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPS2DQ_VdqWps, &BX_CPU_C::CVTPS2DQ_VdqWps, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTTPS2DQ_VdqWps, &BX_CPU_C::CVTTPS2DQ_VdqWps, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPS2PD_VpsWpsR, &BX_CPU_C::CVTPS2PD_VpsWpsR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPS2PD_VpsWpsM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTPS2PD_VpsWpsR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPD2PS_VpdWpdR, &BX_CPU_C::CVTPD2PS_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPD2PS_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPD2PS_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTSD2SS_VsdWsdR, &BX_CPU_C::CVTSD2SS_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTSD2SS_VsdWsdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SS_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTSS2SD_VssWssR, &BX_CPU_C::CVTSS2SD_VssWssR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTSS2SD_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SD_VssWssR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTDQ2PS_VpsWdqR, &BX_CPU_C::CVTDQ2PS_VpsWdqR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTDQ2PS_VpsWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTDQ2PS_VpsWdqR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPS2DQ_VdqWpsR, &BX_CPU_C::CVTPS2DQ_VdqWpsR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPS2DQ_VdqWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPS2DQ_VdqWpsR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTTPS2DQ_VdqWpsR, &BX_CPU_C::CVTTPS2DQ_VdqWpsR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTTPS2DQ_VdqWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTTPS2DQ_VdqWpsR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_SUBPD_VpdWpdR, &BX_CPU_C::SUBPD_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_SUBPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_SUBSD_VsdWsdR, &BX_CPU_C::SUBSD_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
@ -1210,9 +1221,12 @@ bx_define_opcode(BX_IA_PSRAD_VdqWdq, &BX_CPU_C::PSRAD_VdqWdq, NULL, BX_CPU_SSE2,
|
||||
bx_define_opcode(BX_IA_PAVGW_VdqWdq, &BX_CPU_C::PAVGW_VdqWdq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMULHUW_VdqWdq, &BX_CPU_C::PMULHUW_VdqWdq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMULHW_VdqWdq, &BX_CPU_C::PMULHW_VdqWdq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTTPD2DQ_VqWpd, &BX_CPU_C::CVTTPD2DQ_VqWpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPD2DQ_VqWpd, &BX_CPU_C::CVTPD2DQ_VqWpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTDQ2PD_VpdWq, &BX_CPU_C::CVTDQ2PD_VpdWq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTTPD2DQ_VqWpdR, &BX_CPU_C::CVTTPD2DQ_VqWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTTPD2DQ_VqWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTTPD2DQ_VqWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPD2DQ_VqWpdR, &BX_CPU_C::CVTPD2DQ_VqWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTPD2DQ_VqWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPD2DQ_VqWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTDQ2PD_VpdWqR, &BX_CPU_C::CVTDQ2PD_VpdWqR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CVTDQ2PD_VpdWqM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTDQ2PD_VpdWqR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PSUBSB_VdqWdq, &BX_CPU_C::PSUBSB_VdqWdq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PSUBSW_VdqWdq, &BX_CPU_C::PSUBSW_VdqWdq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINSW_VdqWdq, &BX_CPU_C::PMINSW_VdqWdq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: sse_pfp.cc,v 1.71 2010-12-25 17:04:36 sshwarts Exp $
|
||||
// $Id: sse_pfp.cc,v 1.72 2010-12-26 20:41:47 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2003-2010 Stanislav Shwartsman
|
||||
@ -612,21 +612,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SI_GdWss(bxInstruction_c *i)
|
||||
* Convert two single precision FP numbers to two double precision FP numbers
|
||||
* Possible floating point exceptions: #I, #D
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2PD_VpsWps(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2PD_VpsWpsR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedMmxRegister op;
|
||||
BxPackedXmmRegister result;
|
||||
BxPackedMmxRegister op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
|
||||
}
|
||||
// use MMX register as 64-bit value with convinient accessors
|
||||
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -651,20 +644,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2PD_VpsWps(bxInstruction_c *i)
|
||||
* to rounding control bits in MXCSR register.
|
||||
* Possible floating point exceptions: #I, #D, #O, #I, #P
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2PS_VpdWpd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2PS_VpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedXmmRegister op, result;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), eaddr, (Bit8u *) &op);
|
||||
}
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -675,12 +658,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2PS_VpdWpd(bxInstruction_c *i)
|
||||
op.xmm64u(1) = float64_denormal_to_zero(op.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm32u(0) = float64_to_float32(op.xmm64u(0), status_word);
|
||||
result.xmm32u(1) = float64_to_float32(op.xmm64u(1), status_word);
|
||||
result.xmm64u(1) = 0;
|
||||
op.xmm32u(0) = float64_to_float32(op.xmm64u(0), status_word);
|
||||
op.xmm32u(1) = float64_to_float32(op.xmm64u(1), status_word);
|
||||
op.xmm64u(1) = 0;
|
||||
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -691,20 +674,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2PS_VpdWpd(bxInstruction_c *i)
|
||||
* to rounding control bits in MXCSR register.
|
||||
* Possible floating point exceptions: #I, #D, #O, #I, #P
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SS_VsdWsd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SS_VsdWsdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
float64 op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op = read_virtual_qword(i->seg(), eaddr);
|
||||
}
|
||||
float64 op = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -720,20 +693,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SS_VsdWsd(bxInstruction_c *i)
|
||||
* Convert one single precision FP number to one double precision FP.
|
||||
* Possible floating point exceptions: #I, #D
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SD_VssWss(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SD_VssWssR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
float32 op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op = read_virtual_dword(i->seg(), eaddr);
|
||||
}
|
||||
float32 op = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -751,20 +714,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SD_VssWss(bxInstruction_c *i)
|
||||
* to rounding control bits in MXCSR register.
|
||||
* Possible floating point exceptions: #P
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTDQ2PS_VpsWdq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTDQ2PS_VpsWdqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), eaddr, (Bit8u *) &op);
|
||||
}
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -786,20 +739,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTDQ2PS_VpsWdq(bxInstruction_c *i)
|
||||
* to rounding control bits in MXCSR register.
|
||||
* Possible floating point exceptions: #I, #P
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2DQ_VdqWps(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2DQ_VdqWpsR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), eaddr, (Bit8u *) &op);
|
||||
}
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -827,20 +770,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2DQ_VdqWps(bxInstruction_c *i)
|
||||
* truncation if the conversion is inexact.
|
||||
* Possible floating point exceptions: #I, #P
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPS2DQ_VdqWps(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPS2DQ_VdqWpsR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), eaddr, (Bit8u *) &op);
|
||||
}
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -868,20 +801,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPS2DQ_VdqWps(bxInstruction_c *i)
|
||||
* truncation if the conversion is inexact.
|
||||
* Possible floating point exceptions: #I, #P
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPD2DQ_VqWpd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPD2DQ_VqWpdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedXmmRegister op, result;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), eaddr, (Bit8u *) &op);
|
||||
}
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -891,12 +814,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPD2DQ_VqWpd(bxInstruction_c *i)
|
||||
op.xmm64u(1) = float64_denormal_to_zero(op.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm32u(0) = float64_to_int32_round_to_zero(op.xmm64u(0), status_word);
|
||||
result.xmm32u(1) = float64_to_int32_round_to_zero(op.xmm64u(1), status_word);
|
||||
result.xmm64u(1) = 0;
|
||||
op.xmm32u(0) = float64_to_int32_round_to_zero(op.xmm64u(0), status_word);
|
||||
op.xmm32u(1) = float64_to_int32_round_to_zero(op.xmm64u(1), status_word);
|
||||
op.xmm64u(1) = 0;
|
||||
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -907,20 +830,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPD2DQ_VqWpd(bxInstruction_c *i)
|
||||
* to rounding control bits in MXCSR register.
|
||||
* Possible floating point exceptions: #I, #P
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2DQ_VqWpd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2DQ_VqWpdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedXmmRegister op, result;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op = BX_READ_XMM_REG(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
readVirtualDQwordAligned(i->seg(), eaddr, (Bit8u *) &op);
|
||||
}
|
||||
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -930,12 +843,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2DQ_VqWpd(bxInstruction_c *i)
|
||||
op.xmm64u(1) = float64_denormal_to_zero(op.xmm64u(1));
|
||||
}
|
||||
|
||||
result.xmm32u(0) = float64_to_int32(op.xmm64u(0), status_word);
|
||||
result.xmm32u(1) = float64_to_int32(op.xmm64u(1), status_word);
|
||||
result.xmm64u(1) = 0;
|
||||
op.xmm32u(0) = float64_to_int32(op.xmm64u(0), status_word);
|
||||
op.xmm32u(1) = float64_to_int32(op.xmm64u(1), status_word);
|
||||
op.xmm64u(1) = 0;
|
||||
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), result);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -944,21 +857,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2DQ_VqWpd(bxInstruction_c *i)
|
||||
* Convert two 32bit signed integers from XMM/MEM to two double precision FP
|
||||
* Possible floating point exceptions: -
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTDQ2PD_VpdWq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTDQ2PD_VpdWqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedMmxRegister op;
|
||||
BxPackedXmmRegister result;
|
||||
BxPackedMmxRegister op;
|
||||
|
||||
/* op is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
|
||||
}
|
||||
// use MMX register as 64-bit value with convinient accessors
|
||||
MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
|
||||
result.xmm64u(0) = int32_to_float64(MMXUD0(op));
|
||||
result.xmm64u(1) = int32_to_float64(MMXUD1(op));
|
||||
@ -972,20 +878,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTDQ2PD_VpdWq(bxInstruction_c *i)
|
||||
* Compare two single precision FP numbers and set EFLAGS accordintly.
|
||||
* Possible floating point exceptions: #I, #D
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISS_VssWss(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISS_VssWssR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op2 = read_virtual_dword(i->seg(), eaddr);
|
||||
}
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -1007,20 +903,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISS_VssWss(bxInstruction_c *i)
|
||||
* Compare two double precision FP numbers and set EFLAGS accordintly.
|
||||
* Possible floating point exceptions: #I, #D
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op2 = read_virtual_qword(i->seg(), eaddr);
|
||||
}
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -1042,20 +928,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsd(bxInstruction_c *i)
|
||||
* Compare two single precision FP numbers and set EFLAGS accordintly.
|
||||
* Possible floating point exceptions: #I, #D
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISS_VpsWps(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISS_VpsWpsR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op2 = read_virtual_dword(i->seg(), eaddr);
|
||||
}
|
||||
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn()), op2 = BX_READ_XMM_REG_LO_DWORD(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
@ -1077,20 +953,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISS_VpsWps(bxInstruction_c *i)
|
||||
* Compare two double precision FP numbers and set EFLAGS accordintly.
|
||||
* Possible floating point exceptions: #I, #D
|
||||
*/
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISD_VpdWpd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISD_VpdWpdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2;
|
||||
|
||||
/* op2 is a register or memory reference */
|
||||
if (i->modC0()) {
|
||||
op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
}
|
||||
else {
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
/* pointer, segment address pair */
|
||||
op2 = read_virtual_qword(i->seg(), eaddr);
|
||||
}
|
||||
float64 op1 = BX_READ_XMM_REG_LO_QWORD(i->nnn()), op2 = BX_READ_XMM_REG_LO_QWORD(i->rm());
|
||||
|
||||
float_status_t status_word;
|
||||
mxcsr_to_softfloat_status_word(status_word, MXCSR);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user